Roland S-550 Operating and maintenance manual

JAN. 1988 S-550
S-B5D SERVICE NOTES First Edition
SPECIFICATIONS
DISK DRIVE
3.5" Micro Floppy Disk Drive :Double density Double Track (2DD)
SAMPLING SYSTEM
Sampling Rate :30KHz/15KHz
Data Format :12bits Linear
D/A Converter :16 bits
Sampling Time :7.2sec x4(lA, IB, IIA, IIB) @30KHz Sampling rate
:14.4sec X4(lA, IB, IIA, IIB) @15KHz Sampling rate
Wave memory :384K byte x4bank
INPUT MIC :-48dBm
LINE :—lOdBm
Recording Start Jack :OFF—SHORT
ON-OPEN
OUTPUT
MIX, 1—8 :+2dBm 1Voice max
DISPLAY OUT
RGB TTL LEVEL HORIZONTAL FREQ. 15.75KHz
MONOCHROME COMPOSITE IV P-P
EXT CONTROLLER
TTL LEVEL
DIMENSIONS
482 (W) x400 (D) x88 (H) mm
19" X15-3/4" X3-7/16"
WEIGHT
7.7Kg/17 lb.
POWER CONSUMPTION
32W
ACCESSORIES
Connection Cord (PJ-1)x 1
MIDI Cable 1m x1
System Disk x2\ in aset
Utility Disk x1jtwo
Mouse (MU-1)
Owner's manual
Guide Book for MIDI
(Part No. 23430675S0)
(Part No. 23485167)
(Part No. 22403129)
(Part No. 22433515)
OPTION
Remote Controller ;RC-100
RGB Connection Cable:
RGB 251 For 9pin sub
RGB Connection Cable:
RGB 25N For 8pin square
Pedal Switch DP-2, BOSS FS-5U
3.5" Micro Floppy Disk MF2DD
Sound Library Disks L-501 to 509
IRoland (2nd Printing Nov. 1988 B-2) Printed in Japan BA-2LH 1
TABLE OF CONTENTS Sda Page
LOCATION OF CONTROLS
EXPLODED VIEW
MOUSE (MU-1)
PARTS LIST
BLOCK DIAGRAM
CIRCUIT DESCRIPTIONS
CHECKING AND ADJUSTMENT
CHANGE INFORMATION
POWER SWITCH BOARD
POWER SUPPLY BOARD
SWITCH BOARD
JACK BOARD
CPU BOARD
ANALOG BOARD
RGB CABLE
RGB OUT TIMING CHART
1C DATA
2
3
4
4,5
yny'^m 6
7-11
11-15
15
16
/N“7—tt77T.1f-K 16
17
17
CPU-T-K 18-21
22
RGB'^-7)U 23
23
ICx-7 24,25

S-550 JAN. 1988
LOCATION OF CONTROLS
Pot.
12(6VR EVJFSAF15B14
13279844
Knob RED
22485162
Jack (mono)
YKB21-5011
13449149
Switch
SPEA12125A
13129344
Bottom BLK
22470637
LED RED
SLR55VC3F
15029222
Roland S-ESDbICSTTAl- SAN/IPL-ER
REC 1.EVE -
-FIP 16A5GR
15029717
FCD Cover
22043117
o
PLAY
MO
EDTT
RJNC
CD
DISK
CD
UTILrTY
CD
MENU Ao
SUB
MENU
Vo-
CD
COMMAND
D
EXECLTTE
p/|rA ENTRY-
m
Button Assy
22475667
Key Switch
SKHHAR
13129737
ENTTER SPACE
Floppy Disk Drive Unit
FDD4261AOK
12379535 LED GRN
SLR55MC3F
15029224
o
MIDI MESSAGE
A
POWER
o
D-Sub 9pin
DELC-J9PAF-1L8
13439339
Button Assy C
22493534
Jack (stereo)
YKB21-5009
13449148
*Button Assy A
22493532
Pot.
12«iVR EVJFSAF15B14
13279844
Knob BLU
22485166
Button Assy B
22493533
Button Assy
22475669
Key Switch
SKHHAR
13129737
LED RED
SLR55VC3F
15029222 Switch
SDDG 3078A
13129124
Button BLK
22470240
Key Switch :SKH HBS 13129733
LED :LED GL-9HD12 red 15029152
2

JAN. 1988 S-550
f<T.
EXPLODED VIEW HWm
1. 22813599 Subchassis
2. 22193987 Front Holder
3. 22213563 Rear Panel
4. 22213562 Front Panel
5. 22193988 Jack Board Holder
6, 22203119 Disk Drive Holder
7, 22195999 Power Switch Holder
8. 22025364 Top Cover
9. 22463502 Heat Sink
10. 22125586 Rack Mount Angle
11. 22023201 Bottom Cover
12. 22023362 SCSI Cover
13. 79380190 Switch Board
14. 79380230 Jack Board
15. 79380160 Analog Board
16. 79380221 Power Switch Board 100/117V
79380224 Power Switch Board 220V
79380225 Power Switch Board 240VE/A
17. 79380211 Power Supply Board 100/117V
79380214 Power Supply Board 220/240v
3x8mm binding B-tight
3x6mm binding BLK
3x6mm binding B-tight BLK
36. 22493532 BUTTON ASSY A
37. 22493533 BUTTON ASSY B
38. 22493534 BUTTON ASSY C
3x6mm binding B-tight BLK
3x6mm binding
3

ON
Ln
4S
Lo
S-550 JAN. 1988
MOUSE (MU-1)
MOUSE (MU-1) Assy 22433515
1CABLE 23483216
2Button Cover 22043137
PCB Assy 22923571
CASE 22013214
Coating Ball 22173747
Retainer 22133423
PARTS LIST
CASING
22025364 Top Cover 202-364
22023355 Bottom Cover 202-355
22125586 Rack Mount Angle 212-586
22023362 SCSI Cover 202-362
22213562 Front Panel 221-562
22193987 Front Holder 219-987
22213563 Rear Panel 221-563
22813599 Subchassis 281-599
KNOB, BUTTON
22470240 Button POWER
22470637 Button LINE/MIC
22493532 Button Assy APLAY, EDIT, DISK, MIDI, FUNC, UTILITY
22493533 Button Assy BMENU.,A,SUB MENU, ,T.
22493534 Button Assy CCOMMAND, EXECUTE
22485162 Knob (red) REC LEVEL
22485166 Knob (blue) VOLUME
22475667 Button Set of 4in acolumn in DATA ENTRY
excluding the button 0-+*.
22475669 Button 0-+*
SWITCH
13169633 SKH HAD039A CPU board
13129733 SKH HBS panel board
13129737 SKH HAR panel board
13129344 SPEA 12125A panel board
13129124 SDDG 3078A POWER
JACK, SOCKET
13429168 MIDI 3-NS MIDI
13449149 YKB 21-5011 (mono) INPUT, REC/START, MIX OUT
13449622 YKB 11-0252 MONOCHROME
13429640 TCS 4680-01-1111 (8P DIN) DIGITAL RGB
13449157 HLJ 2335-01-3000 INDIVIDUAL OUT
13449148 YKB 21-5009 (stereo) PHONES
POWER TRANSFORMER
22453489 245-489 lOOV
22453490 245-490 117V
22453491 245-491 220V
22453492 245-492 240V
INDUCTOR
12449251 DC-DC Converter
12449306 PFB-3 fc=14.5KHz LC filter
22445304 PFB-3 fc=13.7KHz LC filter
12449244 SC-02-15E line filter
22445240 BLO 2RN2-R62 ferrite beads
13529156 ZJSC-220-101 EMI filter
13529158 ZJSC-2R2-101 EMI filter
RESONATOR
12389738 CSB 400P (ceralock)
12389744 HC-49/U 8MHz (crystal)
12389758 HC-49/U 14, 3496MHz (crystal)
12389778 HC-49/U 20MHz (crystal)
12389759 HC-49/U 24MHz (crystal)
12389760 HC-49/U 26.880MHz (crystal)
PCB ASSY
79380120 CPU Board (pcb 22923493)
79380160 Analog Board w/f liter cover A &B(pcb 22923494)
79380200 Switch Board w/LED board (pcb 22923492)
79380211 Power Board 100/ 117V (pcb 22923495)
79380214 Poewr Board 220/240V (pcb 22923495)
79380221 Power Switch Board 100/ 117V (pcb 22923503)
79380224 Power Switch Board 220V (pcb 22923503)
79380225 Power Switch Board 240VE/A (pcb 22923503)
79380230 Jack Board (pcb 22923492)
POTENTIOMETER
13299193 EVN-D4AA00 B54
13279844 EVJFSAF 15B14 (rotary ill)
13299201 EVN-D4AA00 B53
TRANSISTOR
15119106DR 2SA 933R
15129613 2SD 1207S
15129114 2SC 1815GR
15119129 2SA 1115E
15129140 2SC 2603E
15129136 2SC 2878A
151291300G 2SC 1583G
15119601 2SB 605L
15129606 2SD 844Y
15129150 DTC-114 w/built in resistors
4

JAN. 1988
_ic
15229874
15179246
15229846
15229887
15219158
15179385
15219173
15229861
15179201
15229884
15229883
15219171
15229873
15179856
15199109N0
15179364
15179386
15169514B0
15169548B0
15169552B0
15169555B0
15169544B0
15169560
15229706S0
15219174
15189111P0
15189193
15189186
15219157
15189150
15189197
15199133
15199134
SA-16
or 15229840
18095-90
UPD 65006CW-071
M60011-0125SP
WD1772-02
SRM20256LC12
IMS 3556NL
M6003A-0117SP
yPD 7537C-014
TVF 16
MB 654419U
EHK-MD 6209
BU3905S Rll-0006
LH57128-20
IJPC 78L05
TMS 4464-15NL
M5M 44C256P-12
M74HC 04P
M74HC 14P
M74HC 245P
M74HC 393P
M74HC 573P
TC 74HC 123P
PC910
NJU 201AD
IR-9311
M5238P
PPG 4570C
M5241 L
M5220 L
NJM 5532D
AN 7815F
AN 7915F
wave gate array
RF5C36 wave gate array
CPU
I/O gate array
I/O gate array
floppy disk controller
S-RAM
video display processor
SW scan control gate array
4-bit N-MOS CPU
TVF gate array
TVF interface gate array
16-bit D/A converter
output assign gate array
one time P-ROM
+5V regulator
D-RAM 64Kx4
D-RAM 256Kx4
hex inverter
hex inverting schmitt trigger
octal 3state tranceiver
dual 4-Bit binary counter
3state octal D-type latch
dual retriggerable monostable multivibrator
optoisolator
analog switch
conparater
OP amp
OP amp
VGA
OP amp
OP amp
+15V regulator
+15V regulator
FLOPPY DISK DRIVE UNIT
12379535 FDD4261A0K
or 22405156 FDD4251G0K
DIODE, LED
15019323
15019324
15019143
15019125
15019208
15029222
15029224
15029152
15029717
15019275
15019274
04AZ 9. IX
04AX 39X
lSS-116
lSS-133
lSR-35-200
SLR55VC3F
SLR55MC3F
GL-9HD12
FIP 16A5GR
3B4B41
D5FB-20
LED red
LED green
LED red
CAPACITOR
13659216M0 ECES lEU 682K
13529104 DE 7150F 472MVA1
13529108 Rpe 132f 104Z 50
panel board, CPU board
panel board
panel board
Rectifier Bridge
Rectifier Bridge
Line bypass
Ceramic
RESISTOR
13919310 RMLS 8-103J
13919118R0 RKM lOL 104F
13819261
12559817 1/2W 470Kfi
ERQ-16NKR 15E (fuse resistor)
FUSE, FUSE CLIP
12559404 TSC 4A
12199550 HO 446 (fuse clip)
12559555 CEE T5A
12559410 T-GGS 5A
CONNECTOR HOUSING
13429192 PS-40PE-D4T1-B1
13439371 5483-03AX
13439372 5483-04AX
13439373 5483-05AX
13439374 5483-06AX
13439375 5483-07AX
13439376 5483-08AX
13439380 5483-12AX
13439330 IL-S-3P-S2T2-EF
13439345 IL-S-9P-S2T2-EF
13439298 IL-S-10P-S2T2-EF
13439331 IL-S-11P-S2T2-EF
13439336 IL-S-12P-S2T2-EF
13439337 IL-S-13P-S2T2-EF
13439339 IL-S-15P-S2T2-EF
13429193 DELC-J9PAF-1L8
13439306 5566-06A
13429172 5219-03A
100/117V
220/240V
100/117V
D-Sub 9pin
wafer assy
23483216 Cable
22043137 Button Cover
22923571 PCB Assy
22013214 Case
22173747 Coating Ball
22133423 Retainer
5

S-550 JAN. 1988
t±Zi
BLOCK DIAGRAM
RGB
Iwl
OMIX
1OUTPUT
6

JAN. 1988
CIRCUIT DESCRIPTIONS
Features
The S-550 is a16-voice digital sampler having expanded
16-bit capability (sampling data 12-bit ). The major
features are as described below:
.Employes TVF (Time Variant Filter) and TVA (Time
Variant Amplifier) for versatile sound creation
.Four wave banks, each with the maximum sampling
time of 7.2 sec (sampling frequency at 30kHz)
.Accommodates an optional mouse and remote control-
ler RC-100
.Equipped with 8individual channel outputs
.SCSI (Small Computer System Interface) mountable
.Editable from the CRT screen
ussKin
S-55 h16k" -V h(-th y:7° ij y
T-' -^12k-y h),16iy ^yy°y-
Vimm
•TVF(Time Variant Fil ter )^TVA(Time
Variant Amplifier )J: 0x^
•ij y^"4? TA7. 2# (gy
3OKHzP#)
•fyj-jgCD-^ g-t— h3yha—7RC—10 0
•8CHCDT Tg? hV° -V h^(i
•SCSI (Small Computer System Interface)'
•CRT'&^^L^ h:6Snr|go
Control Section
The main CPU 8095 covers and manages the following
functions and devices.
.Transfer of MIDI messages
.Wave gate array SA16 (or RF5C36)
.Floppy disk controller (FDC) WD1772
.Video display controller (VDD) TMS3556
.FIP CPU MPD7537C
.Gate array M6003A used for switch scanning and LED
driving
.TVF interface gate array MB654419V
.Output assigner gate array BU3905S
.I/O gate arrays juPD65006 and M6001
1
mm'im
y4yCP 809 5/)T^ffl$tlTfc 0. TIB® CD
•MIDI^-y -k -iyCDM^M
•g7x-7"/r'-h TUT SAl 6( X^.CRF5C3 6)
•7D-y k° -X ^y^nyho-y( FDC )WDl 77 2
•k'xXxX 77°uT=tyhD-7 (VDP) TMS3 55 6
•FIPIICPU /^PD753 7C
•SW7+-V7. LED,i^iTfflT"- hTUT M6 0 0 3A
•TVF Ty7-7 XTXT'- bTUT MB6 5441 9U
•T7b7°-y hr-g-T yy-
h
TUT BU390 5S
•I/OT"-bTUT /^PD650 0e;^CKM600 1 1
Waveform Data Memory Section
Stores input waveform data into 12 1Mbit DRAMs
through the wave gate array SA-16 (or RF5C36).
System Operation
•Software
System software is to be supplied externally from the
floppy disk. System bootstrap (initialization) program
and fundamental subroutines are firmware stored in
the internal ROMs. Fig. 1shows the flow of the system
initialization program.
mmmwM
7X-7"T"- hTUT SA-1 6(X(4: RF5C3 6)yj; 0A
-7T1Mk"-y hCD DRAM 12fglcliB'lt^ fT
•VXh'^xT
yXXA77b7XT7a-y k°-x ^X7IC J; 0
yxxACDloffl
i^S7°n 7"x AS,ib':S:A7-7".^ly —tlTt/''
ROMpScD'yxxA|Uffl5^$T°D7"xACD$(ttlT
Fig. 1
s-550
•Reset
Two kinds of reset signal will be issued as necessary by
software and by hardware.
They are:
RST1 .... By hardware on power-up
RST2 .... By software This will cause alow level
signal from pin 63 of IC1 1,juPD65006.
These reset signals are routed to the respective destina-
tions as listed in Table 1.
•'J-b-yh
g-k-y b/N- b" 7X('l/HSAP# )icy
AT RSTl t. V7b7XTT'3 yhp—tlT A
AT(IC11 /^PD65 00 6(D 63#k“yA7tBTJ^tl
T)RST2 iCD 2hS
TnXncDjf.^5*c{4:Table. UD'M^Vi-o
RST 1Destination RST 2Destination
IC9 [18095]
IC10[M600 11
]
IC12[WD1 772 ]
IC17[M6003A]
IC35[ /CPD7537C]
IC28[ SA-16(X(iRF5C36) ]
IC29[ MB65 441 9U]
TXy3yy- k3^77 -cni
(Table 1)
Flow of Initialization Program Resides in ROM ROMp'4'y7xA^T^f^®7°n7'xA9jf4^
(Fig. 1)
7

•Reading program and data from disk
(Fig. 2) CPU BOARD 1>2,4,5 ICs 37 —48
SRAM DRAM
The wave data is stored into DRAMs (ICs 37—48)
while the system program and parameters are into
SRAMs (ICs 1,2, 4and 5).
'&?^-T-"-^{iDRAM (ICS 7—48)-v, A7°a
^"7 A*^'tCDftb®>^°7P^-^{iSRAM( IC 1,2,4,
5)
•Sampling input signal (in REC mode) •A^fi^(D-9->7V>^(REC0#)
OUTPUT
INPUT
The input signals will be converted into digital
equivalents through the A/D converter consisting of
the wave gate array (IC28), DAC (IC31) and com-
parator (IC33). The ADC is asuccessive approximation
type and sends the results to DRAMs (ICs 37—48).
During sampling in REC mode, the TVF gate array
(IC29) is limited to function as transparent path i.e.
it relays the data from the wave gate array as it is to
the DAC for the A/D system to compare with input
signals.
The CPU IC9 monitors the input level through the
wave gate array and sends the information via VDP
(IC21) to VRAMs (ICs 25 and 26) which indicate the
level on the screen.
^X-y/r"- hT UT (IC2 8),D/A ^IC
31), 3(IC3 3)-ClEJXtb^SiCDA/D 3
Atf®^{iC(DA/D 30/y 'y ^
DRAM( IC3 7-4 8)
yy7°ij >/'( REC^) TVFT >/-7xT xy- br
L-T (IC29)Ei, b^x -7'V— h16 t" -y
h5^^D/ A37/<
—
^(IC31)
CPU( 1C9 )(i, 7x-7"y-hTU4 INPUT
VRAM( IC2 5,26){s: -
S-550 JAN. 1988
•Sound Reproduction (PLAY mode) •/J$fl^PI^(PLAYB#)
1. Wave Data from DRAMs (ICs 37-48) 1.DRAM(IC37-48);(?'b(D>J^ff^x-^Ji£ii
When the CPU (IC9) aquires MIDI IN note, it
constructs information concerning note, envelope
and loop and routes them to the wave gate array
(IC28).
Using this envelope data, the wave gate array com-
putes along with a12 bit wave data obtained from
DRAMs (IC37— IC48) to have an expanded 16 bit
wave data which is to be applied to TVF interface
gate array (IC29).
2. TVF (IC27) and TVF Interface Gate
Array (IC29)
CPU (IC9 MI DI IN/)^
NOTE, ENVELOPE, LOOP CD# 'If
fg ^/X-7"y- bTUT (IC28)IC y) LT3^ 0
/X-7"/"- hTUT (i, DRAM( IC3 7-4 8)
12bit CD'^fj^/'— 7itlfSCD
ENVELOPE L, 16 bit CDt’" —
^tfz, Ctl^T VET y7-7x 4
7/r"-h TUT (IC2 9) fcmbt-to
2.TVF(IC27)TVFie;^t>TVFO^-7i<7>5r'-h
TK(IC29)MB654419U
The IC29, once gets 16-bit wave data from IC28,
sends unique data to the TVF (IC27), consecutively
on each INH signal.
The TVF conditions wave data in response to
tone parameters and sends "filtered" waveform
data back to the TVF where they are sent to
the DAC to become an actual sound.
/x-7"/"- hTU4 (IC2 8)
bi tCDi^My- TVFTy7-7xT X/r"- b
TUT (IC29) INH(t^E<:mgLTTVF
(IC2 7)^mihtl^i-o
TVFVli, b-y^^“7
5J; h,7^7 ^31/7
y^li, HCKTVFTy
7-7 X4X/"- hTUT {C /h,D/A3Xys'-
7(IC31
8

JAN. 1988 S-550
3. Output Assignee Gate Array BU3905 (IC49) 3.7^^ N7°'y hTK(IC49)BU3905
The TVF interface sends 16 voice data (each of 16
bit) in time-division fashion. After D/A converted,
each of two consecutive voice pairs is gated into an
individual output circuit in the same time slot. The
output assigner determines the output channel
according to assign information given by the CPU.
TV FT X/r"- hTL-T (IC29)b
(16f'-v 16-T'T
ti. D/A3 (IC3 1)
D/A 3yy'f—
2
>-T'T 1LTT h^fij
'O^X
<J;CDrh'T X^°T^ 18CD<J;(7)Tt> h
itr /h7°-v hT-fl-T x/r"- hTUT (IC4 9)/)\
CPU (IC9
Disk Read/Write
(Fig. 7)
On aread or write command from the CPU, the FDC
pulls MOTOR ON low to let the FDD (Floppy Disk
Drive) starts the motor. When the motor running has
reached stable condition, the FDD signals the CPU
through I/O gate with alow READY. The low READY
allows the CPU to issue acommand which enables read-
ing or writing to/from the disk.
In the read mode the FDC reads data from FDD in serial
format and sends it to the CPU in parallel 8bits.
In the write mode the FDC first pulls and keeps WG high
and then places adata on WD line.
FDCfSCPU/}^^ 'j- KXfixT !>
FDD(7n-7 t° —T-'X X7KXT7" )1/ T
MOTOR
Xo
FDD{S^-7-CD0fe/;JXS-ri)c!:> CPU(C READY
I/O/r'— hT/T^^bXMO ^~to
CPU READY11-^ ^
i
<J -KPt. FDC RDi^-T-J: hFDD/}i (7)/ Ij
bCPUfC^b^-To
xT h0#F DC^WGft^^High
WD^X^ilUTx-"-7 ^FDD{C*^3A7^^-ro
FDC Pin Description (Table 2)
PIN
NUMBER MNEMONIC SIGNAL NAME I/O DESCRIPTION
1CHIP SELECT 1Alogic low on this input selects the chip and enables Host communication
with the device.
Low LevelT'CPUtCOLlSi” Y—'>3>*'"5jHElL4'0St"o
2R/W READ/WRITE 1Alogic high on this input controls the placement of data on the D0-D7
lines from aselected register. While a logic low causes awrite operation to
aselected register.
High LeveLv-f h-X TYYC7)L#U Low Level IZLttr,
3, 4AO, A1 ADDRESS 0, 11These two inputs select aregister to Read/Write data:
>:Ji:lLfF-rJ:9lL.Y(7)20(7)AY(CJ:oT'J-K,*Al47Th-X'1'7tKL*t-f?>FDCrtg|5
CS A1 AO R/W=1R/W=0
000Status Reg Command Reg
001Track Reg Track Reg
010Sector Reg Sector Reg
01 1 Data Reg Data Reg
5-12 DAL0-DAL7 data access lines
0THROUGH 7
I/O Eight-bit bi-directional bus used for transfer of data, control, or status. This
bus is enabled by CS and R/W. Each line will drive one TTL load.
8bitO-Y'-tSr-A'XT.Y'-tXD'POirClLfeffl^nS-ro
13 KM MASTER RESET Alogic low pulse on this line resets the device and initializes the Status
Register (internal pull-up).
Low Leveir\FDC^0-lz-vbLStc
14 GND GROUND Ground. lt;®77>Klc}g|iU*'To
15 Vcc POWER SUPPLY 1-t-5V ±5% power supply input. -F5V^)ig(LfgML$'To
16 STEPP STEP 0The Step output contains apulse for each step of the drive's R/W head.
17 DIRC direction 0The Direction output is high when stepping in towards the center of the
diskette, and low when stepping out.
xVY7 •KxTX(D^-y KSHigh LevelTx-fY2CD Low LevelT'x-rXYCO^'f
fflU ^XXVXS-tf -5 A»CO [S] sISg; L*To
18 CLK CLOCK 1This input requires afree-running 507o duty cycle clock (for internal timing)
at 8MHz ±0,17o.
8MHz ±0.1% 50%xx-x-f±'rC7tKO'7P y2®AYlLT-ro
19 READ DATA 1This active low input is the raw data line containing both clock and data
pulses from the drive.
x-rXY -HxTXA’Dx— SttSTo
20 MO MOTOR ON 0This active high output turns on the motor,
x-f X7 KxTXco±-7SSi]WL^-r,.
21 WG WRITE GATE 0This output is made valid prior to writing on the disk.
x-fX2 -x— JAti'tSlL High Level ICYOSTo
22 WD WRITE DATA FM or MFM clock and data pulses are placed on this line to be written on
the diskette.
X—7$:x'fX'7 •F'xYXYjMDSt'
23 TROO TRACK 00 1This active low input informs the WD1 770-00 that the drive's R/W heads
are positioned over Track zero (internal pull-up).
Fx yTsi iffS-^-SSltST ,Low Level (DLSx-rXY- Kx'fXcO^ yKYx-fX'T CO®
6^ffiULf4BLSY„
24 IP INDEX PULSE 1This active low input informs the WD1 770-00 when the physical index hole
has been encountered on the diskette (internal pull-up).
'r>X'y7Xft-§-S®H*t'„TC0fi-§^(Tx-rX2Y"l(e]te-T5C'tlCxVX7-Kx-TX>b
25 WPRT WRITE PROTECT 1This input is sampled whenever aWrite Command is received. Alogic low on
this line will prevent any Write Command from executing (internal pull-up)
X'rF-XP±2hfl-§-$®ltSr .CCOfS^li.x-rXYlCxTb-XPAYhY'A'YxTL'-S
tgiLxVxx-Kx'rXYDisE.nrs^-r.,
26 DDEN DOUBLE DENSITY
ENABLE 1This input pin selects either single (FM) or double (MFM) density.
When DDEN =0, double density is selected (internal pull-up).
High Level T#®®(FM)(L. Low Level Tf^S'®(MFM)lL|S:®^n*1-o
27 DRQ DATA REQUEST 0This active high output indicates that the Data Register is full (on aRead)
or empty (on aWrite) operation.
C<OtfJ*(OSL-t±Y'HTx-X-L'vXXY'J-K<75t#li7tU.x-Tb(Ot#l4x>'7±<
28 INTRO INTERRUPT REQUEST 0This active high output is set at the completion of any command or reset
at aread of the Status Register.
CCD tii ±®ArT.±YHT\PX>KcD CPUlLjPb-t+*-r„
9

S-550 JAN. 1988
Video Display Processor
(VDP) TMS-3556 TMS3556
CPU BOARD ,/
^CHARAC-
TER
DATA
BIT MAP
DATA
1bit 1dot
(Fig. 9)
The figure 9below shows the block diagram of the VDP,
IC74 and associated circuits. The VDP operates either of
TEXT and BIT MAP modes.
VD PWjHaT' P^0^ Fig. 9
•Text Mode
In the text mode the CPU sends the VDP acharacter
code and the coordinates of the character on the
screen. The VDP fetches the character pattern data
from the VRAM character area and displays the
character in a10 by 8dot matrix on the 21 row by 40
character screen.
•Bit Map Mode
The VRAM bit map area is divided into three portions,
each corresponds to color R, G, or Bof 320 by 210
dot matrix on the screen. When in this mode, the CPU
writes image data into the bit map area. The VDP dis-
plays pixel by pixel with specified color.
•T+:^h^-K
CPU^^
-
K
•lT'yhTy7°^-K
R,G,B—I'y-h
(320X210K-j; h)(?:) 1K•;/ h^VRAM t"
h1h" -.V hb^btz
CP U:;6^'VRAM(Z) V-y —
^J: 0. K-;;
VDP Pin Description (Table 3)
SIGNAL
NAME PIN NO. I/O DESCRIPTION SIGNAL
NAME PIN NO. I/O DESCRIPTION
VGG 1IPower Supply; -t-S.ZV
+5V®>I MP3 AO I/O CPU-VDP Data Bus
CPU-VDPx-T'A'v'X
MPA 2I/O CPU-VDP Data Bus
CPU-VDPx-^'wU MP2 39 I/O CPU-VDP Data Bus
CPU-VDEx-X'/U
MP5 3I/O CPU-VDP Data Bus
CPU-VDPx-^J-/U MPl 38 I/O CPU-VDP Data Bus
CPU-VDPx-7-/SX
MP6 AI/O CPU-VDP Data Bus
CPU-VDPx-3?-/X MPO 37 I/O CPU-VDP Data Bus (MSB)
CPU-VDPx-7-/S'x(MSB)
MP7 5I/O CPU-VDP Data Bus (LSB)
CPU-VDPx-^!-yU(LSB) SCM 36 0 Composite Sync
P>*"V7bin ft§tU tJ
CAS 60Column Address Strobe
=17A•Xb-7ft§B35 0 B
RAS 70Row Address Strobe
'7 •XHVX •7hP-7ff-§ G3A 0G
Gfl-§-ll!7l
WR 80Memory Write R33 0 R
OE 90Memory Output Enable
^^U-X7hX7b-ft--77Hf-§ I32 0 Display Mode Select
HIZ 10 0Not used SLL 31 I/O Horizontal Sync
RWM 11 ICPU-VDP Write
CPU-VOP^YHi^ SCT 30 I/O Vertical Sync
BMP 12 INot used, pulled up to -i-5 .2V
fifflL4x\,4-5VlcXltX77”t2>o OBS 29 0Time Base Clock Xtal
7-f A-/x-X
iA•/\-X •7y7
)
ODS 13 0DMA clock Xtal
(Memory Access Timing)
.><^U-X7-b7-7'r5>7'fflllli)T
lgii^yffi^(DMA7P77)
OBE 28 I
ODE lA IE2 27 IVDP Access Control
VDP-X7-U7 -PAba-^Hf^
READY 15 0VDP Ready
VDPUx-i'fs"§' El 26 IVDP Access Control
VDP-X7-tr7-P>bP-7Uft^
D7 16 I/O VDP-Memory Address/Data Bus (LSB)
VDP-y^U-XKUX/x-^ •A'7(LSB) DO 25 I/O VDP-Memory Address/Data Bus (MSB)
VDP-y<^ ij -XbVX/x-^ •A'X(MSB)
D6 17 I/O VDP-Memory Address/Data Bus
VDP-yLU -XbVX/X-^ •AX D1 2A I/O VDP-Memory Address/Data Bus
VDP-7^U-XbVX/x-7-AX
D5 18 I/O VDP-Memory Address/Data Bus
VDP-yLU-XbV7/X-7-A'X D2 23 I/O VDP-Memory Address/Data Bus
VDP-;><LiJ-XbVX/x-7-A'X
DA 19 I/O VDP-Memory Address/Data Bus
VDP-yLiJ-XHV7/x-X-/<X VDD 22 IPower Supply: +3V
D3 20 I/O VDP-Memory Address/Data Bus
VDP-yLU-XKU7/x-7-AX VSS 21 IGND GND
VDP TMS3556 BLOCK DIAGRAM
I/O Gate Array AtPD65006-017 (ICII)
Figure 11 shows an internal block diagram of the Gate
Array. The controller generates various control signals
which determine the operational timings of most of the
system stages.
The /iPD65006-01 7, in addition to many I/O parts, has
the ports for interfacing with the mouse (MU-1) and
remote controller (RC-100).
EXT CONTROLLER Socket
This socket enables communications with asynchronous
serial format. The pin assignment is as shown below.
I/O /^PD65006-017(IC11)
-v i:^gj^Fig. 1
4?— h&CKnX ha—yLTis f) uxhp—
-7 T> X(MU-1)Ij hPXpP
-x(RC-l 00 )cDTx^-XiT xcD|9;fiJ^
5^Vy^-r-ti^'[EXT CONTROLLER]ffi!ffl5^
vt>x(MU- 1)X(i Ij^-t'^xka-x (RC-100)
iX'J TOfzisb (Dm^x to
Table 4(C^L^-ro
(Table 4)
EXT CONTROLLER SOCKET PIN DESCRIPTION
Pin No. Pin
Designation Function when connecded to MU-1
MU-1 I/O Function when connected to RC-100
RC-100 I/O
1MXO UP 1
Data input from RC-100
RC-100*>GCOx-7$A7lT4 1
2MX! DOWN 1
ATN Ready Signal input from RC-100
(AHENTION) RC-100*'6Wmfii1t-§SA7lt5 1
3MX2 LEFT 1GROUND •••
4MX3 RIGHT 1GROUND ...
5-H5.2V -f5.2V ... -1-5. 2V...
6MX4 LEFT SW 1
Sync clock for DATAl
DATAlffl|BlǤ7n77^ai*ri 0
7MX5 RIGHT SW 1
Sync clock for DATA2
DATA2ffi|5)M7Q77Sttl*T^. 0
8MX6 STROBE (CS) 0DATA? fo RC-100
^Rc-iocKsx-^'^diTorsio 0
9GND GROUND •••GROUND •••
iuPD65006-017 I/O GATE ARRAY BLOCK DIAGRAM (Fig. 11)
10

JAN. 1988 S-550
CHECKING AND ADJUSTMENT
Power Supply (+5.2)
CAUTION
Make sure that connectors CN1 and CN4 of the power
supply board are firmly connected to CN11 and CN10
of the CPU board, respectively. Note that the Analog
ground path (AG) and Digital ground path (DG) of the
power supply board are electrically indepent of the
other.
1.Turn the S-550 on.
2. Connect avoltmeter across TP +5(-i-5.2) and TPDG
of the power supply board.
3. Adjust VRl of power supply board for -I-5.5V
reading. If VRl fails to adjust, refer to the NOTE
below.
NOTE: With products SN below 841699
If VRl cannot bring the TP+5V to +5.2V, first
check R6 for value.
Replace with 30kf2 if the existing value is 27kl2.
All the products SN 841600 and up have 30kl2
R6.
Chains
rnmmEi+bmcDmm
—KCDCNI tCPU^i^'- K0)CN1 1
'i tT:- KcDCN 4iCPKcDC N
10l/''o
KiltCfcl^T.AG (T+p^"GND )
tDG (';>^y^GND )
1. S—550T-v
2. ~r' 't ^h7—^(Xii XX7)—+1-7°
7-4 KcDTP +5V(+5.2 V)iTPDGfC^
?> O
3. 7-7-(D^g^;6>+ 5.2 Vfc;:? ++0^^°^- +7°
74KcDVR 1
IB#Mo
mffi:6>+5.2 ^n°'7-+7°7 4
KCDR 6CDfil^+ X-V 7L. 27
30KHI^I^HLTT ^1/^0
84 16003OKnts: ^^T
Audio Stage
1. Turn the S-550 off.
2. Connect the S-550 to an oscilloscope. Turn the
scope on.
3. Holding down [T] button, turn the S-550 on .. .
keep [T] button until the CRT displays "Please
Insert System Disk”.
4. Insert the utility disk into the disk slot.
5. When the first access to the disk is complete, press
IuTILITYI ,and then |MENU| .The utility menu is
read from the disk and written into internal
memory.
6. Select "Sampling" from the screen using the cursor
buttons and press |eXCUTE| .
7. Connect INPUT jack to an audio generator and
apply a3Vpp, 1kHz sine signal.
8. Select LINE using LINE/MIC button. Set REC
LEVEL to MAX.
9. Connect the scope to TPDA (DAC OUT) with
ground at TPAG (analog ground).
AUDIOOSg^'i'V^
1. —S.S- 5 5
2. S- 550tCRTc^:^jfiEL^ CRTOWM^An
3. [I]®+'7 7^t¥L^T;6>bmiiix4 -y+^An&o tzf£
[E® +^^CRT{(1 "Please Insert System
Disk ”i(/'' 5^-V +— tl'S Loo'
ttTfc< Cio
4. —-r ij XX7 A'+'L o
5. xA IUTILITY I,IMENU I
x^x7;^iL-^ —x-f 'Jx^(7)7 -ib> o—K$tl
6. +—V 7 7"C’ "Sampling ”+—7;u
mLIEXCUTe] +77^
+77° ‘j 77"^—
7. INPUT 1KHz ,3Vp-p^iP;l&c
8. S-550CDLINE/MICi^Jg^^LINEiiJ. REC
LEVEL -y hirho
9. CPU +-KCDxX hh°7TPDA( D/A =i 7y^'-7
T7 h)-TPAG (T+a7"GND) fS{C +7PX3
11

10a. Shift the cursor to “Limiter" position on the screen
and press button to turn off the limiter.
Verify the waveform, as shown in Fig. 1, on the
scope.
lOb.With the cursor at "Limiter" position, press
INC/YES button to turn on the limiter. Verify
the waveform as shown in Fig. 2.
Also verify that the level meter on the CRT is
reading red.
10. LIMITER on/of
F
^hCD (CRT0®
^pX3ho
limiter OFF^ (Fig. 1)
X^Limiter CD
1
IDEC/NO Iy^W-to \
LIMITER ON^ (Fig. 2)
ii —yJU yViJ —Limiter
(Di^^^K^CD^@fc:'^:bfi- IINC/YES~]
CCDP#C RT0®CD —^:6>U-v K'/— X{cl
A'3Tl''^C<h in £i o
11.(With limiter on) Shift the scope lead to MIX OUT.
Set VOLUME to MAX. The waveform on the scope
should be as shown in Fig. 3.
11 .iliaLIMITER ONCD^^CD^^-^, ^:^nXP-
7°%Mix out(j:^^LELv volumes:^A{c-r
i> o
C(D^, ;t'>P XP-7°CD^f^;6>( Fig. 3)cDJ:5(C
rihct
Test Mode
Entering Test Mode
1.Turn the CRT off.
2. Press and hold [Tj button and turn the S-550 on . . .
keep [Tjbutton on until "Please insert System Disk"
is displayed.
3. Insert the utility disk supplied with the S-550. The
disk version number will be displayed.
(The disk should be of Ver. 1.01 and up. Otherwise,
some functions in the Test mode cannot be per-
formed correctly.)
T"7.h^—
K
1. —B.S-5 5OcDm^^iiU^-o
2. S- 550(D[I]cDd<'7 -y
Atl^o fztzL. [HcDdf^Xfi. CRTIC "Please
Insert System Disk ”i0'' 5-L”
Loo'CtTfcX Cio
3. MBcDp-— •T
-
fUX—A^X7[Ver. LQUy^CD
i^CD ]
&M 3- —A-f 'J A-f —A-f XX:^>Ver. 1.0 0(D^
cD(d;^ AX h-t- Kx°p AA ACD—
;6>^^Ai6iEL<
ysf --7 3Xir ACf^CRTid gA: §ntAo
S-550 JAN. 1988
4. After the initial reading from the disk is complete,
press the following buttons in the order of arrows.
IFUNC IHMENU
4. AA T AAx^
The CRT will display "Hacker mode". (Fig. A)
Press lUTI LITV^ and |MENU| in that order to load
the utility menu data from the disk.
Using the cursor buttons, position the cursor at
"The Test". Press EXCUTE button and the Test
Mode Menu is displayed.
CRT0®;6>Fig. AcD j; 5-y A—
A
5. UTILITY cDjiMic: A7X
A'A XXb3- —A^ij A-f —CD 73- a, —a—K$
CRT0®(<:3- —-r ^ij x^—CDX —:l —7^X
6. XT "The Test ”CD^itC A-
mt IEXCUTE IA7 y^Wto
CRT ®®fc: AxhA— KCD7-33. —7^X K7
(Fig. B)
Test Programs
oWave Check
This is to test array of 1M bit DRAM memory consisting
of ICs, 37—48 for wave data.
In the main menu of the test program perform the
following.
1. Position the cursor to "Wave Check" and press
The program will perform the following tests while
displaying counts in hexadecimal number from 00
to F, in brackes in the test title field.
.Writes test data into DRAMs ICs, 37—48 during
the 1st counting cycle.
.Reads the test data from the DRAMs during the
second counting cycle and compare them with
those written into previously.
.Displays "Complete" when all DRAMs are verified
to be intact.
.Displays, when mismatched bit pair(s) is detected,
error messages as exampled in Fig. C.
oWave Check
7X-7" A- 77AIJ [IC3748(1Mb" -y h
DRAM) ]cD^^S^frA^-To
AMjO) $
t-'/JU .A 7XT"Wave Check ”CD^lf (C A-V^
^
W]L IEXCUTE ITT^'^y^Wto
00;6^bFF^Tl 62H] A7Xh
L^ CRTSMlcg^Lt-To (tcDH,
nLtt)
1[o]g(DA7X h^fCDRAMC IC37-48) ^A-
2[g@0A7x h^[<;DRAM;()^bA-
DRAM:6>IE
DRAM>6>^TiES'C^n(4: Complete i
T^^CDDRAM^^tULfC^-a-^ Fig. C(DJ; 5X7-
7-y A—#7 -y A — i/CDMll^(iJil,T(D
•Error bank ... Indicates the bank on which the
DRAM showing error status exists.
•Error bank xy —(Ddj/'^ DRAMCD^'^'X 7
y<X IC#^B
Table AtCyp:L^'4‘c
(Table A
)
12

JAN. 1988
•Error address Indicates the address assign-
ed to the defective memory
cell in that DRAM.
•Correct pattern ...The value written into the
DRAM.
•Error pattern The value read from the
DRAM.
•Error Address
•Correct pattern
•Error pattern
(Fig. B)
X7—CDUi fc ^X—-7V ^'j —
(D-RAM)(7^T
L
DRA
Ltf
DR
S-550
oOffset Adjustment
This compensates for offsets at the DAC (IC31) and op
amp (IC32b). In practice the offset will generate
transient noise upon turning on or off of analog switches
(ICs 51, 53, 55, 57) functioning as output assigner.
©Offset Adjustment
D/A3 (IC31)(ilC32b)
’CCDUgd-M >b7°-y hT-^'
T-yf- (IC51 ,53,55 ,57):6>
ON- OFF Ltz yThht
Connect MIX OUT to amonitor amp.
Select "Offset Adj" in the menu window with
cursor, then press IEXCUTE] .The program enters
into test mode and generates random pulse noises
for use in the adjustment.
Adjust VR1 (CPU board) for the least noise ampli-
tude.
Press IEXCUTEI.
Press ICOMMANDI to return to the menu window.
1. ODT
2. *-VjUtT: 7Xt?' "Offse tAdj” ti-V
#1)L. IEXCUTE I(^xXh-t
-V^Ai> )
3. tihXb\^CRD BOARD
0VR
1
4. IEXCUTE 1("Complete
)
5. 1COMMAND I7x^-7TxK’>
oMSB Adjustment
This adjusts the weight of MSB at DAC output.
Lack of this adjustment will make unpleasant sound
during the release period (after release of akey).
Connect MIX OUT to the monitor amp.
Position the cursor in front of "MSB Adj” and press
|eXCUTE| .The S-550 enters into MSB Adj mode
and generates acontinuous test signal.
Adjust VR2 for aminimum sound level.
Press IEXCUTEI to display "Complete".
Press ICOMMANDI to return back to the menu
window.
OMSB Adjustment
D/ SB^iiE
'C0»d-M Xh;6JX'XT0^c!;^ 1^0 'J U-X(^'
1. ^x7-TX7°^ MIX OUT \TZ^Wr^ho
2. X-U' "MSB Adj ”0(«SC 77-
IEXCUTE I(;$;-r Xf^
-V'^Ahc )
4. IEXCUTE ]("Complete ”
5. ICOMMAND 1L^ 7x^-7TXK^
13

oD/A Bit
This test examines the bits at the DAC.
1.
Connect the monitor amp and scope in parallel to
MIX OUT.
2.
Position the cursor at "D/A bit" in the menu
window and press IeXCUT^ .
Test Program
Entering this mode displays the list relating panel
switches to bits. Pressing adefined switch will set the
corresponding D/A bit (bit 0to bit 12) which will
generate asquare-like waveform, resulting in an audio
sound from OUTPUT.
The GND on the screen means all "0" bits, and the MAX
all "1"bits. Audio sound also reflects these level nota-
tions.
NOTE: This test ignores MSB 3bits, placing them at 0
level.
3. Press panel buttons defined in the screen one by one
and verify that the 0button generates 0(GND)
output, the 2button generates the voltage as large
as twice that generated from button 1.The button
3generates 4times the button 1,etc. FUNC
should generate the maximum voltage of 3.4Vpp.
4. Press IEXCUTE] .("Complete" displayed)
5. Press COMMAND to return to the menu window.
oRC-IOOCHK
This test checks functions of the remote controller,
RC-100 as well as makes it possible to check mouse,
MU-1 and footswitch, DP-2 that are to be used with the
RC-100.
Testing
1.Position the cursor at "RC-100 CHK" field by using
the cursor buttons and then press lEXCUT^ to
enter into the test mode. (Fig. E)
2. Connect MU-1 and DP-2 (s) to the correct jacks on
the RC-100, respectively (one DP-2 to either of
REC or START/STOP; or two DP-2's to both).
3. Connect the RC-100 to the S-550 and press
RESET on the RC-100 panel.
OD/A bit
D/A3 t"-v h
1. MIX OUT{cM
2. "D/A bit
mu IEXCUTE I
VicAh )
-
:$;•/ Xh^CR
T-j /A^ ^t" -V ht
(Fig. D)
hdXa 3hi">y h(bit 0—12 )(DAi)>\L
UOUTPUT/)^ ^tit -To
GND t(t -r-<TCO b" -v h
b' -y h
(bit 0-12 OCi
'&.M D/A=3 ^it 16b" -y hHttK
C(D^^yU Ay 3b"-y h
(bit 0-12) 'V ^(DAX\
3b"-y hb"-y h
)LTl' t^o
3. 'y L. GNDT?it
bit ^1
Ct^mmirho fH
3. 4Vp -p"t? -Si ^<h o
4. IEXCUTE ]("Complete ”
)
5. ICOMMAND |
7ji' ^y
ORC-100 CHK
ij h=iy hP-7-RC-1 OOcDSbi^A^ -y
(RC-10 0iC^mt&-^^^MU~l RO^'y-y -y
f-DP-2 i-y )
1. yv '' RC-1 00 chk” cDW^t>-v
IEXCUTE |yyh
•^r— K'^A&o Fig. E)
2. mu-i;^ckdp-2^rc-i OOfC^^-r^o
3. RC-1 00 ^S-5 50RC-1 0OCD 0-b
•y b"t'o
S-550 JAN. 1988
4. Press |lNC/YES| button on the S-550 to display the
table as shown in Fig. Fon the screen.
5. Press abutton on the RC-100; amark should appear
in front of the field given the button name just
pressed. Proceed to the remaining buttons and
confirm the mark for each button name field. Also
check the LED, if any, in abutton for lighting,
upon pressing the button.
6. Rotate the alpha dial counterclockwise; "FF"
should appear just below "DIAL" on the screen,
rotate the dial clockwise and "0" should appear.
7. Move the mouse in directions and confirm the mark
appearing in front of each MS direction field (e.g.
"MS UP"). Also check "MS SW" fields for amark
upon pressing the switch on the mouse.
8. Press IeXCUTEI to display "Complete".
9. Press |COMMANP| to return back to the menu
window.
10. Re-enter into RC-100 CHK mode by positioning the
cursor at "RC-100 CHK" field and pressing
11. Depress DP-2(s). Amark should appear in front of
"REC" (or REC and START/STOP) on the screen.
12. Press IeXCUTEI to display "Complete".
13. Press IcOMMANDI to return to the menu window.
(Fig. D)
4. S-550(D IINC/YES |rTUy^j^j-Q (CRTlj
ffiliFig. FCDJ: )
5. RC-1 0-y
Aig fC-e-^;e)>Fig.G(Dj;5 §tl ^^
(LEDj^^ y(Dm'^iU LEDMIT^
mt&
)
6. r"FF ”.«j{^[s]
tt "01 ”<LI/^pfi:6>CRTli®CDDIAL(DTi2:^
7. (MS LEFT
etc ••• )^
^’5' XCDXT -y -y A
8. IEXCUTE] TrUy^Wiro ("Complete ”
)
9. Icommand] ay-fo (
10. yi? "RC-10 0CHK”(Djitc:*-y3P
IEXCUTE IA'^y^WL.
KA^o
11. DP-2 -y y^gCREC
Xli START/STOP )C
12. IEXCUTE IAU'y^^to (" Complete ”
13. ICOMMAND 1'y^Wto (^'y K7
(Fig. E)
&mm mmm:
,?. :.is Si
21sjrt.-l
.. UU. 2A
X
:
k:'- -s. Si-i.fe.- ia:- -
(Fig. F) (Fig. G)
..IV^ •«»?#- '.t=5S' Sf^' ',
•v-b*'.','-? .KivT
4vV
:»-uuT USP 7U V
>8.sc«s ^
;«»s. E'lc^ar Jilt*,
a-
tw ";
->?jnKt'1VS«<<9W
''•
14

JAN. 1988
Software Version Display Mode
Running in this mode causes the CRT to display the
software versions of the system disk and ROM on the S-
S-550.
1.Connect the S-550 to the CRT. Turn the CRT on.
2. Press and hold 1button on the S-550 and turn the
power on ...keep 1button on until "Please Insert
System Disk” is displayed.
3. Insert the system disk or the utility disk into the
disk slot.
is: J; 0^'> Xx A7°n ^"7 —i/
3>(2Ro
-'^3 ^i^-^o
1. S-55 0iCRT^: CRT (DmU^Atli>o
2. S-5 50CD 'y
o
tzfzL^ fficD.-^'^^XiCRTfc" Please Insert
System Disk ”0^-y -fe—
Lo-:5Cj-Tfc< *0
$1/^0
Upon pressing |DEC/NO
|
,both system program version CRTjiiMlC '> 7>x A7°a 7acD /<—
3
yi
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S-550
15

S-550 JAN. 1988
c££3 c£o &
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POWER SW BOARD
Assy 79380221 100/11 7
V
79380224 220V
79380225 240V
(pcb 2292350300)
POWER SUPPLY BOARD
Assy 79380211 100/1 17V
79380214 220/240V
(pcb 2292349500)
HEAT SINK HEAT SINK
7815 7915
OUT ®N0
TP+15V
Ji
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no
zz
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View from component side
f^Roland
CN I
SWI
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94 V- O
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ASSY 7938022X 00
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F3
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GND
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240V
AC IN
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R1
1/2W
470K
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Cl
4700P r^W—13
2
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3
CN1
HOT 1
N.U, 2
COLD 3
5219-03
A
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POWER SWITCH BOARD ASSY
(pcb 2292350300)
100/1 17V
220V
240VE/A
79380221
79380224
79380225
AC VCOLOR
100VBLU
120V GRN
220V BWN
240V RED
View from component side
r
*Fig. 1
POWER TRANS.
*Fig. 1
3191-3R1
RED
BLK
RED
YEW
FI F2 F3
100V
117V
220V
240V
Jumper Jumper
TSC 4A
CEE T5A
"Fig. 2
FUSE 1POWER TRANS.
100VT-GGS 5A 22453489
117V T-GGS 5A 22453490
220V CEE T5A 22453491
240VE/A CEE T5A 22453492
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A.GND 5
A.GND 6
CN4
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-P5.2V 2
-P5.2V 3
D.GND 4
D.GND 5
D.GND 6
D.GND 7
CN2
+5.2V 1
-P15V 2
-H5V 3
-15V 4
-15V 5
A.GND _6_
A.GND 7
A.GND 8
CN3
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D.GND 2
D.GND
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16

JAN. 1988 S-550
11 ia 13 15 1B 17 !0 21 22 try 2S 27 21 31 32 33 34 3! ,3'q
View from foil side
o
:side
W/LED BOARD
Assy 79380200
(pcb 22923492)
Assy 79380230
(pcb 22923492)
i
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HII
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JK3
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JK1
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10/25
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C6
10/25
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'100K
CN3
REC.SIG 1
A.GND 2
MIC 3
A.GND 4
LINE
A.GND \l
a
FLI,2,3,4,5,
8
ZJSC-220-101
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CTRL
_0-R8q_
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60-
20-
70-
30-
80-
40-
90-
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B-
FL4
-B-
CN1
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DELC-J9PAF-1L8
FL5
B- FL8
B-
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FL6
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(FUSE RESISTER)
CN4 Iwv
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'o10KB
1REC.SIG
2A.GND
3MIC
4iA.GND
5LINE
6A.GND
i4^ENTER LEDBUSn/l
DISK LED BUS9/1
i/t^COMMAND LEDBUS8/i
^EXECUTE LED BUSQ/1
UTILITY LED BUSI/1
EDIT _L£D_BUSg/^
#/t^SUBMENU LEDBUS3/4
MENU LED Busyr
iA^FUNC LED BUS5/1
PLAY LED BUSM
#^MIDI LED BUS7/
MX5 1—9
MX4 2—8
MXO 3—7
MX1 4—6CPU
MX2 5—5BOARD
MX3 6—4CN4
+5.2V 7—3
D.GND 8—2
MX6 g—1
JACK BOARD ASSY 79380230 J
UTILITY
SW12
<
SW13
V
SW14
0[>
SW15
EXECUTE
iSW2
T>LAY
iSW3 0
'EDIT
iSW4
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vSW5
MENU
SW6
A
SW7
SUBMENU
SW8
COMMAND
SW27
0
iSW24
'1
iSW25
'2
iSW26
3
SW21 0
4
SW22
05
SW23
6
SW28
ENTER
SW18
iSW19
'8
iSW20
9
SW16
DEC
SW17
INC
K-
K
+5.2V 13
LED BUSH 12
LED BUS10 11
LED BUS9 10
LED BUSS 9
LED BUS7 8
LED BUS6 7
LED BUS5 6
LED BUS4 5
LED BUSS 4
LED BUS2 3
LED BUS1 2
LED BUSO 1
—13
—12
—11
—10
—8CPU
—7BOARD
—6CN9
—5
4
3
2
1
CN8
SW BUSO 12
SW BUS1 11
SW BUS2 10
SW BUSS 9
SW BUS4 8
SW BUS5 7
SW BUS6 6
SW BUS7 5
SCANO 4
SCAN1 3
SCAN2 2
SCANS 1
SWITCH BOARD ASSY 79380200
—12
—11
—10
—9
—8
7
6
5
CPU
BOARD
CN5
—4
—3
—2
—1
17
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JAN. 1988 S-550
Assy 79380120 (pcb 2292349302) View from component side
TO FLOPPY DISK DRIVE
S-550 CPU BOARD
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Assy 79380120 (pcb 2292349302) View from component side
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