JAN. 1988 S-550
3. Output Assignee Gate Array BU3905 (IC49) 3.7^^ N7°'y hTK(IC49)BU3905
The TVF interface sends 16 voice data (each of 16
bit) in time-division fashion. After D/A converted,
each of two consecutive voice pairs is gated into an
individual output circuit in the same time slot. The
output assigner determines the output channel
according to assign information given by the CPU.
TV FT X/r"- hTL-T (IC29)b
(16f'-v 16-T'T
ti. D/A3 (IC3 1)
D/A 3yy'f—
2
>-T'T 1LTT h^fij
'O^X
<J;CDrh'T X^°T^ 18CD<J;(7)Tt> h
itr /h7°-v hT-fl-T x/r"- hTUT (IC4 9)/)\
CPU (IC9
Disk Read/Write
(Fig. 7)
On aread or write command from the CPU, the FDC
pulls MOTOR ON low to let the FDD (Floppy Disk
Drive) starts the motor. When the motor running has
reached stable condition, the FDD signals the CPU
through I/O gate with alow READY. The low READY
allows the CPU to issue acommand which enables read-
ing or writing to/from the disk.
In the read mode the FDC reads data from FDD in serial
format and sends it to the CPU in parallel 8bits.
In the write mode the FDC first pulls and keeps WG high
and then places adata on WD line.
FDCfSCPU/}^^ 'j- KXfixT !>
FDD(7n-7 t° —T-'X X7KXT7" )1/ T
MOTOR
Xo
FDD{S^-7-CD0fe/;JXS-ri)c!:> CPU(C READY
I/O/r'— hT/T^^bXMO ^~to
CPU READY11-^ ^
i
<J -KPt. FDC RDi^-T-J: hFDD/}i (7)/ Ij
bCPUfC^b^-To
xT h0#F DC^WGft^^High
WD^X^ilUTx-"-7 ^FDD{C*^3A7^^-ro
FDC Pin Description (Table 2)
PIN
NUMBER MNEMONIC SIGNAL NAME I/O DESCRIPTION
1CHIP SELECT 1Alogic low on this input selects the chip and enables Host communication
with the device.
Low LevelT'CPUtCOLlSi” Y—'>3>*'"5jHElL4'0St"o
2R/W READ/WRITE 1Alogic high on this input controls the placement of data on the D0-D7
lines from aselected register. While a logic low causes awrite operation to
aselected register.
High LeveLv-f h-X TYYC7)L#U Low Level IZLttr,
3, 4AO, A1 ADDRESS 0, 11These two inputs select aregister to Read/Write data:
>:Ji:lLfF-rJ:9lL.Y(7)20(7)AY(CJ:oT'J-K,*Al47Th-X'1'7tKL*t-f?>FDCrtg|5
CS A1 AO R/W=1R/W=0
000Status Reg Command Reg
001Track Reg Track Reg
010Sector Reg Sector Reg
01 1 Data Reg Data Reg
5-12 DAL0-DAL7 data access lines
0THROUGH 7
I/O Eight-bit bi-directional bus used for transfer of data, control, or status. This
bus is enabled by CS and R/W. Each line will drive one TTL load.
8bitO-Y'-tSr-A'XT.Y'-tXD'POirClLfeffl^nS-ro
13 KM MASTER RESET Alogic low pulse on this line resets the device and initializes the Status
Register (internal pull-up).
Low Leveir\FDC^0-lz-vbLStc
14 GND GROUND Ground. lt;®77>Klc}g|iU*'To
15 Vcc POWER SUPPLY 1-t-5V ±5% power supply input. -F5V^)ig(LfgML$'To
16 STEPP STEP 0The Step output contains apulse for each step of the drive's R/W head.
17 DIRC direction 0The Direction output is high when stepping in towards the center of the
diskette, and low when stepping out.
xVY7 •KxTX(D^-y KSHigh LevelTx-fY2CD Low LevelT'x-rXYCO^'f
fflU ^XXVXS-tf -5 A»CO [S] sISg; L*To
18 CLK CLOCK 1This input requires afree-running 507o duty cycle clock (for internal timing)
at 8MHz ±0,17o.
8MHz ±0.1% 50%xx-x-f±'rC7tKO'7P y2®AYlLT-ro
19 READ DATA 1This active low input is the raw data line containing both clock and data
pulses from the drive.
x-rXY -HxTXA’Dx— SttSTo
20 MO MOTOR ON 0This active high output turns on the motor,
x-f X7 KxTXco±-7SSi]WL^-r,.
21 WG WRITE GATE 0This output is made valid prior to writing on the disk.
x-fX2 -x— JAti'tSlL High Level ICYOSTo
22 WD WRITE DATA FM or MFM clock and data pulses are placed on this line to be written on
the diskette.
X—7$:x'fX'7 •F'xYXYjMDSt'
23 TROO TRACK 00 1This active low input informs the WD1 770-00 that the drive's R/W heads
are positioned over Track zero (internal pull-up).
Fx yTsi iffS-^-SSltST ,Low Level (DLSx-rXY- Kx'fXcO^ yKYx-fX'T CO®
6^ffiULf4BLSY„
24 IP INDEX PULSE 1This active low input informs the WD1 770-00 when the physical index hole
has been encountered on the diskette (internal pull-up).
'r>X'y7Xft-§-S®H*t'„TC0fi-§^(Tx-rX2Y"l(e]te-T5C'tlCxVX7-Kx-TX>b
25 WPRT WRITE PROTECT 1This input is sampled whenever aWrite Command is received. Alogic low on
this line will prevent any Write Command from executing (internal pull-up)
X'rF-XP±2hfl-§-$®ltSr .CCOfS^li.x-rXYlCxTb-XPAYhY'A'YxTL'-S
tgiLxVxx-Kx'rXYDisE.nrs^-r.,
26 DDEN DOUBLE DENSITY
ENABLE 1This input pin selects either single (FM) or double (MFM) density.
When DDEN =0, double density is selected (internal pull-up).
High Level T#®®(FM)(L. Low Level Tf^S'®(MFM)lL|S:®^n*1-o
27 DRQ DATA REQUEST 0This active high output indicates that the Data Register is full (on aRead)
or empty (on aWrite) operation.
C<OtfJ*(OSL-t±Y'HTx-X-L'vXXY'J-K<75t#li7tU.x-Tb(Ot#l4x>'7±<
28 INTRO INTERRUPT REQUEST 0This active high output is set at the completion of any command or reset
at aread of the Status Register.
CCD tii ±®ArT.±YHT\PX>KcD CPUlLjPb-t+*-r„
9
