Scenix SX Series User manual

SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Scenix™
SX Family
User’s Manual

© 2000 Scenix Semiconductor, Inc. All rights reserved. SX User’s Manual Rev. 3.1
www.scenix.com
Revision History
©2000 Scenix Semiconductor, Inc. All rights reserved. No warranty is provided and no liability is
assumed by Scenix Semiconductor with respect to the accuracy of this documentation or the
merchantability or fitness of the product for a particular application. No license of any kind is conveyed
by Scenix Semiconductor with respect to its intellectual property or that of others. All information in
this document is subject to change without notice.
Scenix Semiconductor products are not authorized for use in life support systems or under conditions
where failure of the product would endanger the life or safety of the user, except when prior written
approval is obtained from Scenix Semiconductor.
Scenix™ and the Scenix logo are trademarks of Scenix Semiconductor, Inc.
Virtual Peripheral™ is a trademark of Scenix Semiconductor, Inc.
I2C™ is a trademark of Philips Corporation
Microwire™ is a trademark of National Semiconductor Corporation
All other trademarks mentioned in this document are property of their respective companies.
Scenix Inc., 1330 Charleston Road, Mountain View, CA 94043, USA
Telephone: [phone], Fax: [phone], Web site: www.scenix.com,
E-mail: [e-mail]
REVISION RELEASE DATE SUMMARY OF CHANGES
2.0 February 11, 1999 Updated to include SX48/52BD devices
2.01 June 14, 1999 Conyents the same as Rev 2.0 but removed the
last chapter (Device Programming)
2.1 May 19, 1999 Updated to reflect the new revision of the
SX18/20/28 AC devices (datecode Axyywwxx)
2.2 June 4, 1999 Deleted the recommended component values
associated with resonator/crystal oscillator.
This information is available in the datasheets.
3.0 January 21, 2000 Updated to reflect the latest revision of the
SX48/52BD (Production Part)
3.1 August 24, 2000 Updated to correct errata sheet items.

SX User’s Manual Rev. 3.1 4© 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com

© 2000 Scenix Semiconductor, Inc. All rights reserved. 3SX User’s Manual Rev. 3.1
www.scenix.com Contents
Contents
Chapter 1 Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 The Virtual Peripheral Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 The Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Programming and Debugging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.8 Part Numbers and Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2 Architecture
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 SX18/20/28AC and SX18/20/28AC75 Addressing Modes and
FSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 SX48/52BD Addressing Modes and FSR Register . . . . . . . . . . . . . . . . . 17
2.3.4 Register Access Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 W (Working Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.2 INDF (Indirect through FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 RTCC (Real-Time Clock/Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.4 PC (Program Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.5 STATUS (Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.6 FSR (File Select Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.7 RA through RE (Port Data Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.8 Port Control Registers and MODE Register . . . . . . . . . . . . . . . . . . . . . . 26
2.4.9 OPTION (Device Option Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 Instruction Execution Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.2 Pipeline Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.3 Read-Modify-Write Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.1 Test and Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.2 Jump Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.3 Jump Indirect and Jump Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.4 Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.5 Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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2.7 Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.8 Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 3 Instruction Set
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.1 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.2 Arithmetic and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.3 Bitwise Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.4 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.5 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.6 System Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.5 Equivalent Assembler Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6 Detailed Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6.1 ADD fr,W Add W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.6.2 ADD W,fr Add fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.6.3 AND fr,W AND of fr and W into fr . . . . . . . . . . . . . . . . . . . 69
3.6.4 AND W,fr AND of W and fr into W . . . . . . . . . . . . . . . . . . . 70
3.6.5 AND W,#lit AND of W and Literal into W . . . . . . . . . . . . . . . 71
3.6.6 BANK addr8 Load Bank Number into FSR(6:4) . . . . . . . . . . . . 72
3.6.7 CALL addr8 Call Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.6.8 CLR fr Clear fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.6.9 CLR W Clear W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.6.10 CLR !WDT Clear Watchdog Timer . . . . . . . . . . . . . . . . . . . . . 78
3.6.11 CLRB fr.bit Clear Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.12 DEC fr Decrement fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.13 DECSZ fr Decrement fr and Skip if Zero . . . . . . . . . . . . . . . 81
3.6.14 INC fr Increment fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.15 INCSZ fr Increment fr and Skip if Zero . . . . . . . . . . . . . . . 83
3.6.16 IREAD Read Word from Instruction Memory . . . . . . . . . 84
3.6.17 JMP addr9 Jump to Address . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.6.18 MOV fr,W Move W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.6.19 MOV M,#lit Move Literal to MODE Register . . . . . . . . . . . . . 88
3.6.20 MOV M,W Move W to MODE Register . . . . . . . . . . . . . . . . 89
3.6.21 MOV !OPTION,W Move W to OPTION Register . . . . . . . . . . . . . . . 90
3.6.22 MOV !rx,W Move Data Between W and Control Register . . . 91
3.6.23 MOV W,fr Move fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.6.24 MOV W,/fr Move Complement of fr to W . . . . . . . . . . . . . . . 94
3.6.25 MOV W,fr-W Move (fr-W) to W . . . . . . . . . . . . . . . . . . . . . . . . 95
3.6.26 MOV W,--fr Move (fr-1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.6.27 MOV W,++fr Move (fr+1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.6.28 MOV W,<<fr Rotate fr Left through Carry and Move to W . . . 98
3.6.29 MOV W,>>fr Rotate fr Right through Carry and Move to W . . 99
3.6.30 MOV W,<>fr Swap High/Low Nibbles of fr and Move to W . 100
3.6.31 MOV W,#lit Move Literal to W . . . . . . . . . . . . . . . . . . . . . . . 101

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3.6.32 MOV W,M Move MODE Register to W . . . . . . . . . . . . . . . 102
3.6.33 MOVSZ W, --fr Move (fr-1) to W and Skip if Zero . . . . . . . . . . 103
3.6.34 MOVSZ W, ++fr Move (fr+1) to W and Skip if Zero . . . . . . . . . . 104
3.6.35 NOP No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.6.36 NOT fr Complement of fr into fr . . . . . . . . . . . . . . . . . . 106
3.6.37 OR fr,W OR of fr and W into fr . . . . . . . . . . . . . . . . . . . . 107
3.6.38 OR W,fr OR of W and fr into W . . . . . . . . . . . . . . . . . . . 108
3.6.39 OR W,#lit OR of W and Literal into W . . . . . . . . . . . . . . . 109
3.6.40 PAGE addr12 Load Page Number into STATUS(7:5) . . . . . . . 110
3.6.41 RET Return from Subroutine . . . . . . . . . . . . . . . . . . . 111
3.6.42 RETI Return from Interrupt . . . . . . . . . . . . . . . . . . . . . 112
3.6.43 RETIW Return from Interrupt and Adjust RTCC with
W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.6.44 RETP Return from Subroutine Across Page Boundary 114
3.6.45 RETW lit Return from Subroutine with Literal in W . . . . . 115
3.6.46 RL fr Rotate fr Left through Carry . . . . . . . . . . . . . . . 116
3.6.47 RR fr Rotate fr Right through Carry . . . . . . . . . . . . . . 117
3.6.48 SB fr.bit Test Bit in fr and Skip if Set . . . . . . . . . . . . . . . 118
3.6.49 SETB fr.bit Set Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.6.50 SLEEP Power Down Mode . . . . . . . . . . . . . . . . . . . . . . 120
3.6.51 SNB fr.bit Test Bit in fr and Skip if Clear . . . . . . . . . . . . . . 121
3.6.52 SUB fr,W Subtract W from fr . . . . . . . . . . . . . . . . . . . . . . . 122
3.6.53 SWAP fr Swap High/Low Nibbles of fr . . . . . . . . . . . . . . 124
3.6.54 TEST fr Test fr for Zero . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.6.55 XOR fr,W XOR of fr and W into fr . . . . . . . . . . . . . . . . . . . 126
3.6.56 XOR W,fr XOR of W and fr into W . . . . . . . . . . . . . . . . . . 127
3.6.57 XOR W,#lit XOR of W and Literal into W . . . . . . . . . . . . . . 128
Chapter 4 Clocking, Power Down, and Reset
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.2 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.2.1 Clock/Instruction Rate Option (Compatible or Turbo Mode) . . . . . . . . 129
4.2.2 Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.2.3 External RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.2.4 External Crystal/Resonator (XT, LP, or HS Mode) . . . . . . . . . . . . . . . . 131
4.2.5 External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.3 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.3.1 Entering the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.3.2 Waking Up from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 134
4.4 Multi-Input Wakeup/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.4.1 Port B Configuration for Multi-Input Wakeup/Interrupt . . . . . . . . . . . . 134
4.4.2 Reading and Writing the Wakeup Pending Bits . . . . . . . . . . . . . . . . . . 137
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.5.1 Register States Upon Different Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.5.2 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.5.3 Wakeup from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5.4 Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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4.5.5 Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.5.6 MCLR Input Signal (Master Clear Reset) . . . . . . . . . . . . . . . . . . . . . . . 142
Chapter 5 Input/Output Ports
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2 Reading and Writing the Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.3 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.1 Accessing the Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.2 MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.3 Port Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.3.4 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.3.5 Port Configuration Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.3.6 Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Chapter 6 Timers and Interrupts
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2 Real-Time Clock/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.2.1 Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.2.2 Maximum Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.2.3 RTCC Operation as a Real-Time Clock or Timer . . . . . . . . . . . . . . . . . 153
6.2.4 RTCC Operation as an Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.2.5 RTCC Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.1 Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.2 Watchdog Operation in the Power Down Mode . . . . . . . . . . . . . . . . . . 155
6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.4.1 Single-Level Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.4.2 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.4.3 RTCC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.4.4 Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.4.5 Device-Specific Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.4.6 Return-from-Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.4.7 Interrupt Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Chapter 7 Analog Comparator
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.2 Comparator Enable/Status Register (CMP_B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.2.1 Accessing the CMP_B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.3 Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

© 2000 Scenix Semiconductor, Inc. All rights reserved. 7SX User’s Manual Rev. 3.1
www.scenix.com Contents
Chapter 8 Multi-Function Timers
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.2.1 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.2.2 Software Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.2.3 External Event Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.2.4 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.3 Timer Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.4 Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.4.1 Timer T1 Control A Register (T1CNTA) . . . . . . . . . . . . . . . . . . . . . . . 169
8.4.2 Timer T1 Control B Register (T1CNTB) . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.3 Timer T2 Control A Register (T2CNTA) . . . . . . . . . . . . . . . . . . . . . . . 171
8.4.4 Timer T2 Control B Register (T2CNTB) . . . . . . . . . . . . . . . . . . . . . . . 172

SX User’s Manual Rev. 3.1 8© 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comContents
List of Figures
Figure 1-1 SX18/20/28 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 1-2 SX48/52BD Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 1-3 Part Numbering Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2-1 SX28AC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2-2 Register Access Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2-3 Program Counter Loading for Jump Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 2-4 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 2-5 Stack Operation for a “Call” Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-6 Stack Operation for a “Return” Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-7 Device Configuration Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3-1 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 3-2 Rotate fr Left Through Carry into W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 3-3 Rotate fr Right Through Carry into W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 3-4 Rotate fr Left Through Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-5 Rotate fr Right Through Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 4-1 External RC Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 4-2 Crystal or Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 4-3 External Clock Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 4-5 On-Chip Reset Circuit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 4-6 Power-On Reset Timing, Fast VDD Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 4-7 Power-On Reset Timing, VDD Rise Time Too Slow . . . . . . . . . . . . . . . . . . . . 141
Figure 4-8 External Power-On MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 4-9 Power-On Reset Timing, Separate MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 5-1 Port B Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 6-1 RTCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 6-2 Interrupt Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 7-1 Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 8-1 Multi-Function Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

© 2000 Scenix Semiconductor, Inc. All rights reserved. 9SX User’s Manual Rev. 3.1
www.scenix.com Contents
List of Tables
Table 1-1 Device Package Names ...............................................................................................17
Table 1-2 Pin Descriptions ..........................................................................................................20
Table 2-1 SX18/20/28AC and SX18/20/28AC75 RAM Register Map ......................................24
Table 2-2 Register Summary .......................................................................................................30
Table 2-3 STATUS Register Bits ................................................................................................32
Table 2-4 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75 ........................35
Table 2-5 MODE Register Settings for SX48/52BD ..................................................................36
Table 2-6 Prescaler Divide-By Factors .......................................................................................38
Table 2-7 Pipeline Execution Sequence ......................................................................................39
Table 2-8 Return-from-Subroutine/Interrupt Instructions ...........................................................45
Table 2-9 FUSE Word Register Configuration Bits for SX18/20/28AC ....................................49
Table 2-10 FUSEX Word Register Configuration Bits for SX18/20/28AC &
SX18/20/28AC75 ........................................................................................................51
Table 2-11 FUSE Word Configuration Bits for SX48/52BD .......................................................52
Table 2-12 FUSEX Word Register Configuration Bits for SX48/52BD ......................................54
Table 3-1 Logic Instructions .......................................................................................................60
Table 3-2 Arithmetic and Shift Instructions ................................................................................60
Table 3-3 Bitwise Operation Instructions ...................................................................................61
Table 3-4 Data Movement Instructions .......................................................................................61
Table 3-5 Program Control Instructions ......................................................................................63
Table 3-6 System Control Instructions ........................................................................................63
Table 3-7 Equivalent Assembler Mnemonics .............................................................................64
Table 3-8 Key to Abbreviations and Symbols ............................................................................66
Table 4-1 Register States Upon Different Resets ......................................................................139
Table 5-1 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75 ......................146
Table 5-2 MODE Register Settings for SX48/52BD ................................................................146
Table 6-1 Watchdog Timeout Settings ......................................................................................155
Table 8-1 Timer T1/T2 Pin Assignments ..................................................................................168
Table 8-2 T1CNTA Register Bits .............................................................................................169
Table 8-3 T1CNTB Register Bits ..............................................................................................170
Table 8-4 T2CNTA Register Bits .............................................................................................171
Table 8-5 T2CNTB Register Bits ..............................................................................................172

SX User’s Manual Rev. 3.1 10 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comContents

SX User’s Manual Rev. 3.1 11 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Chapter 1
Overview
1.1 Introduction
The Scenix SX family of configurable communications controllers are fabricated in an advanced
CMOS process technology. The advanced process, combined with a RISC-based architecture, allows
high-speed computation, flexible I/O control, and efficient data manipulation. Throughput is enhanced
by operating the device at frequencies up to 100 MHz and by optimizing the instruction set to include
mostly single-cycle instructions. In addition, the SX architecture is deterministic and totally
reprogramable. The unique combination of these characteristics enables the device to implement real-
time functions as software modules (Virtual PeripheralTM) to replace traditional hardware functions.
On-chip core functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a
brown-out detector, a watchdog timer, a power-save mode with multi-source wakeup capability, an
internal R/C oscillator, user-selectable clock modes, and high-current outputs. Additional features are
provided by individual members of the SX family according to the system requirements, such as PWM
timers and additional I/O ports.
1.2 Key Features
50/75/100 MIPS Performance
• DC - 100 MHz operation
• 10 ns instruction cycle, 30 ns internal interrupt response at 100 MHz
• 1 instruction per clock (branches 3)
EE/FLASH Program Memory and SRAM Data Memory
• Access time of < 10 ns provides single cycle access
• EE/Flash rated for > 10,000 rewrite cycles
• SX18/20/28AC and SX18/20/28AC75:
– 2048 words of EE/Flash program memory
– 136 bytes of SRAM data memory
• SX48/52BD:
– 4096 words of EE/Flash program memory
– 262 bytes of SRAM data memory

SX User’s Manual Rev. 3.1 12 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
CPU Features
• Compact instruction set
• All instructions are single cycle except branch
• Eight-level push/pop hardware stack for subroutine linkage
• Fast table lookup capability through run-time readable code (IREAD instruction)
• Predictable program execution flow for hard real-time applications
Fast and Deterministic Interrupt
• Jitter-free 3-cycle internal interrupt response
• Hardware context save/restore of key resources such as PC, W, STATUS, and FSR within the 3-
cycle interrupt response time
• External wakeup/interrupt capability on Port B (8 pins)
Flexible I/O
• All pins individually programmable as I/O
• Inputs are TTL or CMOS level selectable
• All pins have selectable internal pull-ups
• Selectable Schmitt Trigger inputs on Ports B, C, D, and E
• All outputs capable of sourcing/sinking 30 mA
• Port A outputs have symmetrical drive
• Analog comparator support on Port B (RB0 OUT, RB1 IN-, RB2 IN+)
• I/O operation synchronous to the oscillator clock (user selectable)
Hardware Peripheral Features
• Two 16-bit timers with 8-bit prescalers supporting (SX48/52BD devices only):
– Software Timer mode
– PWM mode
– Simultaneous PWM/Capture mode
– External Event mode
• One 8-bit Real Time Clock/Counter (RTCC) with programable 8-bit prescaler
• Watchdog Timer (shares the RTCC prescaler)
• Analog comparator
• Brown-out detector
• Multi-Input Wakeup logic on 8 pins
• Internal RC oscillator with configurable rate from 31.25 KHz to 4 MHz
• Power-On-Reset
Packages
• SX18/2028AC and SX18/20/28AC75: 18pin SO/DIP, 20-pin SSOP, 28-pin SO/DIP
• SX48/52BD family: 48-pin Tiny PQFP, and 52-pin PQFP
• SX52BD75: 52-pin PQFP
• SX52BD100: 52-pin PQFP

© 2000 Scenix Semiconductor, Inc. All rights reserved. 13 SX User’s Manual Rev. 3.1
www.scenix.com Chapter 1 Overview
Programming and Debugging Support
• On- chip in-system programming support through serial or parallel interface
• In-system serial programming via oscillator pins
• On-chip in-system debugging support logic
• Real-time emulation, full program debug, and integrated development environment offered by third
party tool vendors
Software Support
• Library of off-the-shelf Virtual Peripheral modules
• Examples of Virtual Peripheral integration
• Evaluation Kits for communication intensive applications
1.3 Architecture
The SX devices use a modified Harvard architecture. This architecture uses two separate memories
with separate address buses, one for the program and one for data, while allowing transfer of data
from program memory to SRAM. This ability allows accessing data tables from program memory.
The advantage of this architecture is that instruction fetch and memory transfers can be overlapped
with a multi-stage pipeline, which means the next instruction can be fetched from program memory
while the current instruction is being executed using data from the data memory.
Scenix has developed a revolutionary RISC-based architecture and memory design techniques that is
20 times faster than conventional MCUs, deterministic, jitter free, and totally reprogramable.
The SX family implements a four-stage pipeline (fetch, decode, execute, and write back), which
results in execution of one instruction per clock cycle. At the operating frequency of 100 MHz,
instructions are executed at the rate of one per 10-ns clock cycle.
1.4 The Virtual Peripheral Concept
Virtual Peripheral concept enables the “software system on a chip” approach. Virtual Peripheral, a
software module that replaces a traditional hardware peripheral, takes advantage of the Scenix archi-
tecture’s high performance and deterministic nature to produce same results as the hardware periph-
eral with much greater flexibility.
The speed and flexibility of the Scenix architecture complemented with the availability of the Virtual
Peripheral library, simultaneously address a wide range of engineering and product development con-
cerns. They decrease the product development cycle dramatically, shortening time to production to as
little as a few days.
Scenix’s time-saving Virtual Peripheral library gives the system designers a choice of ready-made
solutions, or a head start on developing their own peripherals. So, with Virtual Peripheral modules
handling established functions, design engineers can concentrate on adding value to other areas of the
application.
The concept of Virtual Peripheral combined with in-system re-programmability provides a powerful
development platform ideal for the communications industry because of the numerous and rapidly
evolving standards and protocols.

SX User’s Manual Rev. 3.1 14 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
Overall, the concept of Virtual Peripheral provides benefits such as using a more simple device,
reduced component count, fast time to production, increased flexibility in design, customization to
your application, and ultimately overall system cost reduction.
Some examples of Virtual Peripheral modules are:
• Communication interfaces such as I2C™, Microwire/Plus™ , SPI, IrDA stack, UART, and Modem
functions
• Internet Connectivity protocols such as UDP, TCP/IP stack, HTTP, SMTP, POP3
• Frequency generation and measurement
• PPM/PWM generation
• Delta/Sigma ADC
• DTMF generation/detection
• PSK/FSK generation/detection
• FFT/DFT based algorithms
1.5 The Communications Controller
The combination of the Scenix hardware architecture and the Virtual Peripheral concept create a
powerful, creative platform for the communications design communities: SX communications con-
troller. Its high processing power, re-cofigurability, cost-effectiveness, and overall design freedom
give the designer the power to build products for the future with the confidence of knowing that they
can keep up with innovation in standards and other areas.
1.6 Programming and Debugging Support
The SX devices are currently supported by third party tool vendors. On-board in-system debug capa-
bilities have been added, allowing tools to provide an integrated development environment including
editor, macro assembler, debugger, and programmer. Un-obtrusive in-system programming is pro-
vided through the OSC pins. For emulation purposes, there is no need for a bond-out chip, so the user
does not have to worry about the potential variations in electrical characteristics of a bond-out chip
and the actual chip used in the target application. The user can test and revise the fully debugged code
in the actual SX, in the actual application, and get to production much faster.
1.7 Applications
Emerging applications and advances in existing ones require higher performance while maintaining
low cost and fast time-to-production.
The SX device provides solutions for many familiar applications such as process controllers, elec-
tronic appliances/tools, security/monitoring systems, consumer automotive, sound generation, motor
control, and personal communication devices. In addition, the device is suitable for applications that
require DSP-like capabilities, such as closed-loop servo control (digital filters), digital answering
machines, voice notation, interactive toys, and magnetic-stripe readers.

© 2000 Scenix Semiconductor, Inc. All rights reserved. 15 SX User’s Manual Rev. 3.1
www.scenix.com Chapter 1 Overview
Furthermore, the growing Virtual Peripheral library features new components, such as the Internet
Protocol stack, and communication interfaces, that allow design engineers to embed Internet connec-
tivity into all of their products at extremely low cost and very little effort.
Scenix’s complete network connectivity protocol stack implementation (SX-Stack), enables single-
chip Web servers and E-mail appliances in embedded applications. The implementation includes the
physical layer interface with the TCP/IP network connectivity protocols, enabling system designers to
produce cost-effective embedded Internet devices without external physical access or a gateway PC.
The hardware platform for SX-Stack is the SX52BD communications controller. The device allows
implementation of the entire TCP/IP protocols, physical interface, and other relevant high-speed
communication interfaces as Virtual Peripheral modules.
1.8 Part Numbers and Pinout Diagrams
This user’s guide describes the following Scenix SX devices:
• SX18AC/SX20AC/ SX28AC and SX18AC75/SX20AC75/SX28AC75 devices (with 2K pro-
gram memories)
• SX48BD/SX52BD devices (with 4K program memories and multi-function timers)
The SX18AC/20AC/28AC and SX18AC75/SX20AC75/SX28AC75 devices are available in the pin
configurations shown in Figure 1-1. These devices are functionally the same except that the 18-pin and
20-pin devices do not have the port pins RC0 through RC7. Therefore, Port C cannot be used in the
smaller packages.
Figure 1-1 SX18/20/28 Pin Assignments
SSOP
1
2
3
4
5
6
7
8
16
15
RC4
RC3
RB6
RB5
SX 28-PIN
OSC2
RC7
RC6
RC5
Vdd
Vdd
RA2
RA3
RB0
RB1
RB2
RB3
RB4
Vss
MCLR
OSC1
RC2
RC1
RC0
RB7
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
Vss
RTCC
RA0
RA1
1
2
3
4
5
6
7
8
16
15
RC4
RC3
RB6
RB5
SX 28-PIN
OSC2
RC7
RC6
RC5
n.c.
Vss
RA2
RA3
RB0
RB1
RB2
RB3
RB4
MCLR
OSC1
RC2
RC1
RC0
RB7
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
RTCC
Vdd
RA0
RA1
n.c.
DIP/SOIC
1
2
3
4
5
6
7
8
16
15
RB5
RB4
SX 20-PIN
OSC2
RTCC RA0
RB0
RB1
RB2
RB3
MCLR OSC1
Vdd
Vdd
RB7
RB6
9
10
14
13
12
11
20
19
18
17
RA2
RA3
Vss
RA1
Vss
SSOP
13
1
2
3
4
5
6
7
8
16
RB5
RB4
SX 18-PIN
OSC2
RTCC RA0
RB0
RB1
RB2
RB3
MCLR OSC1
Vdd
RB7
RB6
910
14
12
11
18
17
RA2
RA3 RA1
Vss
DIP/SOIC
15

SX User’s Manual Rev. 3.1 16 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
The SX48/52BD devices are available in the pin configurations shown in Figure 1-2. These devices
are functionally the same except that the 48-pin device does not have the port pins RA4 through RA7.
Therefore, the upper four pins of Port A are not available in the smaller package.
Figure 1-2 SX48/52BD Pin Assignments
Top View
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37 _
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _
RD6
RD5
RD4
Vss
Vdd
RD3
RD2
RD1
RD0
RC7
RC6
RC5
OSC1
OSC2
Vdd
Vss
RA0
RA1
RA2
RA3
RB0
RB1
RB3 RB4 RB5 RB6 RB7
Vdd
Vss
RC0 RC1 RC2 RC3 RC4
RTCC Vss Vdd
RE6 RE5 RE4 RE3 RE2 RE1 RE0 RD7
48 - PIN
TQFP
MCLR
RB2
13 14 15 16 17 18 19 20 21 22 23 24
RE7
Top View
14 15 16 17 18 19 20 21 22 23 24 25 26
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40 _
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _
RD7
RD6
RD5
RD4
Vss
Vdd
RD3
RD2
RD1
RD0
RC7
RC6
RC5
RA6
RA7
MCLR
OSC1
OSC2
Vdd
Vss
RA0
RA1
RA2
RA3
RB0
RB1
RB2 RB3 RB4 RB5 RB6 RB7
Vdd
Vss
RC0 RC1 RC2 RC3 RC4
RA5 RA4 RTCC Vss Vdd RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
52 - PIN
PQFP

© 2000 Scenix Semiconductor, Inc. All rights reserved. 17 SX User’s Manual Rev. 3.1
www.scenix.com Chapter 1 Overview
Table 1-1 is a list of the available SX device packages and the corresponding number of pins, number
of I/O pins, program (flash) memory size, and general-purpose RAM size. Use this table as a guide for
ordering the parts that fit your requirements.
Table 1-1 Device Package Names
Device Pins I/O Operating
Frequency (MHz) EE/Flash (Words) RAM (Bytes) Operating Temp. (°C)
SX18AC/SO
SX18AC-I/SO
SX18AC75/SO
18
18
18
12
12
12
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX18AC/DP
SX18AC-I/DP
SX18AC75/DP
18
18
18
12
12
12
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX20AC/SS
SX20AC-I/SS
SX20AC75/SS
20
20
20
12
12
12
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX28AC/SO
SX28AC-I/SO
SX28AC75/SO
28
28
28
20
20
20
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX28AC/DP
SX28AC-I/DP
SX28AC75/DP
28
28
28
20
20
20
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX28AC/SS
SX28AC-I/SS
SX28AC75/SS
28
28
28
20
20
20
50
50
75
2K
2K
2K
136
136
136
0°C to +70°C
-40°C to +85°C
0°C to +70°C
SX48BD/TQ 48 36 50 4K 262 0°C to +70°C
SX52BD/PQ 52 40 50 4K 262 0°C to +70°C
SX48BD-I/TQ 48 36 50 4K 262 -40°C to +85°C
SX52BD-I/PQ 52 40 50 4K 262 -40°C to +85°C
SX52BD75/PQ 52 40 75 4K 262 0°C to +70°C
SX52BD100/PQ 52 40 100 4K 262 0°C to +70°C

SX User’s Manual Rev. 3.1 18 © 2000 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
Figure 1-3 is a diagram showing the general naming conventions for SX family devices. The part
number consists of several fields that specify the manufacturer, pin count, feature set, memory size,
supply voltage, operating temperature range, and package type, as indicated in Figure 1-3.
Throughout this manual, the term “SX” refers to all the devices listed in Table 1-1, except where
indicated otherwise.
Figure 1-3 Part Numbering Reference Guide
SX18ACXX-I/SO
Packa
g
e T
y
pe
Extended Temperature
Memor
y
Size
Feature Set
Pin Count
SceniX
A = 512 word
B = 1k word
C = 2k word
D = 4k word
Speed
Blank = 50 MHz
75 = 75 MHz
100 = 100 MHz
DP = SDIP
SO = SOP
SS = SSOP
TQ = Tiny PQFP
PQ = PQFP
Blank = 0°C to +70°C
I = -40°C to +85°C