Texas Instruments MSMC User manual

KeyStone Architecture
Literature Number: SPRUGW7
November 2010
Multicore Shared Memory Controller (MSMC)
User Guide

ø-ii KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010
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Release History
Release Date Chapter/Topic Description/Comments
1.0 November 2010 All Initial Release

Contents
SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide ø-iii
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Contents
Release History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ø-ii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ø-v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ø-vi
Preface ø-vii
About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ø-vii
Notational Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ø-vii
Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ø-viii
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ø-viii
Chapter 1
Introduction 1-1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Chapter 2
MSMC Architecture 2-1
2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 C66x CorePac Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.2 System Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.2.1 System EMIF Access Slave Interface (SES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.2.2 System MSMC SRAM Access Slave Interface (SMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.3 System Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.4 External Memory Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Memory Protection and Address Extension (MPAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 MPAX Segment Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.2.2 MPAX Segment Register Reset Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.3 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.2.3.1 Memory Protection Fault Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.4 Address Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.4.1 SES Aliased Access to MSMC RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.2.4.2 SMS MPAX Address Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.4.3 Address Extension Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.3 MSMC Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.3.1 MSMC SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.3.2 MSMC Memory Banking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.3.3 MSMC Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
2.4 MSMC Register Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
2.5 Error Detection and Correction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
2.5.1 Parity Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
2.5.2 EDC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
2.5.2.1 Error Correction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
2.5.3 EDC Error Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
2.5.4 Background Parity Refresh-Scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
2.5.4.1 Scrubbing Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
2.5.4.2 Scrubbing Error Logging and Statistics Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
2.5.5 Parity RAM Initialization at Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
2.6 MSMC Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
2.7 Reset Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19
2.8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20

Contents
ø-iv KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010
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Chapter 3
MSMC Registers 3-1
3.1 MSMC Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Peripheral Identification Register (PID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3 EDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.1 MSMC SRAM EDC Control Register (SMEDCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.2 MSMC SRAM Correctable EDC Error Address Register (SMCERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.3 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
3.3.4 MSMC SRAM Non-correctable EDC Error Address Register (SMNCERRAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
3.3.5 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.6 MSMC Scrubbing Error Corrected Address Register (SMCEA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
3.3.7 MSMC Scrubbing Non-Correctable Address Register (SMNCEA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.3.8 MSMC Scrubbing Error Counter Register (SMSECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 Bandwidth Management Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.1 Starvation Bound Register for C66x CorePac Slave Ports (SBNDCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.4.2 Starvation Bound Register for SMS Port (SBNDM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.4.3 Starvation Bound Register for SES Port (SBNDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
3.5 MPAX Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.5.1 SMS_MPAXHn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.5.2 SMS_MPAXLn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
3.5.3 SES_MPAXHn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.5.4 SES_MPAXLn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.6 Memory Protection Fault Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.6.1 MSMC Memory Protection Fault Address Register (SMPFAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.6.2 MSMC Memory Protection Fault Extension Register (SMPFXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.6.3 MSMC Memory Protection Fault Requestor Register (SMPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.6.4 MSMC Memory Protection Fault Control Register (SMPFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
3.7 MSMC Configuration Write Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.7.1 Configuration Lock Control for Non-MPAX Registers (CFGLCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.7.2 Configuration Unlock Control for Non-MPAX Registers (CFGULCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.7.3 Configuration Lock Status for Non-MPAX Registers (CFGLCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
3.7.4 Configuration Lock Control for SMS MPAX Registers (SMS_MPAX_LCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
3.7.5 Configuration Unlock Control for SMS MPAX Registers (SMS_MPAX_ULCK) . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
3.7.6 Configuration Lock Status for SMS MPAX Registers (SMS_MPAX_LCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
3.7.7 Configuration Lock Control for SES MPAX Registers (SES_MPAX_LCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.7.8 Configuration Unlock Control for SES MPAX Registers (SES_MPAX_ULCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.7.9 Configuration Lock Status for SES MPAX Registers (SES_MPAX_LCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
3.8 MSMC Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
3.8.1 Interrupt Enabled Status Register (SMESTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
3.8.2 Interrupt Raw Status Register (SMIRSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
3.8.3 Interrupt Raw Status Clear Register (SMIRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
3.8.4 Interrupt Enable Status Register (SMIESTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
3.8.5 Interrupt Enable Clear Register (SMIEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24
Index IX-1

List of Tables
SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide ø-v
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List of Tables
Table 2-1 MPAX Segment Size Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 2-2 MSMC Protection Fault Reporting Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Table 2-3 Replacement Address Used as Per-Segment Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Table 2-4 Starvation counters per requestor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Table 2-5 MSMC Configuration Write Lock Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
Table 2-6 MSMC EDC Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
Table 2-7 Soft Error Correction Actions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
Table 2-8 MSMC Interrupt Control Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
Table 2-9 MSMC Memory Map for TCI6616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Table 2-10 MSMC Memory Map for TCI6608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Table 3-1 MSMC Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Table 3-2 Peripheral ID Register (PID) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Table 3-3 MSMC SRAM EDC Control Register (SMEDCC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 3-4 MSMC SRAM Correctable EDC Error Address Register (SMCERRAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 3-5 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Table 3-6 MSMC SRAM Non-correctable EDC Error Address Register (SMNCERRAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . 3-6
Table 3-7 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 3-7
Table 3-8 MSMC Scrubbing Error Corrected Address Register (SMCEA) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Table 3-9 MSMC Scrubbing Non-Correctable Address Register (SMNCEA) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Table 3-10 MSMC Scrubbing Error Corrected Counter Register (SMSECC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Table 3-11 Starvation Bound Register for C66x CorePac Slave Ports (SBNDCn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Table 3-12 Starvation Bound Register for SMS Port (SBNDM) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Table 3-13 Starvation Bound Register for SES Port (SBNDE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-14 SMS_MPAXHnField Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-15 SMS_MPAXLn Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Table 3-16 SES_MPAXHnField Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
Table 3-17 SES_MPAXLnField Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
Table 3-18 MSMC Memory Protection Fault Address Register (SMPFAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Table 3-19 MSMC Memory Protection Fault Extension Register (SMPFXR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 3-20 MSMC Memory Protection Fault Requestor Register (SMPFR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Table 3-21 MSMC Memory Protection Fault Control Register (SMPFCR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
Table 3-22 Configuration Lock Control for Non-MPAX Registers (CFGLCK) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
Table 3-23 Configuration Unlock Control for Non-MPAX Registers (CFGULCK) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Table 3-24 Configuration Lock Status for Non-MPAX Registers (CFGLCKSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
Table 3-25 Configuration Lock Control for SMS MPAX Registers (SMS_MPAX_LCK) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . .3-17
Table 3-26 Configuration Unlock Control for SMS MPAX Registers (SMS_MPAX_ULCK) Field Descriptions . . . . . . . . . . . . . . . . . . . .3-18
Table 3-27 Configuration Lock Status for SMS MPAX Registers (SMS_MPAX_LCKSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . .3-18
Table 3-28 Configuration Lock Control for SES MPAX Registers (SES_MPAX_LCK) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
Table 3-29 Configuration Unlock Control for SES MPAX Registers (SES_MPAX_ULCK) Field Descriptions . . . . . . . . . . . . . . . . . . . . . .3-19
Table 3-30 Configuration Lock Status for SES MPAX Registers (SES_MPAX_LCKSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . .3-20
Table 3-31 Interrupt Enabled Status Register (SMESTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Table 3-32 Interrupt Enabled Status Register (SMIRSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
Table 3-33 Interrupt Raw Status Clear Register (SMIRC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Table 3-34 Interrupt Enabled Status Register (SMIESTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
Table 3-35 Interrupt Enable Clear Register (SMIEC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24

List of Figures
ø-vi KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010
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List of Figures
Figure 2-1 MSMC Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2 MPAX Segment Register Set Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 2-3 MSMC SRAM Bank Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Figure 2-4 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14
Figure 3-1 Peripheral ID Register (PID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 3-2 MSMC SRAM EDC Control Register (SMEDCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-3 MSMC SRAM Correctable EDC Error Address Register (SMCERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-4 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-5 MSMC SRAM Non-correctable EDC Error Address Register (SMNCERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-6 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-7 MSMC Scrubbing Error Corrected Address Register (SMCEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-8 MSMC Scrubbing Non-Correctable Address Register (SMNCEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-9 MSMC Scrubbing Error Corrected Counter Register (SMSECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-10 Starvation Bound Register for C66x CorePac Slave Ports (SBNDCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-11 Starvation Bound Register for SMS Port (SBNDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-12 Starvation Bound Register for SES Port (SBNDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
Figure 3-13 SMS_MPAXHn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Figure 3-14 SMS_MPAXLn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Figure 3-15 SES_MPAXHn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-16 SES_MPAXLn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-17 MSMC Memory Protection Fault Address Register (SMPFAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Figure 3-18 MSMC Memory Protection Fault Extension Register (SMPFXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Figure 3-19 MSMC Memory Protection Fault Requestor Register (SMPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 3-20 MSMC Memory Protection Fault Control Register (SMPFCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
Figure 3-21 Configuration Lock Control for Non-MPAX Registers (CFGLCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
Figure 3-22 Configuration Unlock Control for Non-MPAX Registers (CFGULCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
Figure 3-23 Configuration Lock Status for Non-MPAX Registers (CFGLCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
Figure 3-24 Configuration Lock Control for SMS MPAX Registers (SMS_MPAX_LCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Figure 3-25 Configuration Unlock Control for SMS MPAX Registers (SMS_MPAX_ULCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
Figure 3-26 Configuration Lock Status for SMS MPAX Registers (SMS_MPAX_LCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
Figure 3-27 Configuration Lock Control for SES MPAX Registers (SES_MPAX_LCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
Figure 3-28 Configuration Unlock Control for SES MPAX Registers (SES_MPAX_ULCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-29 Configuration Lock Status for SES MPAX Registers (SES_MPAX_LCKSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Figure 3-30 Interrupt Enabled Status Register (SMESTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
Figure 3-31 Interrupt Enabled Status Register (SMIRSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Figure 3-32 Interrupt Raw Status Clear Register (SMIRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
Figure 3-33 Interrupt Enabled Status Register (SMIESTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
Figure 3-34 Interrupt Enable Clear Register (SMIEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24

SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide ø-vii
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Preface
About This Manual
The Multicore Shared Memory Controller (MSMC) manages traffic among multiple
C66x CorePacs, DMA, other mastering peripherals, and the EMIF in a multicore
device. MSMC also provides a shared on-chip SRAM that is accessible by all the C66x
CorePacs and the mastering peripherals on the device.
Notational Conventions
This document uses the following conventions:
• Commands and keywords are in boldface font.
• Arguments for which you supply values are in italic font.
• Terminal sessions and information the system displays are in screen font.
• Information you must enter is in boldface screen font.
• Elements in square brackets ([ ]) are optional.
Notes use the following conventions:
Note—Means reader take note. Notes contain helpful suggestions or references
to material not covered in the publication.
The information in a caution or a warning is provided for your protection. Please read
each caution and warning carefully.
CAUTION—Indicates the possibility of service interruption if precautions are
not taken.
WARNING—Indicates the possibility of damage to equipment if precautions are
not taken.

ø-viii KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010
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Preface
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Related Documentation from Texas Instruments
Trademarks
TMS320C66x and C66x are trademarks of Texas Instruments Incorporated.
All other brand names and trademarks mentioned in this document are the property of Texas Instruments
Incorporated or their respective owners, as applicable.
C66x CorePac User Guide SPRUGW0
DDR3 Memory Controller for KeyStone Devices User Guide SPRUGV8
External Memory Interface (EMIF16) for KeyStone Devices User Guide SPRUGZ3

SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 1-1
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Chapter 1
Introduction
1.1 "Overview" on page 1-2
1.2 "Terminology" on page 1-2
1.3 "Features" on page 1-2

1.1 Overview
1-2 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010
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Chapter 1—Introduction
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1.1 Overview
The Multicore Shared Memory Controller (MSMC) manages traffic among multiple
C66x CorePacs, DMA, other mastering peripherals, and the EMIF in a multicore
device. MSMC also provides a shared on-chip SRAM that is accessible by all the C66x
CorePacs and the mastering peripherals on the device. MSMC provides memory
protection for accesses to the MSMC SRAM and DDR3 memory from system masters.
1.2 Terminology
1.3 Features
The MSMC module has the following features:
• Level 2 or Level 3 shared MSMC SRAM that is accessible by all the C66x CorePacs
and the mastering peripherals
• Memory protection for accesses to MSMC SRAM and DDR3 memory from
system masters
• 32-bit to 36-bit address extension for larger addressing space
Term Definition
MPAX Memory Protection and Address Extension
MSMC Multicore Shared Memory Controller
PrivID Privilege Identification for the System Masters
SCR Switched Central Resource
SES System EMIF Access Slave Interface
SMS System MSMC SRAM Access Slave Interface

SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 2-1
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Chapter 2
MSMC Architecture
2.1 "Functional Overview" on page 2-2
2.2 "Memory Protection and Address Extension (MPAX)" on page 2-4
2.3 "MSMC Memory" on page 2-10
2.4 "MSMC Register Access Control" on page 2-12
2.5 "Error Detection and Correction Support" on page 2-14
2.6 "MSMC Interrupt Control" on page 2-18
2.7 "Reset Considerations" on page 2-19
2.8 "Memory Map" on page 2-20

2.1 Functional Overview
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2.1 Functional Overview
Figure 2-1 shows a high-level view of the MSMC module that includes the main
interfaces, memory, and subunits.
Figure 2-1 MSMC Functional Block Diagram
The MSMC has slave interfaces to connect to the C66x CorePacs (one slave interface
per CorePac), two slave interfaces to connect to the system interconnect (SCR), one
master port to connect to the EMIF, and one master port to connect to the system
interconnect (SCR).
2.1.1 C66x CorePac Slave Interfaces
The MSMC has slave interfaces to connect to the MDMA port of C66x CorePacs.
C66x CorePacs use this interface to access the MSMC on-chip memory, the external
memory, and EMIF memory-mapped registers through the MSMC-EMIF master port
or system level resources through the MSMC-system master port.
2.1.2 System Slave Interfaces
The MSMC has two slave interfaces to handle accesses from mastering peripherals in
the system (apart from the C66x CorePacs connected to MSMC through the C66x
CorePac slave ports) for the MSMC SRAM and EMIF.
RAM banks,
256 bits per
bank
C66x
CorePac
Slave Port
C66x
CorePac
Slave Port
Syst em
Slave Port
for shared
SRAM
(SMS)
Syst em
Slave Port
for
external
memor y
(SES)
MSMC System
Mast er Por t
MSMC EMI F
Mast er Por t
MSMC Datapath
x N C66x CorePacs
Arbitration for Banks
256
256
256
256
256
Memory
Pr otect i on
and
Extensi on
Unit
( MPAX)
256 256
VBUSM 256
events
VBUSM 256
VBUSM 256
Memory
Pr otect i on
and
Extensi on
Unit
( MPAX)
MSMC
EMIF – 64-bit
DDR3
SCR
SCR
VBUSM 256
EDC for SRAM

2.1 Functional Overview
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2.1.2.1 System EMIF Access Slave Interface (SES)
The SES interface handles accesses to external DDR3 memory and memory-mapped
registers inside the EMIF module that originate from a system master that is not a C66x
CorePac. Accesses presented on this interface to any addresses outside of the address
range mapped to the external memory or the EMIF memory mapped registers result in
an addressing error returned to the requesting master. The address width on this
interface is 32 bits; address extension to a 36-bit external memory address is done
inside the MSMC as described in ‘‘Memory Protection and Address Extension
(MPAX)’’ on page 2-4.
2.1.2.2 System MSMC SRAM Access Slave Interface (SMS)
The SMS interface handles accesses to MSMC SRAM that originate from a system
master that is not a C66x CorePac. Accesses from masters in the system to MSMC
configuration registers are also expected to be presented at this interface. Any accesses
from the SMS interface that do not address the MSMC SRAM or configuration
registers result in an addressing error returned to the requesting master.
2.1.3 System Master Interface
The MSMC features one master interface for the C66x CorePac to access system
resources other than the MSMC SRAM, MSMC MMRs, DDR3 memory, and the EMIF
MMRs. Traffic from the system slave interfaces does not pass through the master
interface.
2.1.4 External Memory Master Interface
The external memory interface (EMIF) module is connected to the MSMC through the
external memory master interface. The address width for this interface is 36 bits
because supports the extended memory addressing space beyond 4 GB. The MSMC
implements an address extension to 36 bits as described in ‘‘Memory Protection and
Address Extension (MPAX)’’ on page 2-4.

2.2 Memory Protection and Address Extension (MPAX)
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2.2 Memory Protection and Address Extension (MPAX)
The MSMC module supports an external memory addressing space of up to 64 GBytes
(addressable with a 36-bit address), even though the native DSP and the SoC addressing
remains at 32-bits. TCI6616 or TCI6608 devices can support only up to 8 GBytes of
external memory space. The C66x CorePac uses its own MPAX units to extend 32-bit
addresses to 36-bit addresses before presenting them to the MSMC module. The slave
interfaces on the MSMC that receive addresses from all other masters in the system
must extend the address inside the MSMC. These interfaces also provide support for
memory protection for accesses from system masters to MSMC SRAM, external
memory, and memory-mapped registers in the EMIF. Both system slave interfaces (SES
and SMS) feature a Memory Protection and Address Extension (MPAX) unit similar to
the MPAX unit inside the C66x CorePac that combines these functions into a single
process. This allows the creation of a programmer’s view of the memory that is
consistent between the C66x CorePac and other system masters (particularly DMA
masters).
2.2.1 MPAX Segment Operation
The MPAX process is performed for a variable-sized segment of memory and is
controlled with a register pair for each segment: MPAXH and MPAXL control
registers.
• The MPAXH specifies the base address and size of the segment to match.
• The MPAXL specifies the replacement address and permissions for the segment.
Each MPAX unit provides eight pairs of control registers per Privilege ID (PrivID) of
the system masters, which allows eight independent and potentially overlapping
variable-size memory segments to be operated upon.
The control register memory-mapped space for the MSMC is not operated upon by the
MPAX hardware. Addresses presented for any system accesses to the MSMC control
registers through the SMS port are used as such.
Figure 2-2 shows how the MPAX segment registers are organized. The MPAX segment
registers are described in ‘‘MPAX Segment Registers’’ on page 3-11.
All the MPAX registers in the MSMC are readable by any of the connected C66x
CorePacs and also by system masters through the SMS port. Write-access control to
these registers can be coordinated with the aid of semaphores external to the MSMC as
well as through the locking mechanism for MSMC configuration registers. Accesses to
the segment registers through system masters is automatically protected as these
registers are addressed by PrivID such that each PrivID has access to only its set of eight
pairs of segment registers. Accesses to MPAX segment registers with a mismatched
PrivID will generate a protection error.

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Figure 2-2 MPAX Segment Register Set Layout
SMS_MPAXH_0_0 SMS_MPAXL_0_0
SMS_MPAXH_0_7 SMS_MPAXL_0_7
SMS_MPAXH_0_6 SMS_MPAXL_0_6
SMS_MPAXH_0_5 SMS_MPAXL_0_5
SMS_MPAXH_0_4 SMS_MPAXL_0_4
SMS_MPAXH_0_3 SMS_MPAXL_0_3
SMS_MPAXH_0_2 SMS_MPAXL_0_2
SMS_MPAXH_0_1 SMS_MPAXL_0_1
SES_MPAXH_0_0 SES_MPAXL_0_0
SES_MPAXH_0_7 SES_MPAXL_0_7
SES_MPAXH_0_6 SES_MPAXL_0_6
SES_MPAXH_0_5 SES_MPAXL_0_5
SES_MPAXH_0_4 SES_MPAXL_0_4
SES_MPAXH_0_3 SES_MPAXL_0_3
SES_MPAXH_0_2 SES_MPAXL_0_2
SES_MPAXH_0_1 SES_MPAXL_0_1
SMS_MPAXH_F_0 SMS_MPAXL_F_0
SMS_MPAXH_F_7 SMS_MPAXL_F_7
SMS_MPAXH_F_6 SMS_MPAXL_F_6
SMS_MPAXH_F_5 SMS_MPAXL_F_5
SMS_MPAXH_F_4 SMS_MPAXL_F_4
SMS_MPAXH_F_3 SMS_MPAXL_F_3
SMS_MPAXH_F_2 SMS_MPAXL_F_2
SMS_MPAXH_F_1 SMS_MPAXL_F_1
SES_MPAXH_F_0 SES_MPAXL_F_0
SES_MPAXH_F_7 SES_MPAXL_F_7
SES_MPAXH_F_6 SES_MPAXL_F_6
SES_MPAXH_F_5 SES_MPAXL_F_5
SES_MPAXH_F_4 SES_MPAXL_F_4
SES_MPAXH_F_3 SES_MPAXL_F_3
SES_MPAXH_F_2 SES_MPAXL_F_2
SES_MPAXH_F_1 SES_MPAXL_F_1
MPAX register set
for PrivID “0x0”
MPAX register set
for PrivID “0xF”

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2.2.2 MPAX Segment Register Reset Values
At reset, the MPAX segment 0 register-pair has initial values that set up unrestricted
access to the full MSMC SRAM address space and 2 GB of the EMIF address space. All
other segments come up with the permission bits and size set to 0 (that is, no access
map to those segments).
• For each PrivID, SMS_MPAXH[0] is reset to 0x0C000017 and SMS_MPAXL[0]
is reset to 0x00C000BF, (i.e., segment 0 is sized to 16 MB and matches any
accesses to the address range 0x0CXXXXXX).
• For each PrivID, SES_MPAXH[0] is reset to 0x8000001E and SES_MPAXL[0] is
reset to 0x800000BF, (i.e., the segment 0 is sized to 2 GB and matches any accesses
to the address range 0x8XXXXXXX). This 2 GB space starts at the external
memory base address of 0x80000000.
• SMS_MPAXH and SMS_MPAXL for segments 1 through 7 come out of reset as
0x0C000000 and 0x00C00000 respectively. SES_MPAXH and SES_MPAXL for
segments 1 through 7 come out of reset as all zeroes.
These reset settings are provided for the convenience of set-up code. It is recommended
that boot code set up these registers as appropriate for the application.
2.2.3 Memory Protection
For the SES and SMS, the MPAXH register contains the Segment Base Address
(BADDR) field that is matched to the incoming address on the SES port to identify the
addressed segment. The BADDR and the Segment Size (SEGSZ) field describe the
placement and size of the controlled segment. SEGSZ is a five-bit field that can be used
to specify segment sizes ranging from 4 KB to 4 GB in powers of two, as listed in
Table 2-1 ‘‘MPAX Segment Size Encoding’’.
Segments are always sized to a power of two and start on a corresponding power-of-two
boundary (for example, a 4 KB segment always starts on a 4 K boundary, and a 4 GB
segment corresponds to the entire 32-bit address space). For the SMS port MPAX unit,
the maximum allowed segment size is 16 MB (SEGSZ=10111b), which would cover the
full MSMC storage space.
For the MPAX unit in the SES port, a sufficient number of upper bits (depending on
the size specified in the SEGSZ field) of the incoming address are matched against the
BADDR field of all the MPAXH registers corresponding to the access PrivID to select
the MPAXH control register pair to use for memory protection and extension. For
Table 2-1 MPAX Segment Size Encoding
SEGSZ Meaning SEGSZ Meaning SEGSZ Meaning SEGSZ Meaning
00000b Segment disabled 01000b Reserved 10000b 128KB 11000b 32MB
00001b Reserved 01001b Reserved 10001b 256KB 11001b 64MB
00010b Reserved 01010b Reserved 10010b 512KB 11010b 128MB
00011b Reserved 01011b 4KB 10011b 1MB 11011b 256MB
00100b Reserved 01100b 8KB 10100b 2MB 11100b 512MB
00101b Reserved 01101b 16KB 10101b 4MB 11101b 1GB
00110b Reserved 01110b 32KB 10110b 8MB 11110b 2GB
00111b Reserved 01111b 64KB 10111b 16MB 11111b 4GB

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example, for 4 KB segments, all 20 bits of the BADDR field must match the upper
20 bits of the system address. For 16 MB segments, the upper eight bits of the BADDR
field must match the upper eight bits of the C66x CorePac address; the remaining bits
are ignored. For 4 GB segments, no BADDR bits are consulted and all addresses match.
• If an address does not match any of the programmed MPAXH registers and is not
a MSMC configuration register address, the access permissions for the access are
considered to be 0; this results in a protection fault.
• If an address matches multiple MPAXH registers (overlapping segment
descriptors), the highest numbered MPAX register-pair is selected (this is, if the
address matches BADDR in MPAXH5 and in MPAXH2, MPAXH5 is selected).
Using this priority-based matching behavior, multiple MPAX entries can be
programmed for overlapping segments to achieve either non-power-of-two sized
segments or subsegments with different memory protection (and/or extension)
parameters.

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2.2.3.1 Memory Protection Fault Reporting
The MSMC memory protection fault reporting registers are listed in Table 2-2 and
described in ‘‘Memory Protection Fault Reporting Registers’’ on page 3-14.
The MPAXL register contains the permission attributes for supervisor and user
accesses. If an access mismatches MPAXL with the corresponding permission
attributes, a memory fault is triggered that results in the following actions:
• A memory-fault interrupt is generated on the faulting access. This is also
recorded in the SMIRSTAT register (see ‘‘MSMC Interrupt Control’’ on
page 2-18) that contains one event bit per PrivID that is set when an access from
the PrivID faults and is cleared on writing 1 to the associated bit in the SMIRC
register. Only one fault is notified per PrivID; until the interrupt status is cleared
in SMIRC, the next interrupt for that PrivID is not generated.
• The access address causing the fault is captured in the SMPFAR register. If the
fault is the result of the address not matching any of the segment BADDR, the
NM field in the SMPFXR register is set. The master ID and PrivID associated with
the access is also recorded in the SMPFR register. A bus-protection-error status
is returned to the requesting master for the faulting access.
• There is only one fault recorded in the SMPFAR and SMPFXR. The master is
notified with a fault interrupt and receives a bus error for the access. In response,
the master must clear the recorded fault by writing 1 to the CLR bitfield in
SMPFCR before further faults can be recorded.
2.2.4 Address Extension
For access to the SES interface, the 32-bit address is extended to 36 bits by replacing the
appropriate number of upper bits of the address (based on segment size) with a
corresponding portion of the replacement address field (RADDR) in the MPAXL
register that has four more upper bits, as shown in Table 2-3 ‘‘Replacement Address
Used as Per-Segment Size’’.
Table 2-2 MSMC Protection Fault Reporting Register List
Acronym Register Description
SMPFAR Shared Memory Protection Fault Address Register
SMPFXR Shared Memory Protection Fault Extension Register
SMPFR Shared Memory Protection Fault Requestor Register
SMPFCR Shared Memory Protection Fault Control Register
Table 2-3 Replacement Address Used as Per-Segment Size
SEGSZ
SES / SMS RADDR
bits SEGSZ
SES RADDR
bits
SMS RADDR
bits SEGSZ
SES RADDR
bits
SMS RADDR
bits SEGSZ
SES RADDR
bits
00000b Segment disabled 01000b Reserved Reserved 10000b [23:5] [19:5] 11000b [23:13]
00001b Reserved 01001b Reserved Reserved 10001b [23:6] [19:6] 11001b [23:14]
00010b Reserved 01010b Reserved Reserved 10010b [23:7] [19:7] 11010b [23:15]
00011b Reserved 01011b [23:0] [19:0] 10011b [23:8] [19:8] 11011b [23:16]
00100b Reserved 01100b [23:1] [19:1] 10100b [23:9] [19:9] 11100b [23:17]
00101b Reserved 01101b [23:2] [19:2] 10101b [23:10] [19:10] 11101b [23:18]
00110b Reserved 01110b [23:3] [19:3] 10110b [23:11] [19:11] 11110b [23:19]
00111b Reserved 01111b [23:4] [19:4] 10111b [23:12] [19:12] 11111b [23:20]

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This operation is identical to that in the C66x CorePac MPAX unit. Programming the
same values into the BADDR, RADDR, and SEGZ fields will result in an identical
address-extension operation for a system master access.
2.2.4.1 SES Aliased Access to MSMC RAM
Using address remapping in the MPAX unit at the SES port, it is possible to map some
or all of the MSMC SRAM into external memory space and access it through the SES
port. This provides the same ability to alias MSMC memory to external address space
for system masters as is available to the C66x CorePacs through the CorePac MPAX
unit.
The ability to alias external addresses to the SRAM has the following constraints:
• Crossing between MSMC SRAM and external memory endpoints in the course
of a transaction on SES is not supported and results in an addressing error for the
endpoint first addressed in the command.
• Addressing errors get prioritized for reporting over protection errors.
2.2.4.2 SMS MPAX Address Extension
For the SMS interface, the address-extension operation is very similar except that the
generated address maintains bits 31:24 to be the same as the original address (that is,
the start address of the MSMC SRAM). The SMS_MPAXL contains a correspondingly
smaller RADDR field. Note that this resultant address is still a 32-bit address within the
address space of the MSMC SRAM and the operation is that of remapping the address
segment to a different location within the MSMC SRAM.
It is possible to violate the permissions associated with a segment and checked as part
of the memory-protection check by extending the address into a target segment that
has more restrictive permissions. This is actually a valid configuration of the MPAX
registers to carve out subsegments that overlap segments with differing permissions.
• If segment overlap is not desired or intended, it is a good practice to align the level
of restriction in the segment permissions with the MPAX segment matching
priority scheme; that is, configure a less restrictive segment A in a lower
numbered MPAX pair than a more restrictive segment B.
• If the permissions of segment A are intended to be used for the overlap region
between the two segments A and B, configure A in a higher numbered MPAX
pair than the one for segment B.
2.2.4.3 Address Extension Error Reporting
If an SES address extension results in an address that is outside the range of the EMIF
(memory or memory-mapped registers), the MSMC EMIF Master port receives an
addressing error from the EMIF and relays this error to the SES interface.

2.3 MSMC Memory
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2.3 MSMC Memory
2.3.1 MSMC SRAM
MSMC SRAM can serve as a Shared Level 2 or Level 3 memory:
• Shared Level 2 memory—The MSMC memory is cacheable by L1D and L1P
caches; L2 will not cache requests to MSMC SRAM.
• Shared Level 3 memory—The MSMC memory is not directly cacheable at the L2,
but is cacheable in L1D and L1P. However, if it is remapped to an external address
using the address-extension capabilities in the C66x CorePac MPAX, the MSMC
memory can be cached as a shared L3 memory both in the L1 and L2 caches. To
achieve this, the caching must be enabled in MAR registers (using MAR.PC bit)
for the remapped region.
2.3.2 MSMC Memory Banking
The memory is organized using banks that consist internally of two subbanks that hold
adjacently-addressed locations. The addressing of the banks is done so that 64-byte
aligned, 64-byte chunks of memory are located in different banks. In addition, 32-byte
aligned addresses within each 64-byte chunk that are addressed in a bank, are located
in different subbanks. Figure 2-3 ‘‘MSMC SRAM Bank Addressing ’’ shows the
location of consecutive byte addresses in the four-bank organization of the MSMC
memory as they are addressed—bit 6 and 7 of the byte address are used to select
between the four banks and bit 5 of the address is used to select the subbank in the
selected bank.
TCI6616 device has MSMC SRAM size of 2 MB, it is made up of four 512 KB banks.
TCI6608 device has MSMC SRAM size of 4 MB, it is made up of four 1 MB banks.
Figure 2-3 MSMC SRAM Bank Addressing
Bank 3
Subbank 1
E0
1E0
Subbank 0
C0
2C0
1C0
Bank 2
Subbank 0
80
Subbank 1
280
A0
1801A0
Bank 1
Subbank 1
60
160
Subbank 0
40
240
140
Bank 0
Subbank 0
00
Subbank 1
200
20
100
120
220
260
2A0
2E0