SGS ATES Z80 Setup guide

Z80
rM
CPU - INSTRUCTION SET
This book on the instruction set of the Z80 CPU is not intended
exclusively as an application support for the device itself but forms
the second part of the instruction manual for SGS-ATES CLZ80
microcomputer, which is based on the Z80 microprocessor.
The paragraphs are therefore numbered accordingly.

[;07£: Execution time (E.T.) for each instruction
given in nicroseconds for an assuoed 4 HllZ clock.
P.lachine cycles (H) are indicated I/ith total clock
periods (T States). Also indicated are the nuober
States for each M cycle. For exanple:
is
Total
indicates that the instruction consists of 2 nachine
cycles. ihe first cycle contains 4 clock periods (T
States). The second cycle contains 3 clock periods for
a total of 7 clock periods or T States. The instruction
will execute in 1.75 microseconds.
Register format is shown for each instruction with the
most sicnificant bit to the left and the least
significant bit to the right.

Z 80 INSTRUCTION SET
TABLE OF CONTENTS
PAGE SECTION
-8 BIT LOAD GROUP.52.1
-16 BIT LOAD GROUP. 31 2.2
-EXCHANGE,BLOCK TRANSFER
AND SEARCH GROUP .55 2.3
-8 BIT ARITHMETIC AND LOGICAL GROUP 79 2.4
-GENERAL PURPOSE ARITHMETIC
AND CPU CONTROL GROUPS.111 2.5
- 16 BIT ARITHMETIC GROUP 127 2.6
~ROTATE AND SHIFT GROUP 145 2.7
- BIT SET,RESET AND TEST GROUP 185 2.8
-JUMP GROUP.203 2.9
- CALL AND RETURN GROUP 221 2.10
- INPUT AND OUTPUT GROUP 237 2.11
-FLAGS 261 2.12
-INDEX. 267

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LD
r, r'
The contents of any register r are loaded into any
other register r. Note: r,r' identifies any of the
registers A, B, C, D, E, li, or L, assembled as follows
in the object code:
A 111
B 000
COOl
DOlO
E 011
li 100
L 101
If the li register contains the number 8AH, and the E
register contains 10H, the instruction

LD
r,
I a:o~r~< < 01
I,,: in::: 1
The eight-bit integer n is loaded into any register r,
where r identifies register A, n, C, D, E, H or L,
assembled as follows in the object code:
Registerr
A 111
B
000
C
001
D
010
E011
H
100
L
101

LD
(HLJ
r,
The eight-bit contents of memory location (HL) are
loaded into register r, where r identifies register A,
B, C, D, E, H or L, assembled as follo~ls in the object
code:
A 111
BODO
COOl
DOlO
E 011
H 100
L 101
If register pair HL contains the number 7SA1H, and
memory address 7SA1H contains the byte SOH, the
execution of

LD r,
(IX +dJ
1<< 0: < 1: < 0 >I DD
Ia:<-~r~«ol
I., : >: : :,.1
The operand (IX+d) (the contents of the Index Register
IX summed with adisplacement integer d) is loaded into
register r, where r identifiesregisterA,B, C, D, E, H
or L, assembled asfollows in the objectcode:
Register r
A III
B 000
C 001
D 010
E
011
H
100
L
101
Ifthe Index Register IXcontains the number25AFH,the
instruc tion