ST STR91 Series Installation and operating instructions

May 2006 Rev 2 1/20
AN2339
Application note
STR91x hardware development
getting started
Introduction
The STR91x MCUs are derivatives of the STMicroelectronics STR9 family of 32-bit 0.18µ
HCMOS microcontrollers. They combine high CPU performance (CPU frequency up to 96
MHz) with rich peripheral functionalities and enhanced I/O capabilities. They offer up to 96
MIPS directly from Flash memory, very large SRAM with optional battery backup and
support clock generation via PLL or via an external clock. The STR91x can perform signal-
cycle DSP instructions good for speech processing, audio algorithms, and low-end imaging.
This application note provides a complement to the information in the STR91x datasheet
and reference manual by describing the minimum hardware environment required to build
an application around the STR91x. It’s divided into six chapters: minimum hardware
requirements, power supply, clock management, reset control, development and debugging
tool support and basic schematic. Each chapter gives the hardware needed for each
specific section and does not describe the STR91x blocks in detail. To get detailed
description of these features, refer to STR91x datasheet and reference manual or STR910
Eval-Board datasheet.
www.st.com

Contents AN2339
2/20
Contents
1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Analog supply and reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Battery backup supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 External crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 TIM clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Development and debugging tool support . . . . . . . . . . . . . . . . . . . . . . 12
5.1 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 JTAG interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2 JTAG signal integrity and maximum cable lengths . . . . . . . . . . . . . . . . 14
5.2 ETM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 ETM Interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.2 Minimizing signal skew (balancing PCB track lengths) . . . . . . . . . . . . . 16
5.2.3 Minimizing crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.4 Impedance matching and termination . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.5 Rules for series terminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AN2339 Contents
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6 STR91x basic schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Hardware requirements summary AN2339
4/20
1 Hardware requirements summary
In order to build an application around STR91x, the application board should, at least,
provide the following features:
●Power supply
●Clock management
●Reset control
●JTAG/Mictor connector

AN2339 Power supply
5/20
2 Power supply
Figure 1. Power Supply Overview
2.1 Main operating voltages
The STR91x devices are processed in 0.18 µm technology, ARM966E-S RISC core and I/O
peripherals need different power supplies. In fact, STR91x requires two separate operating
voltage supplies. The CPU and memories operate in a range from 1.65V to 2.0V on the
VDD pins, and the I/O ring operates in the 2.7V to 3.3V or 3.0V to 3.6V range on the VDDQ
pins.
All pins need to be properly connected to the power supplies. These connections, including
pads, tracks and vias should have an impedance as low as possible. This is typically
achieved with thick track widths and preferably dedicated power supply planes in multi-layer
PCBs.
In addition, each VDD/VSS and VDDQ/VSSQ pair should be decoupled with ceramic
capacitors which need to be placed as close as possible to the appropriate pins or below the
pins on the contrary side of the PCB. Typical values are 10nF to 100nF, but exact values
depend on the application needs. The following figure shows the typical layout on such a
VDD/VSS pair.
A/D converter
AV
DD
V
DDQ
V
DD
AV
SS
Core
(3V or 3.3V)
SRAM
AV
REF
RTC
V
BATT
V
SSQ
I/O Ring
V
SS
(1.8V)
Note 1
(from 1V
(V
DDQ
)
(V
DDQ
)
up to V
DDQ
)
V
DD
Core
SRAM
RTC
V
BATT
V
SS
(1.8V)
Note 1
(V
DDQ
)
A/D converter
AV
REF_
AV
DD
V
DDQ
AV
SS_
V
SSQ
(3V or 3.3V)
V
SSQ
I/O Ring
(V
DDQ
)
128-pin devices 80-pin devices
Note1: You can connect power to the SRAM with VBATT by firmware

Power supply AN2339
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Figure 2. Typical layout for VDD/VSS pair
2.2 Analog supply and reference
The ADC unit on 128-pin packages has an independent A/D Converter Supply and
Reference Voltage. This means that it has an isolated analog voltage supply input at pin
AVDD to accept a very clean voltage source. The analog voltage supply range on pin AVDD
is the same range as the digital voltage supply on pin VDDQ. Additionally, an isolated
analog supply ground connection is provided on pin AVSS only for further ADC supply
isolation. They offer a separate external analog reference voltage input for the ADC unit on
the AVREF pin for better accuracy on low voltage input, and the voltage on AVREF can
range from 1.0V to VDDQ.
On 80-pin packages, the analog supply is shared with the ADC reference voltage pin, and
the analog ground is shared with the digital ground at a single point in the STR91xF device
on pin AVSS_VSSQ. Also the ADC reference voltage is tied internally to the ADC unit
supply voltage on pin AVCC_AVREF, meaning the ADC reference voltage is fixed to the
ADC unit supply voltage.
2.3 Battery backup supply
You can optionally connect a battery to the VBATT pin (2.5V to 3.5V) of the STR91x so that
SRAM contents are automatically preserved when the normal operating voltage on the VDD
pin is lost or drops below the 1.4V threshold. Automatic switchover of VBATT power to
SRAM can be disabled by firmware if you want the battery to power only the RTC and not
the SRAM.
Note: 1 You are advised to ground all unused pins on ports 0-9 to reduce noise susceptibility, noise
generation, and minimize power consumption. There are no internal or programmable pull-
up resistors on ports 0-9.
2 All pins on ports 0-9 are 5V tolerant
3 Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4 mA sink. Ports 3 and 6 have 8 mA drive
and 8 mA sink.
For more details on the power supply, refer to the STR91xF datasheet.
Via to VSSVia to VDD
Cap.
VDD VSS
STR91x

AN2339 Clock management
7/20
3 Clock management
The STR91x offers a flexible way for selecting the core and peripheral clocks, the devices
have up to four external clock source inputs: Main Oscillator, RTC, USB Clock and TIM
clocks. It also provides one output clock.
Figure 3. Clock Management
3.1 Main oscillator
The source for the main oscillator input is a 4 to 25 MHz external crystals connected to
STR91xF pins X1_CPU and X2_CPU or an external oscillator device connected to pin
X1_CPU, in this case the X2_CPU pin can be left open and not used.
The recommended circuitry for a crystal is shown below. C1, C2 and R1 values depend
greatly on the crystal type and manufacturer. You should ask your crystal supplier for the
best values for these components.
MII_PHYCLK
25MHz PHYSEL
X1_CPU
X2_CPU
X1_RTC
X2_RTC
EXTCLK_T0T1
USB_CLK48M
4-25MHz
48MHz
Main
OSC
RTC
OSC
16-bit prescaler
fOSC
PLL
32.768kHz
fRTC
TIM01CLK
fPLL fMSTR
Master CLK
1/2
1/2
BRCLK
To UART
USBCLK
To US B
To TIM0 & TIM1
EXTCLK_T2T3
16-bit prescaler
TIM23CLK
To TIM2 & TIM3

Clock management AN2339
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Figure 4. Recommended circuitry for crystal oscillator pins X1_CPU and X2_CPU
The values of the load capacitors C1 and C2 also heavily depend on the crystal type and
frequency. For best oscillation stability they normally have the same value. Typical values
are in the range from below 10pF up to 30pF. The parasitic capacitance of the board layout
also needs to be considered and typically adds a few pF to the component values. The
resistor R1 is recommended for feedback stability and has a value of around 1MΩ.
Note: In the PCB layout all connections should be as short as possible. Any additional signals,
especially those that could interfere with the oscillator, should be locally separated from the
PCB area around the oscillation circuit using suitable shielding.
3.2 Real time clock
3.2.1 External crystal
A 32.768 kHz external crystal can be connected to pins X1_RTC and X2_RTC, or an
external oscillator connected to pin X1_RTC to constantly run the real time clock unit. This
32.768 kHz clock source can also be used as an input to the clock control unit to run the
CPU in slow clock mode for reduced power.
3.2.2 Tamper detection
On 128-pin STR91xF devices only, there is a tamper detect input pin, TAMPER_IN, used to
detect and record the time of a tamper event on the end product such as malicious opening
of an enclosure, unwanted opening of a panel, etc. The activation mode of the tamper pin is
programmable to one of two modes:
1. One is Normally Closed/Tamper Open.
2. The second mode will detect when a signal on the tamper input pin is driven from low-
to-high, or high-to-low depending on firmware configuration.
XTAL2
XTAL1
R1
C2C1

AN2339 Clock management
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Figure 5. 32.768 kHz oscillator
3.3 USB clock
STR91x contains a USB 2.0 Full Speed device module interface that operates at a precise
frequency of 48 MHz. This clock is usually provided by an external oscillator connected to
the USB clock pin USB_CLK48M. However, to save board space and cost, the 48 MHz USB
clock can also be generated by the internal PLL using one single external oscillator for both
system and USB module.
Note: Care is required when programming the PLL multiplier and divider factors, not to exceed the
maximum allowed operating frequency (96 MHz). At power up, the CPU defaults to run the
oscillator clock, as the PLL is not ready (locked). The LOCK bit is set when the PLL clock
has stabilized.
3.4 TIM clock
Like the USB interface, TIM0/TIM1 and TIM2/TIM3 can receive an external clock on pin
EXTCLK_T0T1 and EXTCLK_T2T3 respectively.
3.5 Output clock
The STR91xF devices can optionally output a 25 MHz clock to the external Ethernet PHY
interface device via output pin MII_PHYCLK, in this case, the STR91xF must use a 25 MHz
signal on its main oscillator input. The advantage here is that an inexpensive 25 MHz crystal
may be used to source a clock to both STR91xF and the external PHY device. Alternatively
an external 25 MHz oscillator can be connected directly to the external PHY interface
device. In this case the STR91xF can use a crystal at a frequency other than 25 MHz.
X1_RTC
STR91xF
X2_RTC
32 kHz
crystal
For more details concerning capacitance, refer to the crystal manufacturer datasheet.
VCC1
VCC1 can be:
VDDQ: if you don’t want to preserve tamper function when VDD and VDDQare switched off
VBATT: if you want to preserve tamper function when VDD and VDDQ are switched off.
TAMPER_IN

Reset control AN2339
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4 Reset control
There are two types of internal hardware reset, defined as System Reset and Global Reset.
The STR91x device also provides a Reset output signal.
4.1 Reset input
4.1.1 System Reset
A system reset resets all registers except the Clock Control Register, PLL Configuration
Register, System Status Register, Flash Configuration register, Protection register and the
FMI Bank address and Bank size Registers.
A system reset is generated when one of the following events occurs:
●A low level on the RESET_INn pin (External Reset):
– This input signal is active low. It has no internal pull-up to VDDQ. A valid active-low
input signal of tRINMIN = 100ns.
●JTAG Reset Command (JTAG reset):
The JTAG interface has two reset signals connected to the debug target hardware:
–nTRST drives the JTAG nTRST signal on the ARM processor core. It is an open
collector output that is activated whenever the In-Circuit Emulators (ICE) software
has to re-initialize the debug interface in the target system.
–nSRST is a bidirectional signal that both drives and senses the system reset
signal on the target. The open collector output is driven LOW by the debugger to
re-initialize the target system.
●Watchdog reset
– In Watchdog mode, a reset is generated when the counter reaches the end of
count.
For more details, refer to Section 5.1: JTAG interface on page 12
Note: If the nRESET and nTRST signals are linked together, resetting the system also resets the
TAP controller.
4.1.2 Global Reset
A global reset sets all the registers to their reset values, it is generated when one of the
following events occurs:
LVD circuitry
LVD circuitry will always cause a global reset if the CPU VDD source drops below it’s fixed
threshold of 1.4V. However, the LVD trigger threshold to cause a global reset for the I/O
ring’s VDDQ source is set to one of two different levels, depending on the VDDQ operating
range. If VDDQ operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If VDDQ
operation is 3.0V and 3.6V, the LVD threshold is 2.7V.