Sisyph SMB10 User manual

User's Guide
SMB10 Garonne  Phase/Frequency Discriminator
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
Contents
1 Scope 3
2 Overview 3
3 Operation 3
3.1 Frontpanel .............................................. 3
3.1.1 Beat-NoteInput ....................................... 3
3.1.2 SynchronizationInput.................................... 4
3.1.3 Beat-NoteMonitor...................................... 4
3.1.4 PhaseErrorMonitor..................................... 4
3.2 BusHeadersConnections ...................................... 4
3.2.1 PhaseErrorOutput ..................................... 4
3.2.2 SignalGround ........................................ 5
3.2.3 Lock-DetectOutput ..................................... 5
3.2.4 Acquire/TrackOutput.................................... 5
3.2.5 PrescalerControlInputs................................... 5
3.2.6 PowerSupply......................................... 6
3.2.7 PinAssignments ....................................... 6
3.3 PrescalerLocalSettings ....................................... 6
3.4 Jumpers................................................ 7
3.4.1 Acquire/TrackJumper.................................... 7
4 Circuitry 7
4.1 CircuitDescription.......................................... 7
4.2 Printed Circuit Board Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
1 Scope
The information given in this guide applies to the SMB10-R22A module.
2 Overview
The SMB10 module is an electronic board for use in Optical Phase-Locked Loop (OPLL) applications where
the frequency detuning between two laser sources requires tight and quick control.
The elds of the master laser and the slave are mixed in a photodetector providing the information
about their phase oset ∆φ=φM−φS . The detected signal is frequency down-converted at the microwave
frequency fREF using a mixer whose ltered output is applied to the Beat-Note input of the SMB10 module.
During in-lock operation, the frequency oset ∆ν is set by the microwave reference oscillator (REF) and the
local RF oscillator (LO) connected at the Synchronization input of the SMB10
∆ν=νM−νS=fREF +NfLO, (1)
where the integer N refers to the divide ratio of the SMB10's prescaler. The prescaler divide ratio can
be set using digital controls or local settings and a monitoring output provides an attenuated copy of the
beat-note.
During in-lock operation of the OPLL, the SMB10 module acts as a phase discriminator providing an
output voltage related to the phase dierence between the local oscillator and the frequency divided beat-note
Verror =KφφLO −∆φ−φREF
N,
(2)
where Kφ denotes the gain of the phase-frequency discriminator (PFD).
On the other hand, when the OPLL is out-of-lock the SMB10 behaves as a frequency discriminator
Verror =Vmax 1−0.5(∆ν−fREF)/N
fLO 
if fLO >(∆ν−fREF)/N, (3)
Verror =Vmax 0.5fLO
(∆ν−fREF)/N −1
if (∆ν−fREF)/N > fLO . (4)
This error signal is further processed by an high-speed compensator (SMB20 module) to maintain a tight
phase control of the slave laser. A monitoring output provide an distinct copy of the phase error output.
3 Operation
3.1 Front panel
There are a total of three SMAs and one BNC on the front panel, they are described in this section.
3.1.1 Beat-Note Input
The OPLL optical heterodyne signal is down-converted to the reference frequency using a microwave mixer
(not included). Connect the ltered output of this mixer to the Beat-Note Input connector. The mixer
output must be processed if the required signal-to-noise ratio is too low: use an additional amplier stage
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
and/or a band-pass lter to achieve the requirements. In this task, the Beat-Note Monitor output provides
a convenient way to check whether the signal specications are met. The Beat-Note input is internally routed
to the feedback input of the PFD circuit.
[Note] An internal RF low-pass lter is installed on this input path. It is set at 900-MHz cuto frequency
but it can be removed to lower the input bandwidth. This operation requires soldering.
3.1.2 Synchronization Input
Connect to this input the local oscillator providing the synchronization signal. The Synchronization Input
signal is applied to the reference input of the PFD circuit.
3.1.3 Beat-Note Monitor
This output signal is intended for closed-loop spectral analysis of the RF beat-note signal. It provides an
attenuated copy ( −10 dB ) of the Beat-Note input.
3.1.4 Phase Error Monitor
The Error Monitor BNC provides a distinct copy of the dierential Phase Error output. It can be used
for a DC-analysis using a oscilloscope or a signal analyser. It can be also used as a PFD's error signal for
an external controller. The output voltage is
VMonitor =KφφLO −∆φ−φREF
N.
(5)
[Note] The bandwidth of this measurement can be changed by modifying one capacitor on the board. The
gain's sign can be reversed by selecting the related resistor on board. These operations require soldering.
3.2 Bus Headers Connections
Like all SMB-Series modules, the SMB10 has two 50-pin stack-through headers acting as Analog I/O and
Digital I/O busses. In this section each pin allocated to the SMB10 operation is described.
3.2.1 Phase Error Output
The PFD's error signal is transmitted to the bus using the dierential pair ERROR-POS and ERROR-
NEG . The module using this signal  such as the high-speed compensator SMB20  retrieves the phase
error information with a dierential input stage
VError =VERROR POS −VERROR NEG =KφφLO −∆φ−φREF
N.
(6)
[Note] The bandwidth of this measurement can be changed by modifying one capacitor on the board. An
additional roll-o pole is also provided for specic loop-gain shaping. The pole's frequency is set via one
capacitor (not installed by default). These operations require soldering.
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
3.2.2 Signal Ground
A clean signal ground GND is provided as a reference for measurements purpose. Do not connect this pin
to a ground signal , use a dierential sense circuit.
3.2.3 Lock-Detect Output
This active-low digital output can be used as a feedback signal in a lock-acquisition procedure. The
/LOCKED signal goes low when an "in-lock" condition is approached, i.e. if the time delay between
the rising edges of the inputs of the PFD circuit remains within 80 ps . These events are averaged through
a smoothing lter before the buer stage. To allow the /LOCKED output to be asserted, the in-lock
condition has to be maintained during 300 ns at least.
3.2.4 Acquire/Track Output
This output can be used as a feedback signal in a lock-acquisition procedure. It is a copy of the Lock-Detect
Output signal. The Acquire/Track output signal goes low when a lock condition is approached, i.e. if
the time delay between the rising edges of the inputs of the PFD circuit remains within 80 ps . These events
are averaged through a smoothing lter before the buer stage.
A typical lock-acaquisition procedure is described : until the digital Acquire/Track output remains
high, the controller operates in phase acquisition mode and a search pattern is applied to the slave laser's
frequency. This mode of operation is switched to the tracking mode when the signal goes low : here, the
controller's loop-gain is maximal to maintain lock and track the master's phase changes. To allow the
Acquire/Track output to be asserted, the in-lock condition has to be maintained during 300 ns at least.
[Note] The Acquire/Track Output signal is directly routed to the SMA91 Autolock Controller module
through the DIO stack-through connector. To connect this signal to the Autolock Controller module, the
jumper JMP1 must be soldered. Refer to the SMA91 Autolock Controller's documentation for more details.
3.2.5 Prescaler Control Inputs
The divide ratio N of the prescaler is set by 3 digital inputs /PDR0 , /PDR1 and /PDR2 . The 3-bit
control word depends on the integrated circuit used for the prescaler as indicated in Tables 1 and 2. The
Prescaler Local Settings switches must be o to allow digital control using the lines of the DIO bus .
PDR0 PDR1 PDR2 N
low high high 8
low high low 4
low low low 2
Table 1: MC12093-Prescaler control using the digital inputs.
PDR0 PDR1 PDR2 N
high high high 80
high high low 40
high low low 20
low low low 10
Table 2: MC12080-Prescaler control using the digital inputs.
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
3.2.6 Power Supply
The module needs analog ±15 V and digital +5 V power supplies. It is recommended to use the SMB00
module to connect these sources to the PFD.
3.2.7 Pin Assignments
The pin allocations of the Analog I/O and Digital I/O stack-through headers are given in Tables 3 and
4.
Signal label Pin assignment Direction
ERROR-POS AIO.38 output
ERROR-NEG AIO.40 output
GND AIO.39 output
−15 V AIO.45 input
+15 V AIO.47 input
±15 V return AIO.49 input
Table 3: Analog I/O connector pin assignments.
Signal label Pin assignment Direction
/PDR0 DIO.41 input
/PDR1 DIO.40 input
/PDR2 DIO.42 input
/LOCKED DIO.39 output
ACQ/TRACK DIO.6 output
+5 V DIO.47 & DIO.48 input
+5 V return DIO.49 & DIO.50 input
Table 4: Digital I/O connector pin assignments.
3.3 Prescaler Local Settings
In addition to digital control, the divide ratio of the prescaler can be set by 3 switches SW1-1 , SW1-2 and
SW1-3 located on the printed circuit board. Use these switches if remote control is not required, otherwise
the switches must remain in o position. The conguration depends on the integrated circuit in use for the
prescaler according Tables 5 and 6. The digital /PDR0, /PDR1 and /PDR2 control pins should be left open
or set high .
SW1-1 SW1-2 SW1-3 N
on o o 8
on o on 4
on on on 2
Table 5: MC12093-Prescaler control using the Local Settings switches.
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
SW1-1 SW1-2 SW1-3 N
o o o 80
o o on 40
o on on 20
on on on 10
Table 6: MC12080-Prescaler control using the Local Settings switches.
3.4 Jumpers
There is one jumper on the SMB10's printed circuit board.
3.4.1 Acquire/Track Jumper
This normally open jumper is used to connect the Acquire/Track Output to the SMA91 Autolock Con-
troller module. In order the Autolock Controller to operate, a 0 Ω resistor must be mounted on the the
JMP1 footprint. Can be left open if not used.
4 Circuitry
4.1 Circuit Description
The ltered output of the microwave mixer is applied to the Beat-Note input connector. The low-pass lter
RF1 provides an additional mixer-products attenuation. By default, its cut-o frequency is set to 900 MHz .
The coupled output ( −10 dB) of RF2 is connected to the Beat-Note monitor connector while the main output
is amplied ( +20 dB ) by the RF gain-block RF3. Its output level is now sucient to drive the prescaler U11
 MC12093 or MC12080 depending of the desired divide ratios. Operation at N= 1 is obtained without
any prescaler circuit. In this case, the prescaler circuit has to be removed and a zero-ohm resistor (R51) is
installed. If the MC12080 is used, the resistor R52 may be required. The prescaler divide ratio is controlled
by the PDR signals coming from the digital interface.
The output of the prescaler is then applied to a PECL-level translator stage (U4) whose the dierential
output pair drives the feedback pins of the LVPECL phase/frequency comparator U7. The Synchronization
input is also translated into PECL levels using another AC-coupled receiver (U3). Its outputs are routed to
the reference terminals of the PFD.
The dierential output of the phase/frequency discriminator is applied to a low-pass lter reducing the
harmonics of the Synchronization signal. The Phase Error signal is given by the dierential amplier U2
whose outputs are connected to the Analog I/O bus header through 50-ohm resistors. Additional pole are
set using the optional capacitors C14 and C15. This features is useful to shape the overall loop-gain of the
OPLL. It also increases the SNR of the measurement. An identical circuit is used to provide the Phase Error
monitor output.
The sampled and smoothed lock-detect output of the phase/frequency comparator is applied to the
comparator U1 to provide a digital signal indicating that an locked-operation is approached.
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
4.2 Printed Circuit Board Legend
Figure 1: The SMB10-R22A PCB legend.
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User's Guide
SMB10-SN03-P22A SMB10 Garonne  Phase/Frequency Discriminator
Document Revision History
Release Comments
SMB10-SN03-P22A rst release
Document identier
This document is identied as SMB10-SN03-P22A .
Notice
Information in this document is subject to change without notice. Copyright c  SISYPH, 2022. All rights
reserved.
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