Skyworks Si5386 User manual

Si5386 Rev. E Reference Manual
Overview
This reference manual is intended to provide system, PCB design, signal integrity, and
software engineers the necessary technical information to successfully use the Si5386
device in end applications. The official device specifications can be found in the Si5386
data sheet.
The Si5386 is a high-performance, clock generator for small cell applications that de-
mand the highest level of integration and phase noise performance. Based on Skyworks
Solutions’ fourth-generation DSPLL technology, the Si5386 combines frequency synthe-
sis and jitter attenuation in a highly integrated digital solution. A single low phase noise
XO connected to the XA/XB input pins provides the reference for the device. This all-dig-
ital solution provides superior performance that is highly immune to external board distur-
bances such as power supply noise.The device configuration is in-circuit programmable
via an SPI or I2C serial interface and is easily stored in non-volatile memory (NVM) for
applications which require preconfigured clocks at start-up or after reset.
Work Flow Expectations with ClockBuilder™ Pro and the Register Map
This reference manual is to be used to describe all the functions and features of the
parts in the product family with register map details on how to implement them. It is im-
portant to understand that the intent is for customers to use the ClockBuilder™ Pro soft-
ware to provide the initial configuration for the device. Although the register map is docu-
mented, all the details of the algorithms to implement a valid and optimum frequency
plan are fairly complex and are beyond the scope of this document. Real-time changes
to the frequency plan and other operating settings are supported by the devices. Pro-
gramming the Si5386 is made easy with Skyworks' ClockBuilder Pro software available
at https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software.
RELATED DOCUMENTS
•Si5386 Data Sheet
•Si5386A-E-EVB Evaluation Kit
•Si5386A-E-EVB User Guide
•Si5386A-E-EVB Schematic, BOM and
layout files
•Recommended XO Reference Manual
•AN1165: Configuring Si538x Devices for
JESD204B/C Wireless Applications
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Table of Contents
1. Functional Description............................5
1.1 DSPLL.................................5
1.2 LTE Frequency Configuration .........................5
1.3 Configuration for JESD204B Subclass 1 Clock Generation ...............7
1.4 DSPLL Loop Bandwidth ...........................8
1.4.1 Fastlock ...............................8
1.4.2 Holdover Exit Bandwidth .........................9
1.5 Dividers Overview .............................9
2. Modes of Operation ............................ 10
2.1 Reset and Initialization ...........................11
2.1.1 Updating Registers During Device Operation ..................12
2.1.2 NVM Programming ...........................13
2.2 Free Run Mode ..............................13
2.3 Lock Acquisition Mode ...........................13
2.4 Locked Mode ..............................13
2.5 Holdover Mode ..............................14
2.6 VCO Freeze Mode.............................16
3. Clock Inputs............................... 17
3.1 Input Source Selection ...........................17
3.1.1 Manual Input Switching..........................17
3.1.2 Automatic Input Switching .........................18
3.2 Types of Inputs ..............................19
3.2.1 Unused Inputs.............................21
3.2.2 Use Case Scenario: Using More Than Two Inputs.................22
3.2.3 Hitless Input Switching with Phase Buildout ...................22
3.2.4 Ramped Input Switching .........................23
3.2.5 Hitless Switching, Loss of Lock (LOL), and Fastlock ................23
3.2.6 Glitchless Input Switching .........................23
3.2.7 Slew Rate Considerations .........................24
3.3 Fault Monitoring .............................25
3.3.1 Input Loss of Signal (LOS) Fault Detection ...................26
3.3.2 Out-of-Frequency (OOF) Detection......................28
3.3.3 Loss of Lock (LOL) Fault Monitoring .....................30
3.3.4 Interrupt Pin (INTR) ...........................32
4. Output Clocks .............................. 34
4.1 Output Crosspoint Switch ..........................34
4.1.1 Output R Divider Synchronization ......................35
4.2 Performance Guidelines for Outputs .......................36
4.2.1 Optimizing Output Phase Noise .......................37
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4.3 Output Signal Format ............................37
4.4 Output Driver Supply Select .........................38
4.5 Differential Outputs ............................39
4.5.1 Differential Output Terminations .......................39
4.5.2 Differential Output Amplitude Controls.....................40
4.5.3 Differential Output Common Mode Voltage Selection................41
4.5.4 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML .........42
4.6 LVCMOS Outputs .............................43
4.6.1 LVCMOS Output Terminations .......................43
4.6.2 LVCMOS Output Impedance and Drive Strength Selection ..............44
4.6.3 LVCMOS Output Signal Swing .......................44
4.6.4 LVCMOS Output Polarity .........................45
4.7 Output Enable/Disable ...........................46
4.7.1 Output Driver State When Disabled .....................47
4.7.2 Synchronous Output Enable/Disable Feature ..................48
4.7.3 Automatic Output Disable During LOL.....................48
4.7.4 Automatic Output Disable During LOSXAXB ..................49
4.7.5 Output Driver Disable Source Summary ....................50
4.8 Static Output Skew Control ..........................51
4.9 Dynamic Output Skew Control .........................53
5. Zero Delay Mode ............................. 54
6. Serial Interface.............................. 56
6.1 I2C Interface ...............................58
6.2 SPI Interface...............................60
7. Field Programming ............................ 65
8. XAXB External References ......................... 66
8.1 Performance of External References ......................66
9. XO and Device Circuit Layout Recommendations................. 67
9.1 Si5386 64-Pin QFN External XO Layout Recommendations ...............67
10. Power Management ........................... 73
10.1 Power Management Features ........................73
10.2 Power Supply Recommendations .......................73
10.3 Power Supply Sequencing .........................74
10.4 Grounding Vias .............................74
11. Base vs. Factory Preprogrammed Devices ................... 75
11.1 "Base" Devices (a.k.a. "Blank" Devices) .....................75
11.2 "Factory Preprogrammed" (Custom OPN) Devices .................75
11.3 Part Numbering Summary ..........................75
12. Register Map .............................. 76
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12.1 Page 0 Registers.............................76
12.2 Page 1 Registers.............................91
12.3 Page 2 Registers.............................98
12.4 Page 3 Registers............................104
12.5 Page 4 Registers............................106
12.6 Page 5 Registers............................107
12.7 Page 9 Registers............................117
12.8 Page A Registers ...........................119
12.9 Page B Registers ...........................124
12.10 Page C Registers ...........................129
13. Appendix—Custom Differential Amplitude Controls ...............130
14. Revision History.............................132
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1. Functional Description
1.1 DSPLL
The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock
frequency or free run from the reference clock. It consists of a phase detector, a programmable digital loop filter, a high-performance
ultra-low-phase-noise analog VCO, and a user configurable feedback divider. Use of an external XO provides the DSPLL with a stable
low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free run or Holdover modes. No other
external components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power
supplies and other uncontrolled noise sources that normally exist on printed circuit boards.
The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-vola-
tile memory (NVM) or RAM. The combination of input dividers (P0-P3), frequency multiplication (M), output division (N), and output
division (R0A-R9A) allows the generation of a wide range of frequencies on any of the outputs. All divider values for a specific
frequency plan are easily determined using the ClockBuilder Pro software.
1.2 LTE Frequency Configuration
The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.
The flexible combination of dividers and a high frequency VCO allows the device to generate multiple output clock frequencies for
applications that require ultra-low phase-noise and spurious performance. The table below shows a partial list of possible output
frequencies for LTE applications. The Si5386's DSPLL core can generate up to five asynchronous frequencies. These frequencies are
distributed to the output dividers using a configurable crosspoint mux. The output R dividers allow further division for up to 12 unique
integer-related frequencies on the Si5386. The ClockBuilder Pro software utility provides a simple means of automatically calculating
the optimum divider values (P, M, N and R) for the frequencies listed below. In addition to the LTE frequencies, the Si5386 device can
simultaneously generate wireline clocks like 156.25 MHz, 155.52 MHz, 125 MHz, etc. and system clocks like 100 MHz, 33 MHz, 25
MHz, etc.
Si5386 Rev. E Reference Manual • Functional Description
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Table 1.1. Example List of Possible LTE Clock Frequencies
LTE Device Clock Fout (MHz)1
15.36
19.20
30.72
38.40
61.44
76.80
122.88
153.60
184.32
245.76
307.20
368.64
491.52
614.40
737.28
983.04
1228.80
1474.56
1638.4
1843.2
2106.51428571
2457.6
2949.12
Note:
1. R output dividers allow other frequencies to be generated. These
are useful for applications like JESD204B SYSREF clocks.
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1.3 Configuration for JESD204B Subclass 1 Clock Generation
The Si5386 can be used as a high-performance, fully-integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete
VCXO and loop filter components. The Si5386 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks
(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF
clocks to drive JESD204B ADCs, DACs, FPGAs, or other logic devices. The Si5386 will clock up to six JESD204B subclass 1 targets,
using six DCLK/SYSREF pairs. If SYSREF clocking is implemented in external logic, then the Si5386 can clock up to 12 JESD204B
targets. Not limited to JESD204B applications, each of the 12 outputs is individually configurable as a high performance output for
traditional clocking applications.
For applications which require adjustable static delay between the DCLK and SYSREF signals, the Si5386 supports up to four DCLK/
SYSREF pairs, each with independently adjustable delay. An example of an adjustable delay JESD204B frequency configuration is
shown in the following figure. In this case, the N0 divider determines the device clock frequencies while the N1-N4 dividers generate the
divided SYSREF used as the lower frequency frame clock. Each output N divider also includes a configurable delay (Δt) for controlling
deterministic latency. This example shows a configuration where all the device clocks are controlled by a single delay (Δt0) while the
SYSREF clocks each have their own independent delay (Δt1 –Δt4), though other combinations are also possible. The bidirectional
delay is programmable over ±8.6 ns in 68 ps steps. See 4.8 Static Output Skew Control for more information on delay control. The
SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register
writes.
IN_SEL[1:0]
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P1
÷P0
÷P2
÷P3
DSPLL
LPFPD
÷M
÷N1
÷N2
÷N3
÷N4
OUT6b
VDDO6
OUT6
VDDO7
VDDO0
OUT0Ab
OUT0A
OUT0b
OUT0
÷R6
÷R0A
OUT7b
OUT7
÷R7
OUT5b
VDDO5
OUT5
÷R5
OUT1b
VDDO1
OUT1
VDDO2
÷R1
OUT2b
OUT2
÷R2
OUT8b
VDDO8
OUT8
÷R8
OUT3b
VDDO3
OUT3
VDDO4
÷R3
OUT4b
OUT4
÷R4
VDDO9
OUT9b
OUT9
OUT9Ab
OUT9A
÷R9
÷R0
÷R9A
Device
Clocks
4x SYSREF
÷N0
÷5
t0
t1
t2
t3
t4
Figure 1.1. Si5386 Block Diagram
Si5386 Rev. E Reference Manual • Functional Description
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1.4 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL
loop bandwidth settings in the range of 20 Hz to 4 kHz are available for selection. The DSPLL loop bandwidth register values are
determined using ClockBuilder Pro.
CBPro chooses the PLL parameters so that peaking in passband of the PLL is less than 0.1 dB.
Note: After manually changing bandwidth parameters, the BW_UPDATE bit must be set high to latch the new values into operation.
This update bit will latch the new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.
Table 1.2. DSPLL Loop Bandwidth Registers
Register Name Hex Address
[Bit Field]
Function
BW_PLL 0x0508[7:0]-0x050D[7:0] Determines the loop BW for the DSPLL.
Parameters are generated by ClockBuilder
Pro.
BW_UPDATE 0x0514[0] Writing a 1 to this register bit will latch
Loop, Fastlock, and Holdover Exit BW pa-
rameter registers.
1.4.1 Fastlock
Selecting a low DSPLL loop bandwidth (e.g., 20 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows
setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop
bandwidth settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings up to 4 kHz are available for selection. Fastlock
bandwidth should generally be set from 10x to 100x the loop bandwidth for optimal results. Once lock acquisition has completed,
the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or
disabled independently by register control.
Note: The BW_UPDATE_PLLx update bit will latch new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.
Table 1.3. DSPLL Fastlock Bandwidth Registers
Register Name Hex Address
[Bit Field]
Function
FASTLOCK_BW_PLL 0x050E[5:0]-0x0513[5:0] Determines the Fastlock BW for the DSPLL. Parameters
are generated by ClockBuilder Pro.
FASTLOCK_AUTO_EN 0x052B[0] Auto Fastlock Enable/Disable.
0: Disable Auto Fastlock (default)
1: Enable Auto Fastlock
FASTLOCK_MAN 0x052B[1] Force Fastlock.
0: Normal Operation (default)
1: Force Fastlock
The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in section 3.3 Fault Monitoring.
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1.4.2 Holdover Exit Bandwidth
In additional to the Loop and Fastlock bandwidths, a user-selectable bandwidth is available when exiting holdover and locking or
relocking to an input clock when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the Loop bandwidth by
default. Note that the BW_UPDATE bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.
Table 1.4. DSPLL Holdover Exit Bandwidth Registers
Register Name Hex Address
[Bit Field]
Function
HOLDEXIT_BW 0x059D[5:0]–0x05A2[5:0] Determines the Holdover Exit BW for
the DSPLL. Parameters are generated by
ClockBuilder Pro.
1.5 Dividers Overview
There are four divider classes within the Si5386. Figure 1.1 Si5386 Block Diagram on page 7 shows all of these dividers. All divider
values for the Si5386 may be either Fractional or Integer. For best phase noise performance, integer dividers are preferred.
• P0-P3: Input clock wide range dividers (0x0208–0x022F)
• 48-bit numerator, 32-bit denominator
•Min. value is 1; Max. value is 224 (Fractional-P divisors must be > 5)
• Practical range limited by phase detector and VCO range
• Each divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset All will also update the P divider values
• M: DSPLL feedback divider (0x0515–0x051F)
• 56-bit numerator, 32-bit denominator
•Max. value is 224 (Fractional-M divisors must be > 10)
• Practical range limited by phase detector and VCO range
• The M divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset will also update M divider values.
• The DSPLL includes an additional divide-by-5 in the feedback path. Manually calculated M divider register values must be
adjusted accordingly.
• N: Output divider (0x0302-0x0338)
• 44-bit numerator, 32-bit denominator
•Min. value is 5, Max. value is 224 (Fractional-N divisors must be > 10)
• Each N divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset will also update N divider values.
• R: Final output divider (0x0247-0x026A)
• 24-bit field
•Min. value is 2, Max. value is 225-2
• Only even integer divide values: 2,4,6, etc.
• R Divisor=2 x (Field +1). For example, Field=3 gives an R divisor of 8.
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2. Modes of Operation
After initialization, the DSPLL will operate in one of the following modes: Free run, Lock-Acquisition, Locked, VCO Freeze, or Holdover.
These modes are described further in the sections below.
No valid
input clocks
selected
Lock Acquisition
(Fast Lock)
Locked
Mode
Holdover
Mode
Phase lock on
selected input
clock is achieved
An input is
qualified and
available for
selection
No valid input
clocks available
for selection
Free Run
Valid input clock
selected
Reset and
Initialization
Power-Up
Selected input
clock fails
Yes
No
Holdover
History
Valid?
Other Valid
Clock Inputs
Available?
No
Yes
Input Clock
Switch
VCO Freeze
State
An input is
qualified and
available for
selection
Figure 2.1. Modes of Operation
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2.1 Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the SPI or I2C serial interface is possible once this
initialization period is complete. No output clocks will be generated until the initialization is complete.
There are two types of resets available. A Hard Reset is functionally similar to a device power-up. All registers will be restored to the
values stored in NVM, and all circuits including the serial interface, will be restored to their initial state. A Hard Reset is initiated using
the RSTb pin or by asserting the Hard Reset bit. A Soft Reset bypasses the NVM download and is used to initiate in-system register
configuration changes. The table below lists the reset and control registers.
Table 2.1. Reset Registers
Register Name Hex Address
[Bit Field]
Function
HARD_RST 0x001E[1] Writing a 1 to this register bit performs the same func-
tion as power cycling the device. All registers will be
restored to their NVM values.
SOFT_RST 0x001C[0] Writing a 1 to this register bit performs a Soft Reset
of the device. Initiates register configuration changes
without reloading NVM.
Power-Up
Serial interface ready
RSTb
pin asserted
Hard Reset bit
asserted
Initialization
NVM download
Soft Reset bit
asserted
Figure 2.2. Initialization from Hard Reset and Soft Reset
The Si5386 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from
internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate
specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply
voltages applied to its VDD and VDDA pins.
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2.1.1 Updating Registers During Device Operation
If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock
indefinitely). Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or
SOFT_RST requires the following special sequence of writes. The following are the affected registers:
Control Register(s)
P0_NUM / P0_DEN 0x0208 – 0x0211
P1_NUM / P1_DEN 0x0212 – 0x021B
P2_NUM / P2_DEN 0x021C – 0x0225
P3_NUM / P3_DEN 0x0226 – 0x022F
Px_UPDATE 0x0230
P0_FRACN_MODE / P0_FRAC_EN 0x0231
P1_FRACN_MODE/ P1_FRAC_EN 0x0232
P2_FRACN_MODE / P2_FRAC_EN 0x0233
P3_FRACN_MODE/ P3_FRAC_EN 0x0234
MXAXB_NUM / MXAXB_DEN 0x0235 – 0x023E
MXAXB_UPDATE 0x023F
PLL lockup can easily be avoided by using the following the preamble and postamble write sequence when one of these registers is
modified during device operation. ClockBuilder Pro software adds these writes to the output file by default when Exporting Register
Files.
1. To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:
Register Value
0x0B24 0xC0
0x0B25 0x00
0x0540 0x01
2. Wait 625 ms for the device state to stabilize.
3. Then modify all desired control registers.
4. Write 0x01 to Register 0x001C (SOFT_RST) to perform a Soft Reset once modifications are complete.
5. Write the postamble by updating the following control bits using Read/Modify/Write sequences:
Register Value
0x0540 0x00
0x0B24 0xC3
0x0B25 0x02
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2.1.2 NVM Programming
The NVM is two-time writable by the user. Once a new configuration has been written to NVM, the old configuration is no longer
accessible.
While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct
values are written into the NVM:
• VDD and VDDA power must both be stable throughout the process.
• No additional registers may be written during the polling. This includes the page register at address 0x01. DEVICE_READY is
available on every register page, so no page change is needed to read it.
• Only the DEVICE_READY register (0xFE) should be read during this time.
The procedure for writing registers into NVM is as follows:
1. Write all registers as needed. Verify device operation before writing registers to NVM.
2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the contents of the NVM bank.
3. Write 0xC7 to NVM_WRITE register.
4. Poll DEVICE_READY until DEVICE_READY=0x0F.
5. Set NVM_READ_BANK 0x00E4[0]=1.
6. Poll DEVICE_READY until DEVICE_READY=0x0F.
Alternatively, Steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the
device to generate a POR. All of these actions will load the new NVM contents back into the device registers.
Note that the I2C_ADDR setting in register 0x000B is not saved as part of this NVM write procedure. To update this register in a
non-volatile way, the "Si534x8x I2C Address Burn Tool" allows updating this value one time. This utility is included in the ClockBuilder
Pro installation and can be accessed under the "Misc" folder in the installation directory.
Table 2.2. NVM Programming Registers
Register Name Hex Address
[Bit Field]
Function
ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.
NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.
NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.
DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept com-
mands when value = 0x0F.
2.2 Free Run Mode
Once power is applied to and initialization is complete the DSPLL will automatically enter Free run mode, generating the output
frequencies determined by the NVM. The frequency accuracy of the generated output clocks in Free run mode is entirely dependent
on the frequency accuracy of the XAXB reference clock. Any temperature drift of this frequency will be tracked at the output clock
frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and lower wander while in Free
run or Holdover modes. Since there is little jitter attenuation from the XAXB pins to the clock outputs, devices should use a low-jitter
XAXB reference clock to minimize output clock jitter.
2.3 Lock Acquisition Mode
The device monitors all inputs for a valid clock. If a valid clock is available for synchronization, the DSPLL will automatically start the
lock acquisition process. If the Fastlock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and
then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate
a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
2.4 Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point,
the XAXB reference clock frequency drift does not affect the output frequency. A loss of lock pin (LOLb) and status bit indicate when
lock is achieved. See section 3.2.4 Ramped Input Switching for more details on the operation of the loss of lock circuit.
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2.5 Holdover Mode
The DSPLL will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks
are available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of
the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical
frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable
window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below.
The window size determines the amount of holdover frequency averaging. This delay value allows recent frequency information to be
ignored for Holdover in cases where the input clock source frequency changes as it is removed.
Programmable delay
Clock Failure
and Entry into
Holdover
time
0s
Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
120s
1s,10s, 30s, 60s
30ms, 60ms, 1s,10s, 30s, 60s
Figure 2.3. Programmable Holdover Window
When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in
Holdover, the output frequency drift is determined by the reference clock temperature drift. If a clock input becomes valid, the DSPLL
will automatically exit the Holdover mode and reacquire lock to the new input clock. This process involves pulling the output clock
frequency to achieve frequency and phase lock with the input clock. This pull-in process is Glitchless and its rate is controlled by the
DSPLL bandwidth or the Fastlock bandwidth, if Fastlock is enabled. These options are register programmable.
The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the
output frequency while in holdover and the desired, new output frequency is measured. It is quite possible that the new output clock
frequency will not be exactly the same as the holdover output frequency because the new input clock frequency might have changed
and the holdover history circuit may have changed the holdover output frequency. The ramp logic calculates the difference in frequency
between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is
calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will
be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be
selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop
BW values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramping is also
used for ramped input clock switching. See 3.2.4 Ramped Input Switching for more information. See AN1057: Hitless Switching using
Si534x/8x Devices for more information on Hitless and Ramped Switching with Rev. E devices.
As shown in Figure 2.1 Modes of Operation on page 10 the Holdover and Free run modes are closely related. The device will only
enter Holdover if a valid clock has been selected long enough for the holdover history to become valid, i.e., HOLD_HIST_VALID = 1.
If the clock fails before the combined HOLD_HIST_LEN + HOLD_HIST_DELAY time has been met, HOLD_HIST_VALID = 0 and the
device will enter Free run mode instead. Note that when switching between input clocks with different (non-0 ppm offset) frequencies,
the holdover history requires a time of 2 * HOLD_HIST_LEN + HOLD_HIST_DELAY to update the average frequency value. If a switch
is initiated before this time, the average holdover frequency will be a value between the old input frequency and the new one.
Note: The Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input
clock is again presented to the DSPLL.
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Table 2.3. Holdover Mode Control Registers
Register Name Hex Address
[Bit Field]
Function
Holdover Status
HOLD 0x000E[5] DSPLL Holdover status indicator.
0: Normal Operation
1: In Holdover/Free run Mode:
HOLD_HIST_VALID = 0 ≥ Free run Mode
HOLD_HIST_VALID = 1 ≥ Holdover Mode
HOLD_FLG 0x0013[5] Holdover indicator sticky flag bit. Remains asserted after the indi-
cator bit shows a fault until cleared by the user. Writing a 0 to the
flag bit will clear it if the indicator bit is no longer asserted.
HOLD_INTR_MSK 0x0019[5] Masks Holdover/Free run from generating INTRb interrupt.
0: Allow Holdover/Free run interrupt (default)
1: Mask (ignore) Holdover/Free run for interrupt
HOLD_HIST_VALID 0x053F[1] Holdover historical frequency data valid.
0: Incomplete Holdover history, Free run mode available
1: Valid Holdover history, Holdover mode available
Holdover Control and Settings
HOLD_HIST_LEN 0x052E[4:0] Window Length time for historical average frequency used in
Holdover mode. Window Length in seconds (s):
Window Length = (2HOLD_HIST_LEN - 1) x 8 / 3 x 10-7
HOLD_HIST_DELAY 0x052F[4:0] Delay Time to ignore data for historical average frequency in
Holdover mode. Delay Time in seconds (s):
Delay Time = 2HOLD_HIST_DELAY x 2 / 3 x 10-7
FORCE_HOLD 0x0535[0] Force the device into Holdover mode. Used to hold the device
output clocks while retraining an upstream input clock.
0: Normal Operation
1: Force Holdover/Free run Mode:
HOLD_HIST_VALID = 0 =>Free run Mode
HOLD_HIST_VALID = 1 =>Holdover Mode
Holdover Exit Control
HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass
0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Hold-
over
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Register Name Hex Address
[Bit Field]
Function
HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit
HOLDEXIT_BW_SEL1 0x052C[4] Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit
RAMP_STEP_INTERVAL 0x052C[7:5] Time Interval of the frequency ramp steps when ramping between
inputs or exiting holdover.
RAMP_STEP_SIZE 0x05A6[2:0] Size of the frequency ramp steps when ramping between inputs
or exiting holdover.
2.6 VCO Freeze Mode
If holdover history is not valid, the DSPLL automatically enters VCO Freeze mode when the selected input clock becomes invalid and
no other valid input clocks are available for selection. The DSPLL uses the last measured input frequency to set the output frequencies
in the VCO Freeze mode. If an input clock becomes valid, the DSPLL automatically exits the VCO Freeze mode and re-acquires lock to
the new input clock.
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3. Clock Inputs
The Si5386 supports four inputs that can be used as inputs to the DSPLL.
3.1 Input Source Selection
The inputs accept ac-coupled clocks that are differential or singled ended such as LVCMOS. In addition, the inputs also accept
dc-coupled CMOS type inputs with 50% or very low input duty cycle. Input selection can be manual (pin or register controlled) or
automatic with user definable priorities. There is a register to select pin or register control, and to configure the input as shown below.
Table 3.1. Input Selection Configuration
Register Name Hex Address [Bit Field] Function
CLK_SWITCH_MODE 0x0536[1:0]
Selects manual or automatic switching modes. Automatic mode can be rever-
tive or non-revertive. Selections are the following:
00 Manual,01 Automatic non-revertive
02 Automatic revertive, 03 Reserved
IN_SEL_REGCTRL 0x052A [0]
0 for pin controlled clock selection
1 for register controlled clock selection
IN_SEL 0x052A [2:1]
0 for IN0, 1 for IN1,
2 for IN2, 3 for IN3 (or FB_IN)
3.1.1 Manual Input Switching
In manual mode, CLK_SWITCH_MODE=0x00.
Input switching can be done manually using the IN_SEL[1:0] device pins from the package or through register 0x052A IN_SEL[2:1]. Bit
0 of register 0x052A determines if the input selection is pin selectable or register selectable. The default is pin selectable. The following
table describes the input selection on the pins. Note that when Zero Delay Mode is enabled, the FB_IN pins will become the feedback
input and IN3 therefore is not available as a clock input. Note, in Zero Delay Mode, register based input clock selection must be done
with IN_SEL (0x052A). If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode.
Table 3.2. Manual Input Selection using IN_SEL[1:0] Pins
IN_SEL[1:0] DEVICE PINS Zero Delay Mode Disabled Zero Delay Mode Enabled
00 IN0 IN0
01 IN1 IN1
10 IN2 IN2
11 IN3 Reserved
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3.1.2 Automatic Input Switching
In automatic mode CLK_SWITCH_MODE = 0x01 (non-revertive) or 0x02 (revertive)
An automatic input switch is available in addition to the above mentioned manual switching option described in 3.1.1 Manual Input
Switching. In automatic mode, the selection criteria is based on input clock qualification, input priority and the revertive option. The
IN_SEL[1:0] pins or IN_SEL[2:1] register bits are not used in automatic input selection. Also, only input clocks that are valid (i.e., with
no active alarms) can be selected by the automatic clock selection. If there are no valid input clocks available the DSPLL will enter the
holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a
higher priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input
will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be
initiated.
Table 3.3. Registers for Automatic Input Selection
Register Name Hex Address [Bit
Field] Function
CLK_SWITCH_MODE 0x0536[1:0]
Selects manual or automatic switching modes. Automatic mode can be revertive
or non-revertive. Selections are the following: 00 Manual,01 Automatic non-rever-
tive 02 Automatic revertive, 03 Reserved
ZDM_EN 0x0487[0]
0: disable zero delay mode
1: enable zero delay mode
ZDM_AUTOSW_EN 0x0487[4]
0: automatic switching disabled for zero-delay mode
1: automatic input switching enabled and input clock selection governed by auto-
matic input switching engine
IN0_PRIORITY 0x0538[2:0]
IN0, IN1, IN2, IN3 priority select for the automatic selection state machine. Priority
selections are 1,2,3,4, or zero for not selected.
IN1_PRIORITY 0x0538[6:4]
IN2_PRIORITY 0x0539[2:0]
IN3_PRIORITY 0x0539[6:4]
IN_LOS_MSK 0x0537[3:0]
Determines the LOS status for IN3,2,1,0 and is used in determining a valid clock
for automatic input selection
0 to use LOS in clock selection logic, 1 to mask LOS from the clock selection logic
IN_OOF_MSK 0x0537[7:4]
Determines the OOF status for IN3,2,1,0 and is used in determining a valid clock
for the automatic input selection
0 to use OOF in the clock selection logic, 1 to mask the OOF from the clock
selection logic
When in zero delay mode (ZDM_EN (0x0487[0]) the phase difference between the output, which is connected to the selected input, will
be nulled to zero. However the IO delay variation will substantially increase in ZDM mode if the Fpfd is below 128 kHz. Phase buildout
is not supported in Zero Delay Mode.
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3.2 Types of Inputs
Each of the four different inputs IN0-IN3 can be configured as ac-coupled differential formats such as LVDS, LVPECL, HCSL, CML, and
ac-coupled single-ended CMOS formats. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled and use the
“Standard” input buffer selection as these pins are internally dc-biased to approximately 0.83 V.
Floating clock inputs are noise sensitive. Add a cap to ground for all non-CMOS unused clock inputs. To place the input into Standard
Mode make sure IN_PULSED_CMOS_EN 0x949 [7:4] = 0. Bit 7 = IN3, Bit 6 = IN2, Bit 5 = IN1 and Bit 4 = IN0. Make sure the corre-
sponding input bit is set to 0 for Standard Mode. If this bit is 1 this will turn on dc-coupled CMOS Mode. Setting IN_PULSED_CMO_EN
enables all dc-coupled CMOS modes described below.
50
100
INx
INxb
50
Standard AC-Coupled Differential
LVDS, LVPECL, CML
Standard AC-Coupled Single-Ended
INx
3.3 V, 2.5 V, 1.8 V
LVCMOS
R1
R2
50
RS
RS matches the CMOS driver to a
50 ohm transmission line (if used)
C1
INxb
*This cap should have less than ~20 ohms of capacitive reactance at the clock input
frequency.
** Only when 3.3 V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if
needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the
output jitter due to faster input slew rate at INx. If attenuation is not needed for
Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1,
and R2 should be physically placed as close as practical to the device input pins.
0.1uF *
0.1uF *
* These caps should have < ~5 ohms capacitive reactance at the clock input frequency.
0.1uF *
0.1uF
0.1uF
Clock IC
Standard
Clock IC
Standard
**
Figure 3.1. AC-Coupled Standard Input Termination Diagrams
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Each of the four different inputs IN0-IN3 can be configured as single-ended dc-coupled standard CMOS, non-standard CMOS or
pulsed CMOS inputs. In all cases, the inputs should be terminated near the device input pins. In these configurations CMOS mode is
enabled via register setting "IN_PULSED_CMOS_EN" = 1 for each input. Note from the data sheet that the Standard CMOS selection
has higher VIL and VIH settings than the non-standard/ pulsed CMOS Input buffer selection. See the data sheet for the max VIL
and min VIH values for both Standard CMOS vs Non-standard CMOS & Pulsed CMOS selection. In general, following the “Standard
AC-Coupled Single-Ended” arrangement shown above will give superior jitter performance than the dc-coupled arrangements below.
Non-Standard or Pulsed CMOS
3.3 V, 2.5 V, 1.8 V LVCMOS
INx
50
*R2
*R1
RS
RS matches the CMOS driver to a 50
ohm transmission line (if used)
INxb
Standard CMOS
INx
3.3 V, 2.5 V, 1.8 V
LVCMOS
Standard CMOS
*R1
*R2
50
RS
RS matches the CMOS driver to a 50
ohm transmission line (if used)
INxb
Clock IC
Non-Standard
Or
Pulsed CMOS
Clock IC
* Attenuation circuit not required for 1.8 V input or if all input specifications in data sheet are met.
* Attenuation circuit recommended but not required if input specifications in data sheet are met.
Figure 3.2. Input Terminations for DC-Coupled Standard CMOS and Non-Standard/Pulsed CMOS Inputs
Standard CMOS refers to a signal with a swing of (1.8 V, 2.5 V or 3.3 V) +/- 5% that complies with the specified maximum VIL and
minimum VIH specifications in the data sheet. Refer to the data sheet for the VIL and VIH specifications. For non-compliant inputs,
a resistive attenuator is required as shown. It is not recommended to add the attenuation circuit for compliant inputs as it adversely
affects the signal integrity at the input pins. Note that maximum input frequency cannot be guaranteed with the attenuator circuit. If an
input exceeds 3.3 V +5% then the input must be attenuated before going into the chip.
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