Skyworks Si5361 User manual

REFERENCE MANUAL
Skyworks Solutions, Inc. • Phone [949] 231-3000 • [email protected] • www.skyworksinc.com
206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
March 21, 2023
1
Si5361/62/63 Reference Manual
Description
This Family Reference Manual is intended to provide
hardware, system, and software engineers the
necessary technical information to successfully use the
Si5361/62/63 in end applications. The official device
specifications and ordering information can be found
in the Si5361/62/63 data sheet.
The Si5361/62/63 jitter attenuating clock multipliers
combine fifth-generation DSPLL and MultiSynth™
technologies to enable any-frequency clock genera-
tion. These parts are used for applications that require
the highest level of jitter performance. The Si5361,
Si5362, and Si5363 are 1-DSPLL, 2-DSPLL, and 3-DSPLL
devices, respectively. These devices are programmable
with a serial interface. Alternatively, on-chip, program-
mable, non-volatile memory (NVM) can be used to
ensure power-up with known frequency configura-
tions.
Free-run, synchronous, and holdover modes of
operation are supported offering both automatic and
manual input clock switching. The loop filter is fully
integrated on-chip eliminating the risk of potential
noise coupling associated with discrete solutions.
Furthermore, the jitter attenuation bandwidth is digi-
tally programmable providing jitter performance opti-
mization at the application level. These devices can
generate any combination of output frequencies from
any input frequency within the specified input and
output range.
The Si5361/62/63 is programmed using Skyworks
ClockBuilder Pro software and can be made to power
up with known frequencies as a factory programmed
custom part or can be ordered as a “custom blank”
part for increased flexibility.
Related Documents
• Si5361/62/63 Data Sheet
• UG514: Si536x-EVB User Guide
• Si55xx, Si540x, and Si536x Recommended XTAL,
XO, VCXO, TCXO, and OCXO Reference Manual
• AN1357: Si5360/61/62/63 Schematic Design and
Board Layout Guidelines
• AN1360: Serial Communications and API Program-
ming Guide for Si536x, Si540x,and Si55xx Devices

REFERENCE MANUAL Si5361/62/63
Skyworks Solutions, Inc. • Phone [949] 231-3000 • [email protected] • www.skyworksinc.com
206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
2March 21, 2023
1. Introduction to the Si5361/62/63 and ClockBuilder Pro
The Si5361/62/63 family are jitter attenuator devices that support flexible frequency planning with up to three
clock domains. This device family is designed to support synchronization in line card solutions for network
applications like Synchronous Ethernet, SONET, SDH, OTN. Other applications include:
• 56 G/112 G/224 G PAM4 SerDes clocking
• GbE/10 GbE/100 G SyncE
• OTN muxponders and transponders
• Medical imaging
• Test and measurement
ClockBuilder Pro software is used to create a frequency plan and custom programmed or custom blank orderable
part number (OPN) for the Si5361/62/63 jitter attenuator. During operation, the Device API embedded on the
clock devices may be used to dynamically adjust or poll the Si5361/62/63 parameters. To learn more about config-
uration settings of the Si5361/62/63, open a ClockBuilder Pro Sample Plan and explore.
This family reference manual provides information on the Si5361/62/63 hardware capabilities. ClockBuilder Pro
and the Device API are discussed further at the end of this document. The full documentation for the Device API
depends on the part number and is available by link from ClockBuilder Pro.
Figure 1. ClockBuilder Pro Front Wizard Front Panel showing Sample Plans

REFERENCE MANUAL Si5361/62/63
Skyworks Solutions, Inc. • Phone [949] 231-3000 • [email protected] • www.skyworksinc.com
206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
3March 21, 2023
2. Possible Si5361/62/63 Jitter Attenuator Applications
This section describes intended use cases and end applications for the Si5361/61/63 family of devices.
2.1. Si5361 Application Example
Typical applications of the Si5361 device include:
• 10/40/100/200/400G networking line cards
• SONET/SHD line cards
• Jitter cleaner
Figure 2 shows the Si5361 used in a typical SyncE architecture as a line card device. It also shows the Skyworks
Si540x device acting as a timing card to distribute timing information from different Building Integrated Timing
Supplies (BITS).
Figure 2. Si5361 as Line Card Device
LAN / WAN
SyncE Line Card
Si5361
112/224 GbE
PHY
112/224 GbE
PHY
Hit les s Swit chin g
Jitter Fi ltering
Frequency Translation
8 kHz
19.44 MHz
25 MHz
DSPLL P
Rx Timing Path
Tx Timing Path
Line Recove re d
Clocks
Si5348
Wa nder Fi lter ing
Hit les s Swit chin g
Holdover
Redundant
Timing Cards
TCXO/
OCXO
BITS A
8 kHz
19. 44 MHz
25 MHz
A
B
LAN / WAN
SyncE Line Card
A
B
Si5361
112/224 GbE
PHY
Hit les s Swit chin g
Jitter Fi ltering
Frequency Translation
8 kHz
19.44 MHz
25 MHz
DSPLL P
Rx Timing Path
Tx Timing Path
Line Recove re d
Clocks
A
B
Line Recovered Timing
Telecom or
Ethernet
Backplane
156. 25 MHz
155. 52 MHz
161. 1328125 MHz
156. 25 MHz
155. 52 MHz
161. 1328125 MHz
Si540x
BITS B
112/224 GbE
PHY
206420-002

REFERENCE MANUAL Si5361/62/63
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4March 21, 2023
2.2. Si5362/63 Application Examples
The application schematic in Figure 3 shows the Si5362/63 devices used in SyncE line cards. These multi-PLL
devices provide independent timing paths to generate ultra-low jitter PHY layer clock frequencies, and at the
same time clean up the recovered PHY clocks and generate output clock frequencies that connect to the Ethernet
backplane.
Figure 3. Si5362/63 as SyncE Line Card
LAN / WAN
SyncE Line Card
Si5362/63
Hit les s Sw itchin g
Jitter Filtering
Frequency Translation
DSPLL P
DSPLL A/B
Rx Timing Path
Tx Timing Path
Lin e Rec overe d
Clocks
112/224 GbE
PHY
112/224 GbE
PHY
8 kHz
19.44 MHz
25 MHz
156.25 MHz
155.52 MHz
161.13 28125 MHz
Si5348
Wander Filtering
Hitless Switching
Holdover
Redundant
Timing Cards
TCXO/
OCXO
BITS A
BITS B
8 kHz
19.44 MHz
25 MHz
A
B
LAN / WAN
SyncE Line Card
A
B
Si5362/63
Hit les s Sw itchin g
Jitter Filtering
Frequency Translation
DSPLL P
DSPLL A/B
Rx Timing Path
Tx Timing Path
Lin e Rec overe d
Clocks
A
B
Line Recovered Timing
Telecom or
Ethernet
Backplane
112/224 GbE
PHY
8 kHz
19.44 MHz
25 MHz
156.25 MHz
155.52 MHz
161.13 28125 MHz
Si540x
112/224 GbE
PHY
206420-003

REFERENCE MANUAL Si5361/62/63
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5March 21, 2023
The Si5362/63 devices can be deployed in IEEE 1588 Precision Time Protocol line card applications, as illustrated in
Figure 4. The reference PLL (DSPLL P) receives the SyncE clocks from the Network Synchronizers such as Skyworks
Si540x family devices. These SyncE input clocks are now used to generate ultra-low jitter Ethernet PHY layer clock
output frequencies. DSPLL P provides jitter filtering for noise picked up over the backplane. The DSPLL A (for
Si5362) and DSPLL A/B (for Si5363) can be used as an independent timing path to generate System clock for the
1588 Time of Day (ToD) counter. The main advantage of this scheme is any changes to DSPLL A/B made to adjust
the ToD counter will not affect the PHY layer.
Figure 4. Si5362/63 in 1588 Application
Note: When multiple inputs are assigned to DSPLL P, switching between them will affect all device outputs.
PHY
FPGA
Si5362/63
DSPLL A/B
ToD
Host
PHY
DSPLL P
n
Timestamps
Si540x
DSPLL B
DSPLL A
Line Card
Host
DCO
Timing Card Primary
Timing Card Secondary
SyncE (primary)
SyncE (secondary)
Sysclk
SyncE SyncE
Tx PHY ’sRx PHY’s
Sysclk
Backplane
DCO Ctrl
DCO Ctrl
206420-004

REFERENCE MANUAL Si5361/62/63
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206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
6March 21, 2023
2.3. Si5363 Application Example
This section describes another popular application for the multi-PLL Si5363 device. Muxponders used in OTN
(Optical Transport Network) protocols help to reduce the number of wavelengths required to transmit the data by
aggregating multiple services into a single wavelength. This increases both the fiber capacity and the overall
network efficiency. The three independent timing paths (DSPLL P, DSPLL A and DSPLL B) provided by the Si5363
device are used to clean up the gapped clock in an OTN Muxponder.
Figure 5. Si5363 in OTN Muxponder Application
Note: When multiple inputs are assigned to DSPLL P, switching between them will affect all device outputs.
Si5363
DSPLL P
DSPLL A
DSPLL B
Data
Clock
Client #3
High Jitter Clock
PHY
Jitter Attenuated
Non-Gapped Clock
Data
Clock
Client #2
High Jitter Clock
PHY
Jitter Attenuated
Non-Gapped Clock
Data
Clock
Client #1
High Jitter Clock
PHY
Jitter Attenuated
Non-Gapped Clock
200-400G OTN
OTN Muxponder
OTN Demapper
112/224 GbE
112/224 GbE
112/224 GbE
206420-005

REFERENCE MANUAL Si5361/62/63
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7March 21, 2023
3. DSPLL and MultiSynth
The DSPLL is responsible for input frequency translation and jitter attenuation. The input dividers (Pxn/Pxd) allow
for integer or fractional division of the input frequency. The DSPLL can perform hitless switching between input
clocks (INx), if enabled. Input switching is controlled manually or automatically using an internal state machine.
The external reference (XTAL or XO) provides a frequency reference, which determines output frequency stability
and accuracy while the device is in free-run or holdover mode. It is also the jitter reference for the device. Note
that either a XTAL on XA/XB or an XO on XO_IN is always required. The high-performance MultiSynth dividers
(NA/NB) generate fractionally related output frequencies for the output stage, while Q dividers generate integer
related output frequencies. A crosspoint switch connects any of the generated frequencies to any of the outputs.
A single MultiSynth output can connect to one or more output drivers. Additional integer division (R) determines
the final output frequency.
For the Si5362/63 devices, each of the DSPLLs operate independently from each other and are controlled through
a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) after having been divided
down by the P dividers, which are either fractional or integer.
Figure 6 shows the block diagram for the Si5361, a single PLL device with two MultiSynth available, NA and NB.
Figure 6. Si5361 Detailed Block Diagram
PD
VCO
DSPLL P
x18
M
P
DIV
÷P
÷P
IN2
÷P
÷P
IN1
÷P
IN0
÷P
IN3
Si5361
OUT1
÷R
OUT0
÷R
OUT3
÷R
OUT2
÷R
OUT17
÷R
OUT5
÷R
OUT4
÷R
OUT6
÷R
÷Q
NB
DIV
XTAL / XO
XO_IN
XO_INb
XA XB
OSC
XTAL
N A
DIV
206420-006

REFERENCE MANUAL Si5361/62/63
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206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
8March 21, 2023
Figure 7 shows the block diagram for the Si5362, a 2 PLL device with one MultiSynth. It can be programmed to
drive the NB divider through either DSPLL P or DSPLL A. If DSPLL A is not used, consider using the Si5361 instead.
Figure 7. Si5362 Detailed Block Diagram
PD
VCO
DSPLL P
x18
M
P
DIV
÷P
÷P
IN2
÷P
÷P
IN1
÷P
IN0
÷P
IN3
Si5362
OUT1
÷R
OUT0
÷R
OUT3
÷R
OUT2
÷R
OUT17
÷R
OUT5
÷R
OUT4
÷R
OUT6
÷R
÷Q
DSPLL A
PD
M A
DIV
N A
DIV
NB
DIV
XTAL / XO
XO_IN
XO_INb
XA XB
OSC
XTAL
206420-007

REFERENCE MANUAL Si5361/62/63
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206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
9March 21, 2023
Figure 8 shows the block diagram for the Si5363, a 3 PLL device. When DSPLL A and/or DSPLL B are not used,
consider using the Si5362 or Si5361 instead.
Figure 8. Si5363 Detailed Block Diagram
PD
VCO
DSPLL P
x18
M
P
DIV
÷P
÷P
IN2
÷P
÷P
IN1
÷P
IN0
÷P
IN3
Si5363
OUT1
÷R
OUT0
÷R
OUT3
÷R
OUT2
÷R
OUT17
÷R
OUT5
÷R
OUT4
÷R
OUT6
÷R
÷Q
DSPLL A
PD
M A
DIV
N A
DIV
DSPLL B
PD
M B
DIV
NB
DIV
XTAL / XO
XO_IN
XO_INb
XA XB
OSC
XTAL
206420-008

REFERENCE MANUAL Si5361/62/63
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3.1. Dividers
The Si5361/62/63 has both fractional and integer frequency dividers. The block diagrams in Figures 6 and 7 show
the location of each divider and how it fits into the signal flow for all the three devices. The ClockBuilder Pro soft-
ware will choose the optimal divide values based on the frequency plan the user wishes to create. A description of
each type of divider is listed below:
• Input P Divider: P3, P3b, P2, P2b, P1, P0
- Integer or Fractional Divide Value
- Minimum value is 1
• DSPLL P Output Q Divider: Q17-Q0
- Integer Only Divide Value
- Open loop divider taps directly off VCO
• DSPLL A/B Output NA, NB Divider
- MultiSynth Divider
- Fractional Divide Value
• DSPLL A/B Feedback MA, MB Divider
- Fractional Divide Value
• Output R Divider: R17-R0
- Integer Only Divide Value
- Minimum value is 2 if signal comes from NA/NB; Minimum value is 1 if signal comes from Q divider
3.2. DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. The DSPLL loop bandwidth is
configurable within the range of 20 Hz to 4 kHz. The loop bandwidth is controlled digitally and remains stable with
less than 0.1 dB of peaking for any loop bandwidth selected. The DSPLL loop bandwidth can be set using
ClockBuilder Pro or from Device API commands during operation. In general, increasing PLL bandwidth speeds up
lock acquisition while decreasing jitter attenuation. For DSPLL P, using loop bandwidth between 20 Hz to 40 Hz
provides a good optimization for both jitter and wander performance.
Selecting a low DSPLL loop bandwidth will generally lengthen the lock acquisition time but also increase jitter
attenuation. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock
acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings enable the DSPLLs to lock faster.
Once lock acquisition has completed, the loop bandwidth of the DSPLL automatically reverts to the nominal DSPLL
Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently using ClockBuilder Pro. If
enabled, when LOL is asserted Fastlock will be automatically applied. When LOL is no longer asserted Fastlock will
automatically be disabled. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL
feature can be found in the fault monitoring section.
For more information, see AN1365: Si5361/62/63 Lock Time Parameters.
3.3. Output Skew Control
Output skew control allows outputs that are derived from the Q dividers to be phase adjusted in steps of 1/fVCO
or 1/(4*fVCO), when fine adjust is enabled. Output skew is programmable and the output delay adjustment range
is displayed in ClockBuilder Pro.
In addition to output skew control, groupings of Q divider clock outputs can be adjusted with dynamic phase
adjust. Dynamic phase adjustment changes the phase of grouped clock outputs to be earlier or later. For more
information see the Device API documentation.

REFERENCE MANUAL Si5361/62/63
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11 March 21, 2023
3.3.1. VCO Frequency Range
In the Si5361/62/63, the VCO frequency range is 10.4 GHz to 13.0 GHz. The output delay (skew) adjustment range
will vary depending on VCO frequency used in the plan. To find the specific fVCO used in a frequency plan, see the
ClockBuilder Pro Design Report.
3.4. Optimizing the Si536x DSPLL and Divider Performance
The Si536x can be used to replace the Si5345/95 jitter attenuator products in circumstances where the user
requires the lowest possible phase noise best jitter performance, and more outputs. There are some PLL architec-
ture differences the user must understand in order to configure the Si536x device for best performance.
1. Outputs requiring the best jitter and phase noise performance should use DSPLL P and Q dividers.
2. In the Si5362 and Si5363 devices, the bandwidth of the DSPLL P must have enough separation from the DSPLL
A and B bandwidths to maintain sufficient isolation from DSPLL P to DSPLL A/B. ClockBuilder Pro sets the
default bandwidth separation to 10x (i.e., the bandwidth of DSPLL P is 10x lower than the bandwidth of both
DSPLL A and DSPLL B). If the bandwidth separation is insufficient, changes in the input of the DSPLL P may
cause transients on DSPLL A/B outputs. DSPLL P →DSPLL A/B bandwidth separation is inversely (linearly)
related to the magnitude of the transient observed at DSPLL A/B output when a step change in frequency is
applied to DSPLL P input.
3. Before finalizing a ClockBuilder Pro configuration, be sure to resolve all output crosstalk errors by rearranging
outputs within ClockBuilder Pro using the Clock Placement Wizard. Clearing any and all clock placement warn-
ings is equally as important as selecting the correct PLLs and dividers for output clocks.
4. DSPLL A and DSPLL B use closed-loop DSPLL P as their holdover reference, just like DSPLL P uses the XTAL/
XO_IN/b as its holdover reference. If DSPLL P is in free-run or holdover, DSPLL A and B stability will revert back
to DSPLL P reference, which is the XTAL/XO_IN/b clocks.
5. When DSPLL A (Si5362) and DSPLL B (Si5362/63) are placed in holdover or free-run, they will track DSPLL P
input clock stability due to point 2) above. When DSPLL A and B are re-locked, the PLLs will go back to tracking
their respective inputs. For more details of the holdover or free-run behavior, see the sections about free-run
and holdover.
6. In the Si5361/62 where routing DSPLL P outputs through the Q dividers or Multisynths (NA or NB) is allowed,
selecting Q dividers will provide the best performance, while selecting the Multisynths allows for greater
frequency flexibility.
7. Output clocks derived from the DSPLL P directly (DSPLL P + Q dividers) will have higher performance than
clocks derived from the combination of DSPLL A/B in series with a Multisynths (DSPLL A + NB).
8. In many cases, the DSPLL A/B for the Si536x fractional division performance is equal to or better than the
Si5345/95 integer (and fractional) division phase noise/jitter performance. Refer to the device datasheets for
jitter specifications.
9. Si536x output jitter as a Mx divider is modulated by DCO commands should be better than what can be
achieved with the Si534x/8x/9x devices.
For more details on the differences between the Si536x and Si539x, see AN1370: Si5361/62/63 vs. Si5392/94/95/
96/97.

REFERENCE MANUAL Si5361/62/63
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12 March 21, 2023
4. Modes of Operation
Once initialization is complete, each of the PLLs of Si5361/62/63 operates independently in one of four modes:
free-run, lock acquisition, locked, or holdover. Figure 9 shows the modes of operation. Each mode is explained in
sections 4.2 through 4.5.
Figure 9. State Machine Modes of Operation
4.1. Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default firmware and config-
uration data from internal non-volatile memory (NVM), and performs other initialization tasks. Communicating
with the device through the serial interface is possible once this initialization period is complete. No clocks will be
generated until the initialization is complete.
There are two types of resets available. A hard reset is functionally similar to a device power-up. All device
settings will be restored to the values stored in NVM, and all circuits will be restored to their initial state including
the serial interface. A hard reset is initiated using the RST pin. A soft reset bypasses the NVM download. Soft reset
can be initiated using Device API commands in ClockBuilder Pro.
For more information about chip reset during programming, see AN1360: Serial Communications and API Pro-
gramming Guide for Si536x, Si540x, and Si55xx Devices.
For information about recommended circuitry to drive the reset pin, see AN1357: Si5360/61/62/63 Schematic
Design and Board Layout Guide.
No valid
input cl ocks
selected
Lock Acquisition
Locked
Mode
Holdover
Mode
Phase lock on
selected input
clock is achi eved
An input is
qualified and
available for
selection
No valid input
clocks available
for selection
Free-run
Valid input clock
sel ected
Reset and
Initi alization
Power-Up
Selected input
clock fai ls
Yes
No
Holdover
History
Valid?
Other Valid
Clock Inputs
Available?
No
Yes
Input Clock
Switch
20 64 20- 00 9

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13 March 21, 2023
4.2. Free-Run Mode
In the Si5361, the free-run frequency accuracy and stability of the generated output clocks is entirely dependent
on the frequency accuracy and stability of the reference clock source (XTAL or XO_IN/b). If a XTAL is connected to
the XA/XB pins, then the clock outputs will generate a frequency at the XTAL accuracy. For example, if a XTAL is
operating at –28 ppm, then clock outputs will also be –28 ppm. The same is true if an XO is connected at the
XO_IN/XO_INb inputs instead of using XTAL at XA/XB.
In the Si5362/63, the DSPLL P free-run frequency accuracy is the same as the Si5361. Additionally, when DSPLL A
(and/or DSPLL B, Si5363) is in free-run, the outputs of that PLL will track DSPLL P input frequency. If DSPLL P has no
valid input clock, the outputs of a free-running DSPLL A (and/or DSPLL B) will track the XTAL/XO frequency. There
is no option for DSPLL A/B to track the XTAL/XO_IN/b frequency in free-run if DSPLL P is locked to an input.
ClockBuilder Pro provides an option to force DSPLL P, DSPLL A, and DSPLL B into free-run on power-up. When
ready to lock the PLL, the host must use the FORCE_HOLDOVER API command. The FORCE_HOLDOVER command
in the Device API is used to force a PLL into or out of holdover mode.
4.3. Lock Acquisition Mode
Lock acquisition modes:
1. Initial Lock refers to the process of locking from the free-run state. Fastlock bandwidths can be applied to ini-
tial lock, if configured in ClockBuilder Pro. Frequency ramping can also be enabled during initial lock.
2. Holdover Exit refers to the process of (re-)locking to an input after the device has previously entered hold-
over. Fastlock bandwidths can be applied to lock from holdover exit, if set in ClockBuilder Pro. Frequency
ramping can also be enabled during holdover exit.
3. Input Switch refers to the process of switching between input clocks either automatically or manually,
depending on the ClockBuilder Pro configuration. Fastlock cannot be enabled during an input switch, but
ramping can be enabled.
4.4. Locked Mode
Once locked, the PLL will generate clock outputs that are both frequency and phase locked to their selected input
clocks. The PLL loop bandwidths can be independently configured. Any frequency changes (e.g., because of tem-
perature variations) of the input clock within the PLL loop bandwidth will be corrected by the loop ensuring 0 ppm
lock to its input clock (IN). Any frequency movement of the input clock within the loop bandwidth of DSPLL P/A/B
will pass through to the clock output of that DSPLL. Likewise, any frequency movement of the input clock outside
of the loop bandwidth of DSPLL P/A/B will be attenuated by that DSPLL.

REFERENCE MANUAL Si5361/62/63
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14 March 21, 2023
4.5. Holdover Mode
Any of the PLLs will automatically enter holdover mode when the selected input clock becomes invalid, provided
that the holdover history is valid, and no other valid input clocks are available for selection. Each PLL uses an aver-
aged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase
and frequency when an input clock suddenly fails. The holdover circuit for each PLL stores historical frequency
data while locked to a valid input clock. The final averaged holdover frequency value is calculated from a program-
mable window within the stored historical frequency data. Both the window size and delay are programmable as
shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay
value allows ignoring frequency data that may be corrupt just before the input clock failure.
The maximum window size is a function of input frequency and is reported in CBPro for each PLL. Up to 5000
seconds of holdover history can be stored, but may be reduced depending on PLL configuration. For calculated
limits, see the DSPLL configuration pages in ClockBuilder Pro.
Figure 10. Programmable Holdover Window
When entering holdover, a PLL will pull its output clock frequency to the calculated averaged holdover frequency.
While in holdover, the output frequency drift is entirely dependent on the external reference clock connected to
the XA/XB or XO_IN/b input. If the input clock becomes valid, a PLL will automatically exit the holdover mode and
re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve fre-
quency and phase lock with the input clock. This pull-in process is glitchless.
In the Si5362/63, when DSPLL A or B is in Holdover mode the outputs of DSPLL A or B track DSPLL P input. If
DSPLL P input is not present, DSPLL A/B in holdover will track the XA/XB or XO_IN/b input.
The PLL output frequency when exiting holdover can be ramped. Just before the exit is initiated, the difference
between the current holdover frequency and the new desired frequency is measured. Using the calculated differ-
ence and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The PLL loop BW does
not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover and free-run.
The ramp rate settings are configurable for initial lock (exit from free-run), exit from holdover, and clock switching.
If ramped holdover exit is disabled, the holdover exit is governed either by (1) the PLL loop BW or (2) the PLL
Fastlock bandwidth, when enabled.
Programmable delay
Clock Failure
and Entry into
Holdover
time
Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
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5. Dynamic Frequency Changes
Using a ClockBuilder Pro configuration, Si5361/62/63 will have clock output at start up. After start up, dynamic fre-
quency changes can be made using either the Digitally-Controlled Oscillator (DCO) function for small changes, or
the Frequency-On-The-Fly (FOTF) function for larger frequency plan changes.
5.1. Digitally-Controlled Oscillator (DCO)
In Si5361/62/63, DCO frequency adjustments are made by modifying DSPLL dividers or MultiSynth dividers.
As discussed in Section 3. DSPLL and MultiSynth, Si5361/62/63 has one, two or three DSPLLs, respectively.
Si5361/62 has one or two Multisynth dividers, respectively.
The DCO function may be applied as follows:
• For Si5361, the DCO can be applied to DSPLL P divider (MP) and to the Multisynth dividers NA and NB.
• For Si5362, the DCO can be applied to DSPLL A divider (MA), DSPLL P divider (MP) and to the Multisynth
divider NB.
• For Si5363, the DCO can be applied to DSPLL A divider (MA), DSPLL P divider (MP) and to DSPLL B divider
(MB).
The DCO can be controlled using a preset incremental control available by hardware GPIO, or by Device API
commands as follows:
• FINC_DCO/FDEC_DCO method. This is the simplest method. FINC_DCO (frequency increment) and FDEC_DCO
(frequency decrement) are triggered by an API command, or with GPIO pins configured as FINC and FDEC. The
frequency step size, range, and the affected divider(s) are configurable through ClockBuilder Pro. Each
FINC_DCO or FDEC_DCO event (Device API command or pin) will increase or decrease the output frequency of
the specified divider(s) by the configured frequency step size.
• VARIABLE_OFFSET_DCO API command. This is the most flexible method. It allows changing the output fre-
quency by one or more step size(s) as defined in ClockBuilder Pro in either the positive or negative direction.
Unlike the FINC_DCO/FDEC_DCO method, the targeted divider (NA, NB, MP) is specified by the Device API
command. The dividers used in the Device API must be enabled in the ClockBuilder Pro configuration. One or
more dividers can be offset using a single Device API command.
A summary of the Device API commands used to make DCO frequency adjustments is provided in Table 1.
DSPLL A and DSPLL B will track the MP DCO when in holdover/free-run, in a fashion identical to the scenario
where DSPLL A/B is placed into holdover and a DSPLL P input frequency transient occurs. MP DCO may cause tran-
sients on DSPLL A/B outputs, if the 10x BW separation is not followed. See 4.5. Holdover Mode for details.
Table 1. DCO Device API Commands
Device API Command Comment
FINC_DCO Increments one or more dividers by a single frequency step de- fined by the ClockBuilder Pro configuration.
FDEC_DCO Decrements one or more dividers by a single frequency step de- fined by the ClockBuilder Pro configuration.
VARIABLE_OFFSET_DCO Applies a frequency change (offset). The offset value (positive or negative) and the divider(s) affected are specified
in a single Device API command.

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5.2. Frequency-On-The-Fly
Frequency-On-The-Fly (FOTF) is a software function that enables Si5361/62/63 to change to a subset of input/out-
put dividers/frequencies while leaving others unchanged and undisturbed. FOTF will not cause phase transients
on outputs not reconfigured.
An example of FOTF usage is to reconfigure an input frequency from 156.25MHz to 161.1328125MHz while the
system is operating.
For more information on FOTF operation, see AN1367: Si55xx/Si540x/Si536x Frequency-on-the-Fly Guide.
6. Zero Delay Mode (ZDM)
Zero delay mode is available on each of the PLLs (DSPLL P, DSPLL A, DSPLL B) for applications that require mini-
mum delay between selected input and outputs. This helps to cancel out the internal delay introduced by the
dividers, the crosspoint switches, and the input and output drivers. The ZDM mode may also be used to cancel out
delay introduced by external buffers.
For more information on applying ZDM, see AN1357: Si8360/61/62/63 Schematic Design and Board Layout Guide.
Zero delay mode is configured using ClockBuilder Pro by selecting both a clock output and input to be ZDM and
making the physical connection. The physical connection is made by opening the internal feedback loop and clos-
ing the loop externally.The external feedback connection can be either single-ended or differential. Note that
phase buildout is disabled while in zero delay mode. Any one of the outputs can be fed back to any one of the INx
pins. However, using the output driver that achieves the shortest trace length will help to minimize the input-to-
output delay.
Figure 11. Internal Feedback vs Zero Delay Mode
Note: ZDM cannot be used on a PLL when DCO is enabled on its M feedback divider.
÷
PD
÷
PD
External Feedback Connection
PLL with Internal Feedback PLL in Zero Delay Mode
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7. Reference Inputs
Si5361/62/63 operates from either a fixed-frequency crystal (XTAL) connected to the XA, XB pins or an external
crystal oscillator (XO) connected to the OSC pins. The internal oscillator (OSC) combined with a low cost external
XTAL produces an ultra low jitter reference clock for the DSPLL. When using an external XO, it is important to
select one that meets the jitter performance requirements of the end application and to ensure that adequate
supply filtering for the XO is provided to avoid power supply noise from creating spurs in the phase noise of the
XO output.
For more details on external references for Si5361/62/63, see Si55xx, Si540x, and Si536x Recommended XTAL, XO,
VCXO, TCXO, and OCXO Reference Manual.
Figure 12. XTAL or XO Reference
7.1. Crystal (XTAL) Reference
The XA/XB inputs are used to provide a fixed frequency reference for the DSPLL. The device includes internal XTAL
loading capacitors which eliminate the need for external capacitors and also has the benefit of reduced noise
coupling from external sources. A crystal in the range of 48 to 54 MHz is recommended for best jitter perfor-
mance. The internal crystal load capacitors have a capacitance of 8 pF.
7.2. Crystal Oscillator (XO) Reference
An alternative to using an external XTAL is to connect a crystal oscillator (XO) directly to the XO_IN/XO_INb Input.
This input accommodates both single-ended CMOS as well as differential XOs. All XOs (differential or otherwise)
must be properly terminated. Reference the XO device datasheet. Additionally, see the input terminations section
in AN1357: Si5360/61/62/63 Schematic Design and Board Layout Guide for more details. Note that it is important
to ensure the power supply for the XO is well filtered to minimize any power supply noise from degrading the XO
output spectrum.
PD
VCO
DSPLL P
Mp
DIV
XA XB
OSC
XTAL
VCO
Reference
Clock
XO_IN/XO_INb
n/c
PD
VCO
DSPLL P
Mp
DIV
XA/XB
n/c
XO_IN
VCO
Reference
Clock
XO
XO_INb
206420-012

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8. Input Clocks
Clock inputs on the Si5361/62/63 can be provided through either a crystal input on XA/XB, external oscillators on
XO_IN/XO_INb pins or any of the four input buffers IN0-IN3. The input buffers may be set as differential or single-
ended input.
The recommended termination schemes for the below input types are provided in:
AN1357: Si5360/61/62/63 Schematic Design and Board Layout Guide.
8.1. Differential Inputs
An input buffer configured as “differential” can accept a variety of differential formats such as LVDS, LVPECL, HCSL,
and CML. The input clock must have a nominally 40–60% duty cycle and be ac-coupled, since the input buffer is
biased internally. The value of the ac coupling capacitor should be chosen such that its reactance is less than 5 Ω
at the input clock frequency. External 100 Ωdifferential termination must also be provided close to the input
buffer pins. The use of split termination is recommended if the increased number of termination components is
not an issue for the PCB layout area.
8.2. CMOS and Dual CMOS Inputs
All inputs can be also be configured in single-ended mode. Note that if IN0/IN1 are selected as single-ended, then
the inverted inputs IN0b/IN1b cannot be used and should be left unconnected. For IN2/IN3 however, all 4 inputs
(IN2/IN2b/IN3/IN3b) can be used as separate inputs. This allows a maximum of six input clocks to be supported.
The input buffers IN0-IN3 are powered via the VDDIN pin. The voltage of the VDDIN pin determines the logic
threshold of the CMOS inputs. If a 3.3 V CMOS is being given to the input buffer, then VDDIN should be set to 3.3
V to ensure that the input buffer is able to properly detect the logic high and low levels of the CMOS signal. If
there is a mix of 1.8 V and 3.3 V CMOS inputs, it is recommended to use VDDIN=1.8 V and add a resistive divider to
attenuate the 3.3 V CMOS input down to 1.8 V.
8.3. Unused Inputs
Any differential input configured as “Enabled” yet not actively being driven by a clock should be properly termi-
nated to avoid introducing system noise.
8.4. Phase Readout (PHRD)
Unused inputs can also be configured as phase readout (PHRD) or phase readout feedback (PHRD_FB) inputs.
These inputs are used to compare input-to-output phase of reference inputs. PHRD_FB inputs can be used to com-
pare an externally fed-back output of the Si5361/62/63 to an input of known phase. These inputs can use the same
alarms such as LOS/OOF/PHMON as the other clock inputs but they are not assigned to a PLL.
8.5. Input Clock Selection
Input selection for the PLL may be done through automatic selection or manual selection. Manual selection is
completed using either the Device API or a GPIO pin selection.
Using ClockBuiler Pro, selecting either Automatic or Manual will change the required configuration parameters on
the tab.

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8.5.1. Manual Input Selection
As stated, a PLL configured for manual input selection will be selected by either Device API or by GPIO. Up to three
GPIO/GPI pins can be used to select inputs. The user can assign each input to one or more pin combinations in
ClockBuilder Pro.
Note: for manual input select using the Device API, the default input is specified in ClockBuilder Pro. If hardware
manual input selection is desired, then the GPIO pins should be configured in ClockBuilder Pro. When the input
select is configured for GPIO, the Device API will have no effect.
8.5.2. Automatic Input Selection
A PLL configured for automatic input selection looks to the input clock priority list and locks to the highest priority
valid input clock. The input clock priority list for the PLL is configured in ClockBuilder Pro. A valid input clock is one
which does not have an active loss-of-signal (LOS) alarm. If the highest priority input clock is lost due to the
assertion of an any of these alarms, then the PLL will automatically lock to the next highest priority valid input
clock.
If the PLL is locked to an input clock and a higher priority input clock becomes valid, the PLL may either be config-
ured to automatically revert to the highest priority input clock or to stay locked to the current input clock. This is
referred to as auto-revert and non-revert modes respectively. This option can be configured in ClockBuilder Pro.
8.6. Smart Input Switching
Depending on the user settings in ClockBuilder Pro, the Si536x can automatically switch inputs without output
phase glitches, using the measured frequency difference between the clocks at the time of the switch. Clock
inputs to the Si536x can be either from the same source (0 ppm, same nominal frequency) or different sources
(non-0 ppm, different nominal frequency). How the Si536x handles the two cases is described in more detail
below.
Regardless of the switching mode, input clock switches are performed on the Si536x without glitches, meaning
there will be no runt pulses generated at the output during the transition.

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8.6.1. Switching Between Non-0 ppm Offset
When switching between non-0 ppm offset, the Si536x performs a frequency-ramped input switch with
user-programmable frequency ramp rate.
Ramped switching allows the DSPLLs to switch between two input clock frequencies, avoiding an abrupt
frequency transient at the output. When the two input clock frequencies are not the same nominal frequency, the
DSPLL will pull in the frequency difference between inputs at the ramp rate set in ClockBuilder Pro from ppb/s to
ppm/s. The loss-of-lock (LOL) indicator will assert while the DSPLL is ramping to the new clock frequency. As
shown Figure 13, frequency ramping can also be done after a phase threshold has been exceeded.
Figure 13. Input Switch Phase Ramp Thresholds
8.6.2. Switching Between 0 ppm Offset
When switching between two clocks synchronized to a common upstream clock domain (0 ppm inputs), Clock-
Builder Pro settings can instruct the Si536x to perform either a Hitless Switch with Phase Buildout (PBO) or a
Phase Pull-in (PPI) switch.
8.6.2.1. Hitless Switch or Phase Buildout (PBO)
Phase buildout is a feature that prevents a phase offset from propagating to the output when switching between
two clock inputs that have a fixed phase relationship. This is referred to as a hitless switch and is commonly
desired for SyncE and other applications to minimize transients during clock switching. Due to the nature of a
phase buildout, the input-to-output delay of the PLL is not preserved.
A hitless switch (phase buildout) can only occur when two input frequencies are frequency locked, meaning they
are traceable to the same source. When phase build out is enabled, the DSPLL simply absorbs the phase
difference between the two input clocks during an input switch. The phase buildout feature supports clock fre-
quencies down to a minimum input frequency of 8 kHz. On the Si536x, phase buildout can be enabled on a per
DSPLL basis.
206420-013