SMSC USB3290 User manual

SMSC USB3290 DATASHEET Revision1.5(11-02-07)
Datasheet
PRODUCT FEATURES
USB3290
Small Footprint Hi-Speed
USB 2.0 Device PHY with
UTMI Interface
Available in a 40 ball lead-free RoHS compliant
(4 x 4 x 0.9mm) VFBGA package
Interface compliant with the UTMI specification
(60MHz, 8-bit bidirectional interface)
Only one required power supply (+3.3V)
Supports 480Mbps Hi-Speed (HS) and 12Mbps Full
Speed (FS) serial data transmission rates
Integrated 45Ωand 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 24MHz
crystal
Latch-up performance exceeds 150mA per EIA/JESD
78, Class II
ESD protection levels of 5kV HBM without external
protection devices
SYNC and EOP generation on transmit packets and
detection on receive packets
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB 2.0
specification
55mA Unconfigured Current (typical) - ideal for bus
powered applications.
83uA suspend current (typical) - ideal for battery
powered applications.
Industrial Operating Temperature -40oC to +85oC
Applications
The USB3290 is the ideal companion to any ASIC, SoC
or FPGA solution designed with a UTMI Hi-Speed USB
device (peripheral) core.
The USB3290 is well suited for:
Cell Phones
MP3 Players
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers

ORDER NUMBER(S):
USB3290-FH FOR 40 BALL, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE
USB3290-FH-TR FOR 40 BALL, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)
Reel Size is 4000 pieces.
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07) 2 SMSC USB3290
DATASHEET
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]
Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
SMSC USB3290 3 Revision 1.5 (11-02-07)
DATASHEET
Table of Contents
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers. . . . . . . . . . . . 16
6.2 High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 System Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.4 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5 RX Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6 USB 2.0 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6.1 High Speed and Full Speed Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8.2 Power On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8.3 Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 8 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Linestate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Test Mode Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.8 HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.9 HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.14 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07) 4 SMSC USB3290
DATASHEET
List of Figures
Figure 2.1 USB3290 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.1 USB3290 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 17
Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 17
Figure 6.3 Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 8.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8.9 USB3290 Application Diagram showing USB related signals . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8.10 USB3290 Application Diagram showing power and miscellaneous signals. . . . . . . . . . . . . . 42
Figure 9.1 USB3290-FH 40 Ball, VFBGA Package Outline & Parameters 4x4x0.9mm Body, Lead-Free
RoHS Compliant 43
Figure 9.2 BGA, 4x4 Taping Dimensions and Part Orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 9.3 Reel Dimensions for 12mm Carrier Tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9.4 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
SMSC USB3290 5 Revision 1.5 (11-02-07)
DATASHEET
List of Tables
Table 4.1 System Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4.4 Biasing and Clock Oscillator Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) . . . . . . . . . . . . . . . . . . . . 14
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4). . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7.1 DP/DM Termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8.1 Linestate States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8.3 USB 2.0 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8.8 HS Detection Handshake Timing Values from Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07) 6 SMSC USB3290
DATASHEET
Chapter 1 General Description
The USB3290 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is
available in a 40 ball lead-free RoHS compliant VFBGA package. The small footprint package makes
the USB3290 ideal for portable consumer electronics applications.
1.1 Product Description
The USB3290 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit.
SMSC’s proprietary technology results in low power dissipation, which is ideal for building a bus
powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which complies
with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate,
while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps.
All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip.
The USB3290 also has an integrated 1.8V regulator so that only a 3.3V supply is required.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
SMSC USB3290 7 Revision 1.5 (11-02-07)
DATASHEET
Chapter 2 Functional Block Diagram
Figure 2.1 USB3290 Block Diagram
PWR
Control
FS SE+
R
X
UTMI
Interface
TX State
Machine
Parallel to
Serial
Conversion
Bit Stuff
NRZI
Encode
TX
LOGIC
Clock
Recovery Unit
Clock
and
Data
Recovery
Elasticity
Buffer
VP
VM
BIASING
Bandgap Voltage Reference
Current Reference
RBIAS
VDD3.3
PLL and
XTAL OSC System
Clocking
FS RX
FS SE-
HS RX
HS SQ
RX State
Machine
Serial to
Parallel
Conversion
Bit Unstuff
NRZI
Decode
RX
LOGIC
DM
TX
1.5kΩ
FS
TX
HS
TX
HS_DATA
HS_CS_ENABLE
HS_DRIVE_ENABLE
OEB
VMO
VPO
RPU_EN
MUX
DP
RXVALID
RXACTIVE
RXERROR
TXREADY
RESET
SUSPENDN
XCVRSELECT
TERMSELECT
OPMODE[1:0]
LINESTATE[1:0]
CLKOUT
TXVALID
DATA[7:0]
XI
XO
1.8V
Regulator

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07) 8 SMSC USB3290
DATASHEET
Chapter 3 Pinout
Figure 3.1 USB3290 Pinout - Top View
TOP VIEW
TSELTXR
SPDN TXV
RST
V33
V33
DP
XSEL GND
CLK
DM
V33
RXA OM0 LS1
LS0OM1
D6
D7
RXV
D0
D5
D2 D3
D4
D1
RB
VIOV18A
XI XO
V18
V33
RXEREN
G
E
C
B
A
F
D
1765432
GND
GND GND
VIO

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
SMSC USB3290 9 Revision 1.5 (11-02-07)
DATASHEET
Chapter 4 Interface Signal Definition
Table 4.1 System Interface Signals
NAME DIRECTION ACTIVE LEVEL DESCRIPTION
RESET
(RST) Input High Reset. Reset all state machines. After coming out of
reset, must wait 5 rising edges of clock before asserting
TXValid for transmit.
See Section 7.8.3
XCVRSELECT
(XSEL) Input N/A Transceiver Select. This signal selects between the FS
and HS transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.
TERMSELECT
(TSEL) Input N/A Termination Select. This signal selects between the FS
and HS terminations:
0: HS termination enabled
1: FS termination enabled
SUSPENDN
(SPDN) Input Low Suspend. Places the transceiver in a mode that draws
minimal power from supplies. Shuts down all blocks not
necessary for Suspend/Resume operation. While
suspended, TERMSELECT must always be in FS mode
to ensure that the 1.5kΩpull-up on DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current
CLKOUT
(CLK) Output Rising Edge System Clock. This output is used for clocking receive
and transmit parallel data at 60MHz.
OPMODE[1:0]
(OM1)
(OM0)
Input N/A Operational Mode. These signals select between the
various operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved
LINESTATE[1:0]
(LS1)
(LS0)
Output N/A Line State. These signals reflect the current state of the
USB data bus in FS mode, with [0] reflecting the state of
DP and [1] reflecting the state of DM. When the device is
suspended or resuming from a suspended state, the
signals are combinatorial. Otherwise, the signals are
synchronized to CLKOUT.
[1] [0] Description
0 0 0: SE0
0 1 1: J State
1 0 2: K State
1 1 3: SE1

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DATASHEET
Table 4.2 Data Interface Signals
NAME DIRECTION ACTIVE LEVEL DESCRIPTION
DATA[7:0]
(D7)
.
.
.
(D0)
Bidirectional High Data bus. 8-bit Bidirectional mode.
TXVALID DATA[7:0]
0 output
1 input
TXVALID
(TXV) Input High Transmit Valid. Indicates that the DATA bus is valid for transmit. The
assertion of TXVALID initiates the transmission of SYNC on the USB
bus. The negation of TXVALID initiates EOP on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must
not be changed on the de-assertion or assertion of TXVALID. The
PHY must be in a quiescent state when these inputs are changed.
TXREADY
(TXR) Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always
have data available for clocking into the TX Holding Register on the
rising edge of CLKOUT. TXREADY is an acknowledgement to the
SIE that the transceiver has clocked the data from the bus and is
ready for the next transfer on the bus. If TXVALID is negated,
TXREADY can be ignored by the SIE.
RXVALID
(RXV) Output High Receive Data Valid. Indicates that the DATA bus has received valid
data. The Receive Data Holding Register is full and ready to be
unloaded. The SIE is expected to latch the DATA bus on the rising
edge of CLKOUT.
RXACTIVE
(RXA) Output High Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
RXERROR
(RXE) Output High Receive Error.
0: Indicates no error.
1: Indicates a receive error has been detected.
This output is clocked with the same timing as the receive DATA lines
and can occur at anytime during a transfer.
Table 4.3 USB I/O Signals
NAME DIRECTION ACTIVE LEVEL DESCRIPTION
DP I/O N/A USB Positive Data Pin.
DM I/O N/A USB Negative Data Pin.
Table 4.4 Biasing and Clock Oscillator Signals
NAME DIRECTION ACTIVE LEVEL DESCRIPTION
RBIAS
(RB) Input N/A External 1% bias resistor. Requires a 12kΩresistor to ground.
Used for setting HS transmit current level and on-chip
termination impedance.
XI/XO Input N/A External crystal. 24MHz crystal connected from XI to XO.

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DATASHEET
Table 4.5 Power and Ground Signals
NAME DIRECTION ACTIVE LEVEL DESCRIPTION
VDD3.3
(V33)
(VIO)
N/A N/A 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+
Digital, Digital I/O, and Regulators.
REG_EN
(REN) Input High On-Chip 1.8V regulator enable. Connect to ground to disable
both of the on chip (VDDA1.8 and VDD1.8) regulators. When
regulators are disabled:
External 1.8V must be supplied to VDDA1.8 and VDD1.8 pins.
When the regulators are disabled, VDDA1.8 may be connected
to VDD1.8 and a bypass capacitor (0.1μF recommended)
should be connected to each pin.
The voltage at VDD3.3 must be at least 2.64V (0.8 * 3.3V)
before voltage is applied to VDDA1.8 and VDD1.8.
VDD1.8
(V18) N/A N/A 1.8V Digital Supply. Supplied by On-Chip Regulator when
REG_EN is active. Low ESR 4.7uF minimum capacitor
requirement when using internal regulators. Do not connect
VDD1.8 to VDDA1.8 when using internal regulators. When the
regulators are disabled, VDD1.8 may be connected to VDD1.8A.
VSS
(GND) N/A N/A Common Ground.
VDDA1.8
(V18A) N/A N/A 1.8V Analog Supply. Supplied by On-Chip Regulator when
REG_EN is active. Low ESR 4.7uF minimum capacitor
requirement when using internal regulators. Do not connect
VDD1.8A to VDD1.8 when using internal regulators. When the
regulators are disabled, VDD1.8A may be connected to VDD1.8.

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DATASHEET
Chapter 5 Limiting Values
Note: In accordance with the Absolute Maximum Rating system (IEC 60134)
Table 5.1 Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum DP and DM
voltage to Ground VMAX_5V -0.3 5.5 V
Maximum VDD1.8 and
VDDA1.8 voltage to Ground VMAX_1.8V -0.3 2.5 V
Maximum 3.3V Supply
Voltage to Ground VMAX_3.3V -0.3 4.0 V
Maximum I/O Voltage to
Ground VI-0.3 4.0 V
Storage Temperature TSTG -55 150 oC
ESD PERFORMANCE
All Pins VHBM Human Body Model ±5 kV
LATCH-UP PERFORMANCE
All Pins ILTCH_UP EIA/JESD 78, Class II 150 mA
Table 5.2 Recommended Operating Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
3.3V Supply Voltage
(VDD3.3 and VDDA3.3) VDD3.3 3.0 3.3 3.6 V
Input Voltage on Digital Pins VI0.0 VDD3.3 V
Input Voltage on Analog I/O
Pins (DP, DM) VI(I/O) 0.0 VDD3.3 V
Ambient Temperature TA-40 85 oC
Table 5.3 Recommended External Clock Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
System Clock Frequency XO driven by the external
clock; and no connection at XI 24
(±100ppm) MHz
System Clock Duty Cycle XO driven by the external
clock; and no connection at XI 45 50 55 %

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DATASHEET
Chapter 6 Electrical Characteristics
Note 6.1 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA= -40oC to 85oC; unless otherwise specified.
Note 6.2 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA= -40oC to 85oC; unless otherwise specified.
Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Unconfigured Current IAVG(UCFG) Device Unconfigured 55 mA
FS Idle Current IAVG(FS) FS idle not data transfer 55 mA
FS Transmit Current IAVG(FSTX) FS current during data
transmit 60.5 mA
FS Receive Current IAVG(FSRX) FS current during data
receive 57.5 mA
HS Idle Current IAVG(HS) HS idle not data transfer 60.6 mA
HS Transmit Current IAVG(HSTX) HS current during data
transmit 62.4 mA
HS Receive Current IAVG(HSRX) HS current during data
receive 61.5 mA
Low Power Mode IDD(LPM) VBUS 15kΩpull-down and
1.5kΩpull-up resistor
currents not included.
83 uA
Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-Level Input Voltage VIL VSS 0.8 V
High-Level Input Voltage VIH 2.0 VDD3.3 V
Low-Level Output Voltage VOL IOL = 8mA 0.4 V
High-Level Output Voltage VOH IOH = -8mA VDD3.3
- 0.5 V
Input Leakage Current ILI ± 1 uA
Pin Capacitance Cpin 4 pF

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DATASHEET
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity VDIFS | V(DP) - V(DM) | 0.2 V
Differential Receiver
Common-Mode Voltage VCMFS 0.8 2.5 V
Single-Ended Receiver Low
Level Input Voltage VILSE 0.8 V
Single-Ended Receiver High
Level Input Voltage VIHSE 2.0 V
Single-Ended Receiver
Hysteresis VHYSSE 0.050 0.150 V
Output Levels
Low Level Output Voltage VFSOL Pull-up resistor on DP;
RL= 1.5kΩto VDD3.3 0.3 V
High Level Output Voltage VFSOH Pull-down resistor on DP,
DM;
RL= 15kΩto GND
2.8 3.6 V
Termination
Driver Output Impedance for
HS and FS ZHSDRV Steady state drive (See Figure 6.1)40.5 45 49.5 Ω
Input Impedance ZINP TX, RPU disabled 10 MΩ
Pull-up Resistor Impedance ZPU Bus Idle 0.900 1.24 1.575 kΩ
Pull-up Resistor Impedance ZPURX Device Receiving 1.425 2.26 3.09 kΩ
Termination Voltage For Pull-
up
Resistor On Pin DP
VTERM 3.0 3.6 V
HS FUNCTIONALITY
Input levels
HS Differential Input Sensitivity VDIHS | V(DP) - V(DM) | 100 mV
HS Data Signaling Common
Mode Voltage Range VCMHS -50 500 mV
HS Squelch Detection
Threshold (Differential) VHSSQ Squelch Threshold 100 mV
Unsquelch Threshold 150 mV
Output Levels
High Speed Low Level
Output Voltage (DP/DM
referenced to GND)
VHSOL 45Ωload -10 10 mV

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SMSC USB3290 15 Revision 1.5 (11-02-07)
DATASHEET
Note 6.3 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA= -40oC to 85oC; unless otherwise specified.
Note 6.4 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA= -40oC to 85oC; unless otherwise specified.
High Speed High Level
Output Voltage (DP/DM
referenced to GND)
VHSOH 45Ωload 360 440 mV
High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
VOLHS 45Ωload -10 10 mV
Chirp-J Output Voltage
(Differential) VCHIRPJ HS termination resistor
disabled, pull-up resistor
connected. 45Ωload.
700 1100 mV
Chirp-K Output Voltage
(Differential) VCHIRPK HS termination resistor
disabled, pull-up resistor
connected. 45Ωload.
-900 -500 mV
Leakage Current
OFF-State Leakage Current ILZ ± 1 uA
Port Capacitance
Transceiver Input Capacitance CIN Pin to GND 5 10 pF
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FS Output Driver Timing
Rise Time TFSR CL= 50pF; 10 to 90% of
|VOH - VOL|420ns
Fall Time TFFF CL= 50pF; 10 to 90% of
|VOH - VOL|420ns
Output Signal Crossover
Voltage VCRS Excluding the first
transition from IDLE state 1.3 2.0 V
Differential Rise/Fall Time
Matching FRFM Excluding the first transition from IDLE state 90 111.1 %
HS Output Driver Timing
Differential Rise Time THSR 500 ps
Differential Fall Time THSF 500 ps
Driver Waveform
Requirements Eye pattern of Template 1 in USB 2.0 specification See
Figure 6.2
High Speed Mode Timing
Receiver Waveform
Requirements Eye pattern of Template 4 in USB 2.0 specification See
Figure 6.2
Data Source Jitter and
Receiver Jitter Tolerance Eye pattern of Template 4 in USB 2.0 specification See
Figure 6.2
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

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DATASHEET
Note 6.5 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA= -40oC to 85oC; unless otherwise specified.
6.1 Driver Characteristics of Full-Speed Drivers in High-Speed
Capable Transceivers
The USB3290 uses a differential output driver to drive the USB data signal onto the USB cable.
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiveron page 17
shows the V/I characteristics for a full-speed driver which is part of a high-speed capable transceiver.
The normalized V/I curve for the driver must fall entirely inside the shaded region. The V/I region is
bounded by the minimum driver impedance above (40.5 Ohm) and the maximum driver impedance
below (49.5 Ohm). The output voltage must be within 10mV of ground when no current is flowing in
or out of the pin.
Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UTMI Timing
DATA[7:0] TPD Output Delay. Measured
from PHY output to the
rising edge of CLKOUT
25ns
RXVALID
RXACTIVE
RXERROR
LINESTATE[1:0]
TXREADY
DATA[7:0] TSU Setup Time. Measured
from PHY input to the
rising edge of CLKOUT.
5ns
TXVALID
OPMODE[1:0]
XCVRSELECT
TERMSELECT
DATA[7:0] THHold time. Measured from
the rising egde of
CLKOUT to the PHY input
signal edge.
0ns
TXVALID
OPMODE[1:0]
XCVRSELECT
TERMSELECT

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
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DATASHEET
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver
Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver
Vout (Volts) VOH
0
0
Drive High
0.698*VOH
Test Limit
Slope = 1/49.5 Ohm
Slope = 1/40.5 Ohm
0.566*VOH
-10.71 * |VOH|
-6.1 * |VOH|
Iout
(mA)
Vout (Volts) VOH
0
0
Drive Low
Iout
(mA)
22
1.09V 0.434*VOH
Test Limit
Slope = 1/40.5 Ohm
Slope = 1/49.5 Ohm
10.71 * |VOH|

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Revision 1.5 (11-02-07) 18 SMSC USB3290
DATASHEET
6.2 High-speed Signaling Eye Patterns
High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4
points have been defined (see Figure 6.3). The Universal Serial Bus Specification Rev.2.0 defines the
eye patterns in several ‘templates’. The two templates that are relevant to the PHY are shown below.
Figure 6.3 Eye Pattern Measurement Planes
USB Cable
Transceiver
Device Circuit Board
Transceiver
Hub Circuit Board
Connector
Traces Traces
A Connector B
TP1 TP2 TP3 TP4

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DATASHEET
The eye pattern in Figure 6.4 defines the transmit waveform requirements for a hub (measured at TP2
of Figure 6.3) or a device without a captive cable (measured at TP3 of Figure 6.3). The corresponding
signal levels and timings are given in table below. Time is specified as a percentage of the unit interval
(UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate.
Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-) TIME (% OF UNIT INTERVAL)
Level 1 525mV in UI following a transition,
475mV in all others N/A
Level 2 -525mV in UI following a transition,
-475mV in all others N/A
Point 1 0V 7.5% UI
Point 2 0V 92.5% UI
Point 3 300mV 37.5% UI
Point 4 300mV 62.5% UI
Point 5 -300mV 37.5% UI
Point 6 -300mV 62.5% UI
Differential
-400mV
Differential
400mV
Unit Interval 100%
Level 2
Level 1
Point 1 Point 2
Point 4Point 3
Point 6Point 5
0%
0 Volts
Differential

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DATASHEET
The eye pattern in Figure 6.5 defines the receiver sensitivity requirements for a hub (signal applied at
test point TP2 of Figure 6.3) or a device without a captive cable (signal applied at test point TP3 of
Figure 6.3). The corresponding signal levels and timings are given in the table below. Timings are
given as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480
Mbit/s transmission rate.
Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-) TIME (% OF UNIT INTERVAL)
Level 1 575mV N/A
Level 2 -575mV N/A
Point 1 0V 15% UI
Point 2 0V 85% UI
Point 3 150mV 35% UI
Point 4 150mV 65% UI
Point 5 -150mV 35% UI
Point 6 -150mV 65% UI
Point 1
0% 100%
Point 2
Level 2
Level 1
Point 3 Point 4
Point 5 Point 6
Differential
-400mV
Differential
400mV
Differential
0 Voltｓ