Sony CDX-600 - Compact Disc Changer System User manual

MICROFILM
SERVICE MANUAL
COMPACT DISC CHANGER
US Model
CDX-600/606
Canadian Model
AEP Model
UK Model
CDX-600
E Model
CDX-626
SPECIFICATIONS
CDX-600/606/626
Model Name Using Similar Mechanism CDX-505RF
CD Drive Mechanism Type MG-250C-137
Optical Pick-up Name KSS-521A/J2N
Photo: CDX-600

CDX-600/606/626
7-3. SCHEMATIC DIAGRAM – RF Section – • See page 18 forWaveforms. •See page 31 for IC Block Diagrams.
The components identified by mark !or dotted
line with mark !are critical for safety.
Replaceonly withpart numberspecified.
Lescomposants identifiés par une marque!sont
critiques pour la sécurité. Ne les remplacer que
par une piéce portant le numéro spécifié.
– 21 – – 22 –
(Page 27)

CDX-600/606/626
– 27 – – 28 –
7-6. SCHEMATIC DIAGRAM – MAIN Section (1/2) – • See page 18 forWaveforms. •See page 33 for IC Block Diagrams.
(Page 22)

CDX-600/606/626
– 29 – – 30 –
7-7. SCHEMATIC DIAGRAM – MAIN Section (2/2) – • See page 18 for Waveforms. •See page 33 for IC Block Diagrams.

– 31 – – 32 –
• IC Block Diagrams
– RF Board –
IC11 CXA1992BR
FZC
VC
TDFCT
TZC
ATSC
TEI
LPFI
TEO
VEE
EI
E
F
FE
BIAS
SL P
SL M
SL O
ISET
VCC
XRST
DATA
XLT
CLK
LOCK
SENS2
SENS1
C. OUT
VCC
DFCTO
IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4
FS1 – FS4
TG1 – TG2
TM1 – TM7
PS1 – PS4
TGH
TGL
BALH
BALL
ATSC
DFCT
TM1
TG1
FS2
IFB1 – IFB6
VCC
VEE
VCC
VEE
VEE
PD 2
I-V AMP
FOK
CC2
CC1
CB CP
RF O RF I
RFTC
PD2
PD1
PD
LD
RF M
TA O
TA M
FSET
TG2
TGU
SRCH
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
TZC
FZC FOL
FOH
MIRR
LDON LPCL
LPC
TGFL
DFCT1
CC1
1 2 3 45678 9 10
26
25
24
23
22
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
39
PD 1
I-V AMP
38
PD
AMP
37
LD
AMP
LASER
POWER
CONTROL
FOCUS BIAS
WINDOW
COMPARATOR
FOCUS ERROR
AMP
F I-V
AMP
E I-V
AMP TGFL TRACKING GAIN
WINDOW
COMPARATOR
E-F BALANCE
WINDOW
COMPARATOR
ATSC
WINDOW
COMPARATOR
TZC
COMPARATOR
TRACKING PHASE
COMPENSATION
CENTER
VOLTAGE
GENERATOR
FZC
COMPARATOR
FOCUS PHASE
COMPENSATION CHARGE UP
FSET
ISET
IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
OUTPUT DECODER TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
RF SUMMING
AMP FOCUS OK
COMPARATOR
PEAK/BOTTOM
HOLD
PEAK/BOTTOM
HOLD
DEFECT
AMP
MIRR
COMPARATOR
36 34 31 30 29 28 27
35 33 32
BAL1 – BAL4
TM6
TM2
VCC
VEE
TM5
11 12 13
TG2
TM4
VCC
VEE
TM3
FS1
VCC
VEE
TOG1 – TOG4
TM7
FS4
DFCT
+
–
+ –
IC52 BA6287F
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER DRIVER
– MAIN Board –
IC101 CXD2530Q
1 2 3456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
43
42
41
40
39
38
37
36
35
34
33
32
31
50
49
48
47
46
45
44
88
89
90
91
92
93
94
95
96
97
98
99
100
81
82
83
84
85
86
87
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SUB CODE
PROCESSOR
TIMING
LOGIC CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM DIGITAL OUT
OSC
EFM
DEMODULATOR
TES6 VDD VSS EXCK SBSO SCOR WFCK TES5 EMPH DOUT C4M FSTT XTSL MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9
LRCK
WDCK
ASYE
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
LOCK
PWMI
MDP MDS
VSS
MON
FOK
VDD
SPOD
XLON SPOB SPOC
CLKO
SPOA DATO
XLTO
SEIN
CNIN
XLAT
CLOK SENS DATA
SQCK
SQSO
TES2
CKOUT
LMUT
RMUT
VDD
VSS
NC
XRST
VSS
NC
NC
VDD
NC
TES8
XVSS
VSS
XTAI
XTAO
VSS
XVDD
TES7
NC
VDD
NC
NC
VSS

– 33 –
IC204 BA8272F-E2
IC401 TC9464FN-EL
IC301 BA6287F
12 3 45 6 7
891014 13 12 11
VCC BUS ON LINK OFF CLK OUT DATA OUT DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER DRIVER
DIGITAL FILTER CIRCUIT
ATTENUATOR OPERATIONAL CIRCUIT
DEEMPHASIS FILTER CIRCUIT
D-∆MODULATION CIRCUIT
INTERFACE
CIRCUIT
TEST
CIRCUIT OUTPUT CIRCUIT
ANALOG
FILTER
TIMING
GENERATOR
OSC
MICROCOMPUTER
INTERFACE
CIRCUIT
OUTPUT
CIRCUIT
ANALOG
FILTER
12 3 45 6 7 8 9 10
20 19 18 17 16 15 14 13
1211
21222324
LRCK BCK DATA HS
(SM)
ATT
(EMP)
SH
(BS)
LA
VDX XO XI GNDX MCK
VDD
T1
P/S
VDA
RO
GNDA
VR
GNDA
LO
GNDD
ZD
VDA

– 34 –
7-8. IC PIN FUNCTION DESCRIPTION
•MAIN BOARD IC302 CXP84124-080Q (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Function
1 LIM.SW I Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
2 BUSON I Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on
3 EJECT I Eject switch (SW303) input terminal “H” active
4 LOAD1 I Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
5 LOAD2 I Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
6 A.MUTE O Audio line muting on/off control signal output terminal “H”: muting on
7 EMPH O Emphasis mode output to the D/A converter (IC401) “L”: emphasis on
8 CH.R O Motor drive signal (save direction) output to the chucking motor drive (IC52)
“H” active *1
9 CH.F O Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“H” active *1
10 — O Not used (open)
11 ELV.R O Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
12 ELV.ON O Mechanism deck section power supply on/off control signal output “H”: power on
13 CD RST O System reset signal output to the CXA1992BR (IC11) and CXD2530Q (IC101) “L”: reset
14 CDON O D/A converter and servo section power supply on/off control signal output “H”: power on
15 to 23 — O Not used (open)
24 AUTO ON/OFF I Setting terminal for the automatic adjustment
“L”: automatic adjustment, “H”: manual adjustment (fixed at “L” in this set)
25 to 29 — O Not used (open)
30 RESET I System reset signal input from the reset signal generator (IC202) and SONY bus interface (IC204) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31 EXTAL I Main system clock input terminal (8 MHz)
32 XTAL O Main system clock output terminal (8 MHz)
33 VSS — Ground terminal
34 TX O Sub system clock output terminal Not used (open)
35 TEX I Sub system clock input terminal Not used (fixed at “L”)
36 AVSS — Ground terminal (for A/D converter)
37 AVREF I Reference voltage (+5V) input terminal (for A/D converter)
38 ATRIBT I Selection input of the custom file, D-BASS, etc.
39 MCK I Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator
position (A/D input)
40 EHS I Elevator height position detect input from the RV302 (elevator height sensor) (A/D input)
41 to 47 — O Not used (open)
48 SCK I Serial data transfer clock signal input from the SONY bus interface (IC204)
49 SI I Serial data input from the SONY bus interface (IC204)
50 SO O Serial data output to the SONY bus interface (IC204)
51 SQCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101)
52 SUBQ I Subcode Q data input from the CXD2530Q (IC101)
53 — O Not used (open)
54 — I Not used (fixed at “H”)
55 MGLK I Magazine eject operation completion detect switch (SW301) input terminal
“L”: eject completed

– 35 –
Pin No. Pin Name I/O Function
56 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
57 SENS2 I Internal status signal (sense signal) input from the CXA1992BR (IC11)
58 PWM O Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *2
59 — O Not used (open)
60 MAG.SW I Magazine in/out detect switch (SW302) input terminal “L”: magazine detected
61 BUCHECK I Battery detection signal input terminal “H”: battery on
62 W.UP I Bus on or eject switch (SW303) input terminal “H”: bus on or eject switch pushing
63 C.OUT I Track number count signal input from the CXA1992BR (IC11)
64 EEDATA I/O Two-way data bus with the EEPROM Not used (open)
65 EECLK O Serial clock signal output to the EEPROM Not used (open)
66 EEINIT I Initialize signal input for the EEPROM “H”: format Fixed at “L” in this set
67 — O Not used (open)
68 SINGLE I Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
69 FOK I Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
70 GFS I Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
71 SENS1 I Internal status signal (sense signal) input from the CXD2530Q (IC101)
72 VDD — Power supply terminal (+5V)
73 NC (VDD) — Connected to the power supply (+5V)
74 CDCLK O Serial data transfer clock signal output to the CXD2530Q (IC101)
75 CDXLT O Serial data latch pulse signal output to the CXD2530Q (IC101)
76 CDDATA O Serial data output to the CXD2530Q (IC101)
77 to 80 — O Not used (open)
*1 chucking motor (M103) control
STOP LOAD
CHUCKING SAVE BRAKE
CH.F (pin 9) “L” “H” “L” “H”
CH.R (pin 8) “L” “L” “H” “H”
Mod
e
Terminal
*2 elevator motor (M104) control
STOP ELEVATOR
UP ELEVATOR DOWN BRAKE
PWM (pin %•) “H” “L” “H” “L”
ELV.R (pin !¡) “H” “H” “L” “L”
Mod
e
Terminal