Sony CDX-828 - Compact Disc Changer System User manual

MICROFILM
SERVICE MANUAL
COMPACT DISC CHANGER
US Model
Canadian Model
AEP Model
UK Model
E Model
SPECIFICATIONS
CDX-828
Model Name Using Similar Mechanism CDX-805
CD Drive Mechanism Type MG-250C-137
Optical Pick-up Name KSS-521A/J2N

CDX-828
7-6. SCHEMATIC DIAGRAM – RF/SW Boards – • See page 39 forWaveforms. •See page 45 for IC Block Diagrams.
The components identified by mark !or dotted
line with mark !are critical for safety.
Replaceonly with partnumber specified.
Lescomposantsidentifiés par une marque!sont
critiques pour la sécurité. Ne les remplacer que
par une piéce portant le numéro spécifié.
– 27 – – 28 –
(Page 33)

CDX-828
– 33 – – 34 –
7-9. SCHEMATIC DIAGRAM – MAIN Board (1/3) – • See page 39 forWaveforms. •See page 46 for IC Block Diagrams.
(Page
28)
(Page 37)

CDX-828
– 35 – – 36 –
7-10. SCHEMATIC DIAGRAM – MAIN Board (2/3) – • See page 40 forWaveforms. •See page 47 for IC Block Diagrams.
(Page 38)
(Page 43)

CDX-828
– 37 – – 38 –
7-11. SCHEMATIC DIAGRAM – MAIN Board (3/3) – • See page 40 forWaveforms. •See page 47 for IC Block Diagrams.
(Page 34) (Page 35)

– 39 –
• Waveforms
– RF Board –
1IC11 #£ (RF O)
500 mV/DIV, 500 ns/DIV
2IC11 2(FEI)
50 mV/DIV, 1 µs/DIV
3IC11 $¶ (TEI)
200 mV/DIV, 500 µs/DIV
1.4 Vp-p
Approx.
110 mVp-p
Approx.
280 mVp-p
– MAIN Board (1/3) –
1IC101 @¶ (MDP)
2IC101 #§ (V16M)
3IC101 $ª (WDCK)
4IC101 %º (LRCK)
5IC101 %¢ (BCKO)
6.8 Vp-p
120 ns
6.6 Vp-p
11.4 µ s
6.6 Vp-p
22.7 µ s
6.6 Vp-p
472 ns
7IC101 &º (C4M)
8IC101 &¢ (WFCK)
9IC101 *ª (XTAI)
!º IC201 #¡ (EXTAL)
6IC101 ^™ (RFCK)
5.7 Vp-p
137 µ s
6.6 Vp-p
236 ns
5.5 Vp-p
137 µ s
3.3 Vp-p
59.2 ns
3.2 Vp-p
125 ns
2.5 Vp-p
7.6
µ s

– 40 –
– MAIN Board (2/3) –
!¡ IC603 4
!™ IC601 4(XTO)
!£ IC601 7(BCK)
!¢ IC601 9(LRCK)
4.7 Vp-p
59.2 ns
6.4 Vp-p
59.2 ns
7.4 Vp-p
472 ns
7.4 Vp-p
22.7 µ s
– MAIN Board (3/3) –
!∞ IC401 !ª (LRCK)
!§ IC401 !¶ (BCK)
!¶ IC401 !£ (WDCI)
!• IC401 !™ (LRCI)
!ª IC401 9(BCKI)
@¡ IC401 5(C4M)
@™ IC401 3, IC501&¶ (WFCK)
@£ IC403 1
@¢ IC501 @ª (EXTAL)
@º IC401 7(RFCK)
6.2 Vp-p
22.7 µ s
6.2 Vp-p
472 ns
7.7 Vp-p
11.4 µ s
6.6 Vp-p
22.7 µ s
6.6 Vp-p
472 ns
5.7 Vp-p
137 µ s
6.6 Vp-p
236 ns
5.5 Vp-p
137
µ s
6.6 Vp-p
11.4 µ s
3.2 Vp-p
100 ns

CDX-828
– 43 – – 44 –
7-13. SCHEMATIC DIAGRAM – DIGITAL OUT/JACK Boards –
(Page 36)

– 45 –
• IC Block Diagrams
– RF Board –
IC11 CXA1992BR
FZC
VC
TDFCT
TZC
ATSC
TEI
LPFI
TEO
VEE
EI
E
F
FE
BIAS
SL P
SL M
SL O
ISET
VCC
XRST
DATA
XLT
CLK
LOCK
SENS2
SENS1
C. OUT
VCC
DFCTO
IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4
FS1 – FS4
TG1 – TG2
TM1 – TM7
PS1 – PS4
TGH
TGL
BALH
BALL
ATSC
DFCT
TM1
TG1
FS2
IFB1 – IFB6
VCC
VEE
VCC
VEE
VEE
PD 2
I-V AMP
FOK
CC2
CC1
CB CP
RF O RF I
RFTC
PD2
PD1
PD
LD
RF M
TA O
TA M
FSET
TG2
TGU
SRCH
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
TZC
FZC FOL
FOH
MIRR
LDON LPCL
LPC
TGFL
DFCT1
CC1
1 2 3 45678 9 10
26
25
24
23
22
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
39
PD 1
I-V AMP
38
PD
AMP
37
LD
AMP
LASER
POWER
CONTROL
FOCUS BIAS
WINDOW
COMPARATOR
FOCUS ERROR
AMP
F I-V
AMP
E I-V
AMP TGFL TRACKING GAIN
WINDOW
COMPARATOR
E-F BALANCE
WINDOW
COMPARATOR
ATSC
WINDOW
COMPARATOR
TZC
COMPARATOR
TRACKING PHASE
COMPENSATION
CENTER
VOLTAGE
GENERATOR
FZC
COMPARATOR
FOCUS PHASE
COMPENSATION CHARGE UP
FSET
ISET
IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
OUTPUT DECODER TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
RF SUMMING
AMP FOCUS OK
COMPARATOR
PEAK/BOTTOM
HOLD
PEAK/BOTTOM
HOLD
DEFECT
AMP
MIRR
COMPARATOR
36 34 31 30 29 28 27
35 33 32
BAL1 – BAL4
TM6
TM2
VCC
VEE
TM5
11 12 13
TG2
TM4
VCC
VEE
TM3
FS1
VCC
VEE
TOG1 – TOG4
TM7
FS4
DFCT
+
–
+ –

– 46 –
IC52 BA6287F
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER DRIVER
– MAIN Board –
IC101 CXD2530Q
1 2 3456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
43
42
41
40
39
38
37
36
35
34
33
32
31
50
49
48
47
46
45
44
88
89
90
91
92
93
94
95
96
97
98
99
100
81
82
83
84
85
86
87
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SUB CODE
PROCESSOR
TIMING
LOGIC CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM DIGITAL OUT
OSC
EFM
DEMODULATOR
TES6 VDD VSS EXCK SBSO SCOR WFCK TES5 EMPH DOUT C4M FSTT XTSL MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9
LRCK
WDCK
ASYE
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
LOCK
PWMI
MDP MDS
VSS
MON
FOK
VDD
SPOD
XLON SPOB SPOC
CLKO
SPOA DATO
XLTO
SEIN
CNIN
XLAT
CLOK SENS DATA
SQCK
SQSO
TES2
CKOUT
LMUT
RMUT
VDD
VSS
NC
XRST
VSS
NC
NC
VDD
NC
TES8
XVSS
VSS
XTAI
XTAO
VSS
XVDD
TES7
NC
VDD
NC
NC
VSS

– 47 –
IC202 AT24C16N-10SI-TR
IC302 BA8272F-E2 IC401 CXD2522Q
DEVICE
ADDRESS
COMPARATOR
Y DEC
H.V. PUMP/TIMING
DATA RECOVERY
E
2
PROM
SERIAL MUX
START
STOP
LOGIC SERIAL
CONTROL
LOGIC
DATA WORD
ADDR/COUNTER
D
OUT
/ACK
LOGIC
1
2
3
4
5
6
7
8
X DEC
VCC
TST
SDL
SDA
A0
A1
A2
GND
COMP
LOAD
LOAD INC
R/W
EN
D
OUT
D
IN
IC301 BA6287F
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER DRIVER
12 3 45 6 7
891014 13 12 11
VCC BUS ON LINK OFF CLK OUT DATA OUT DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
VWA
ADDRESS MONITOR
WRITE
BASE
COUNTER
READ
BASE
COUNTER
CPU I/F
SELECTOR
TIMING
GEN.
DSP
I/F
DATA
LINKING
CONTROL DAC
I/F DIGITAL OUT
12 3 45 6 7 8 9 10
20
191817161514131211
21
22
23
24
25
26
27
28
29
30
31
32
33343536373839404142
43444546
56
55
54
53
52
51 50 49 48 47
57
58
59
60
61
62
63
64
XWIH
AM4
AM3
AM2
AM1
AM0
VDD
XQOK
GSCR
SCOR
NC
NC
NC
GRST
XRST
WFCK
DIN
C4M
XROI
RFCK
GTOP
BCKI
VSS
DATI LRCI
WDCI
TEST
XTAO
XTAI
BCK
DATA LRCK
DOUT
C176
A3
A2
A1
A0
VDD
A9
XRAS
XWE
D1
D0
D3
D2 XCAS XOE A8 A7 A6 A5 A4 OSCE VSS SPSL XEMP SDTO XSOE SCK SDTI XLT XRDE XWRE
DRAM
I/F

– 48 –
IC402 MSM514400D-60TS-K
IC502 KM62256DLG-7LT IC601 AK4321-VF-E2
WRITE
CLOCK
GENERATOR
DATA INPUT
BUFFER DATA OUTPUT
BUFFER
COLUMN
DECODER SENSE AMP
I/O GATE
4M BIT
MEMORY
CELL
ROW
DECODER
ADDRESS
BUFFER PRE-
DECODER
REFRESH
ADDRESS
COUNTER
BOARD
BIAS
GENERATOR
MODE
CONTROL
CLOCK
GENERATOR
1
CLOCK
GENERATOR
2
18
24
25
26
17
16
15
14
5
4
1
2
3
9
10
11
12
13
23
22
DQ1
DQ2
WE
RAS
A9
A0
A1
A2
A3
VCC
VSS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
MEMORY
MATRIX
512X512
ROW
DECODER
BUFFER
1
A14 2
3
4
5
A5
A12
A7
A6
26 A13
25 A8
24
23 A11
A9
I/O GATE
COLUMN
DECODER
BUFFER
6
A4 7
8
9
10
A0
A3
A2
A1
27
28 VCC
WE
22 OE
21 A10
BUFFER
18 I/O7
17 I/O6
16 I/O4
I/O5
19 I/O8
15
I/O BUFFER
11
12
13
I/O3
I/O1
I/O2
20 CE
14
GND
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
CTF SCF
CLOCK OSC/DIVIDER
∆Σ
MODULATOR
SERIAL INPUT
INTERFACE
8 ×
INTERPOLATOR
DE-EMPHASIS
CONTROL
8 ×
INTERPOLATOR
∆Σ
MODULATOR
CTF SCF
12 3 45 6 7 8 9 10
20 19 18 17 16 15 14 13
1211
21222324
TTL DZF VREF AVSS AVDD VCOM AOUTL AOUTR BVDD DIF1 DIF0 DEM1
CKS
DVDD
DVSS
XTO
XTI
PD
BICK
SDATA
LRCK
SMUTE
DFS
DEMO

– 49 –
7-14. IC PIN FUNCTION DESCRIPTION
•MAIN BOARD IC201 CXP84332-208Q (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Function
1 to 3 — O Not used (open)
4 CH.F O Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“L” active *1
5 CH.R O Motor drive signal (save direction) output to the chucking motor drive (IC52)
“L” active *1
6 LOAD2 I Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
7 LOAD1 I Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
8 SENS2 I Internal status signal (sense signal) input from the CXA1992BR (IC11)
9 LIM.SW I Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
10 EE.INIT I Initialize signal input for the EEPROM (IC202) “H”: format Fixed at “L” in this set
11 EE.CLK O Serial data transfer clock signal output to the EEPROM (IC202)
12 EE.DATA I/O Two-way data bus with the EEPROM (IC202)
13 to 19 — O Not used (open)
20 SINGLE I Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
21 XRST O System reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q
(IC401) “L”: reset
22 FOK I Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
23 SENS I Internal status signal (sense signal) input from the CXD2530Q (IC101)
24 GFS I Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
25 GRSRT O Reset signal output to the CXD2522Q (IC401) “L”: reset
26 XQOK O Subcode Q OK pulse signal output to the CXD2522Q (IC401) “L” active
27 SDTI I ESP status signal input from the CXD2522Q (IC401)
28 XSOE O ESP status read enable signal output to the CXD2522Q (IC401) “L” active
29 ESPXLT O ESP latch pulse signal output to the CXD2522Q (IC401) “L” active
30 RST I System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31 EXTAL I Main system clock input terminal (8 MHz)
32 XTAL O Main system clock output terminal (8 MHz)
33 VSS — Ground terminal
34 TX O Sub system clock output terminal Not used (open)
35 TEX I Sub system clock input terminal Not used (fixed at “L”)
36 AVSS — Ground terminal (for A/D converter)
37 AVREF I Reference voltage (+5V) input terminal (for A/D converter)
38 MCK I Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator
position (A/D input)
39 EHS I Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)
40 H.TEMP I High temperature sensor input terminal Not used (fixed at “L”)
41 XRDE O D-RAM read enable signal output to the CXD2522Q (IC401) “L” active
42 XWRE O D-RAM write enable signal output to the CXD2522Q (IC401) “L” active
43 A.MUTE O Audio line muting on/off control signal output terminal “H”: muting on
44 EMP O Emphasis mode output to the D/A converter (IC601) “H”: emphasis on
45 ML O Fast speed dubbing control signal output to the D/A converter (IC601) “L”: fast speed
46 GRSCOR I Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401)

– 50 –
Pin No. Pin Name I/O Function
47 D/A.RESET O Reset signal output to the D/A converter (IC601) “L”: reset
48 SCK I Serial data transfer clock signal input from the SONY bus interface (IC302)
49 SI I Serial data input from the SONY bus interface (IC302)
50 SO O Serial data output to the SONY bus interface (IC302)
51 SCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101)
52 SUBQ I Subcode Q data input from the CXD2530Q (IC101)
53 — O Not used (open)
54 C.OUT I Track number count signal input from the CXA1992BR (IC11)
55 BUS.ON I Bus on/off control signal input from the SONY bus interface (IC302) “H”: bus on
56 A/D.SW I Analog/digital select switch (SW801) input terminal “L”: digital, “H”: analog
57 MGLK I Magazine eject operation completion detect switch (SW201) input “L”: eject completed
58 ELV.F O Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *2
59 — O Not used (open)
60 MAG.SW I Magazine in/out detect switch (SW202) input “L”: magazine detected
61 BU.CHK I Battery detection signal input terminal “H”: battery on
62 W.UP I Bus on or eject switch (SW301) input terminal “H”: bus on or eject switch pushing
63 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
64 EJECT I Eject switch (SW301) input terminal “H” active
65 CD.CLK O Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401)
66 CD.XLT O Serial data latch pulse signal output to the CXD2530Q (IC101)
67 CD.DATA O Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401)
68 CD.ON O D/A converter and servo section power supply on/off control signal output “H”: power on
69 ELV.ON O Mechanism deck section power supply on/off control signal output “H”: power on
70 ELV.R O Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
71 — O Not used (open)
72 VDD — Power supply terminal (+5V)
73 NC (VDD) — Connected to the power supply (+5V)
74 BUSY I Busy monitor input from the CD text decoder (IC501) “L”: busy status
75 RESET O Reset signal output to the CD text decoder (IC501) “L”: reset
76 REQ I Data request signal input from the CD text decoder (IC501) “L” active
77 CCCLK O Command clock signal output to the CD text decoder (IC501)
78 CSO O Command data output to the CD text decoder (IC501)
79 CSI I Command data input from the CD text decoder (IC501)
80 ADJ I Automatic/manual adjustment selection terminal
“L”: manual adjustment mode, “H”: automatic adjustment mode (fixed at “H” in this set)
*1 chucking motor (M103) control
STOP LOAD
CHUCKING SAVE BRAKE
CH.F (pin 4) “H” “L” “H” “L”
CH.R (pin 5) “H” “H” “L” “L”
Mod
e
Terminal
*2 elevator motor (M104) control
STOP ELEVATOR
UP ELEVATOR DOWN BRAKE
ELV.F (pin %•) “H” “L” “H” “L”
ELV.R (pin &º) “H” “H” “L” “L”
Mod
e
Terminal

– 51 –
•MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER)
Pin No. Pin Name I/O Function
1, 2 NC O Not used (open)
3 NC I Not used (fixed at “L”)
4 REQ O Request signal output to the system controller (IC201) “L” active
5 CCLK I Serial data transfer clock signal input from the system controller (IC201)
6 CSI I Serial data input from the system controller (IC201)
7 CSO O Serial data output to the system controller (IC201)
8 SCLK O Clock signal output for subcode data reading to the CXD2530Q (IC101)
9 SSI I Subcode data input from the CXD2530Q (IC101)
10 NC O Not used (open)
11 to 18 ADD0 to ADD7 OAddress signal output to the S-RAM (IC502)
19 NC I Not used (fixed at “L”)
20 to 27 DATA0 to DATA7 I/O Two-way data bus with the S-RAM (IC502)
28 RST I System reset signal input from the system controller (IC201), SONY bus interface (IC302) and
reset signal generator (IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
29 EXTAL I System clock input terminal (10 MHz)
30 XTAL O System clock output terminal (10 MHz)
31 VSS — Ground terminal
32 to 55 NC O Not used (open)
56 BUSY O Busy signal output to the system controller (IC201) “L”: busy status
57 to 61 NC O Not used (open)
62 CE O Chip enable signal output to the S-RAM (IC502) “L” active
63 WE O Data write enable signal output to the S-RAM (IC502) “L” active
64 to 69 ADD8 to ADD13 OAddress signal output to the S-RAM (IC502)
70 VDD — Power supply terminal (+5V)
71, 72 NC O Not used (open)
73 NC I Not used (fixed at “H”)
74 ADD14 O Address signal output to the S-RAM (IC502)
75 NC O Not used (open)
76 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
77 WFCK I Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101)
78 BUCK I Backup power supply detection signal input terminal (used also to reset standby)
79, 80 NC I Not used (fixed at “L”)