Sony Vaio vgn-s36c User manual

Confidential

SERVICE MANUAL

BOARD REPAIR

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

Ver. 2 2005B

Revision History

S400

B-876-402-02

PERSONAL COMPUTER

•Design and specifications are subject to

change without notice.

Area Model Lineup

VGN-S52B/S

VGN-S62PS/S∗

VGN-S62PSY∗

VGN-S62S/S∗

VGN-S360

VGN-S360P

VGN-S350F

VGN-S350FP

VGN-S370F

VGN-S36GP/S

VGN-S36LP/S

VGN-S36SP/S

VGN-S36TP/S

VGN-S36C/B

VGN-S36C/S

VGN-S38CP/B

∗: CTO Model

Asian/Oceania/

South Africa

International

Chinese

Japanese Japanese

American

US Canadian

Latin

[MA]

– 2 –

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

Service and Inspection Precautions

1. Obey precautionary markings and instructions

Labels and stamps on the cabinet, chassis, and components identify areas

requiring special precautions. Be sure to observe these precautions, as well

as all precautions listed in the operating manual and other associated

documents.

2. Use designated parts only

The set’s components possess important safety characteristics, such as

noncombustibility and the ability to tolerate large voltages. Be sure that

replacement parts possess the same safety characteristics as the originals.

Also remember that the mark, which appears in circuit diagrams and

parts lists, denotes components that have particularly important safety

functions; be extra sure to use only the designated components.

3. Always follow the original design when

mounting parts and routing wires

The original layout includes various safety features, such as inclusion of

insulating materials (tubes and tape) and the mounting of parts above the

printer board. In addition, internal wiring has been routed and clamped so

as to keep it away from hot or high-voltage parts. When mounting parts or

routing wires, therefore, be sure to duplicate the original layout.

4. Inspect after completing service

After servicing, inspect to make sure that all screws, components, and wiring

have been returned to their original condition. Also check the area around

the repair location to ensure that repair work has caused no damage, and

confirm safety.

5. When replacing chip components...

Never reuse components. Also remember that the negative side of tantalum

capacitors is easily damaged by heat.

6. When handling flexible print boards...

• The temperature of the soldering-iron tip should be about 270°C.

• Do not apply the tip more than three times to the same pattern.

• Handle patterns with care; never apply force.

Caution: Remember that hard disk drives are easily damaged by

vibration. Always handle with care.

Caution Markings for Lithium/Ion Battery - The following or similar

texts shall be provided on battery pack of equipment or in both the

operating and the service instructions.

CAUTION: Danger of explosion if battery is incorrectly replaced.

Replace only with the same or equivalent type recommended by

the manufacturer. Discard used batteries according to the

manufacturer’s instructions.

CAUTION: The battery pack used in this device may present a fire

or chemical burn hazard if mistreated. Do not disassemble, heat

above 100°C (212°F) or incinerate.

Dispose of used battery promptly.

Keep away from children.

Information in this document is subject to change without notice.

Sony, VAIO and CLIE are trademarks or registered trademarks of

Sony. Microsoft, Windows, Windows Media, Outlook, Bookshelf

and other Microsoft products are trademarks or registered trademarks

of Microsoft Corporation in the United States and other countries.

The word Bluetooth and the Bluetooth logo are trademarks of

Bluetooth SIG, Inc. AMD, the AMD logo, other AMD product names

and combinations thereof are trademarks of Advanced Micro

Devices, Inc. Intel Inside logo, Pentium and Celeron are trademarks

or registered trademarks of Intel Corporation.Transmeta, the

Transmeta logo, Crusoe Processor, the Crusoe logo and

combinations thereof are trademarks of Transmeta Corporation in

the USA and other countries. Graffiti, HotSync, PalmModem, and

Palm OS are resistered trademarks, and the Hotsync logo and Palm

are trademarks of Palm, Inc. or its subsidiaries. (M) and Motrola

are trademarks of Motrora, Inc. Other Motrola products and services

with (R) mark like Dragomball are the trademarks of Motrola, Inc.

All other names of systems, products and services in this manual

are trademarks or registered trademarks of their respective owners.

In this manual, the (TM) or (R) mark are not specified.

– 3 –

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

– 4 –

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S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

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S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

CHAPTER 1. SEMICONDUCTOR PIN

ASSIGNMENTS

Semiconductors Index ..................................................... 1-1

Semiconductor Pin Assignments ..................................... 1-2

(to 1-53)

CHAPTER 2. POWER UP SEQUENCE/

BLOCK DIAGRAM

2-1. Power Up Sequence ......................................................... 2-1

2-2. Block Diagram ................................................................. 2-4

(to 2-4)

CHAPTER 3. DIAGRAMS

Schematic Diagrams and Printed Wired Boards Index ............ 3-1

1. CNX-251.......................................................................... 3-3

2. CNX-261.......................................................................... 3-8

3. IFX-311.......................................................................... 3-15

4. IFX-331.......................................................................... 3-28

5. LEX-61 .......................................................................... 3-33

6. MBX-109 ....................................................................... 3-38

7. SWX-172 ..................................................................... 3-100

8. SWX-173 ..................................................................... 3-105

(to 3-109)

TABLE OF CONTENTS

Section Title Page

Note: The parts location index which precedes

every schematic diagram, serves as the

electrical part list too.

History of the changes is shown as the “Revision

History”at the end of this data.

1-1

INDEX

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

CHAPTER 1.

SEMICONDUCTOR PIN ASSIGNMENTS

Semiconductors Index

TYPE PAGETYPE PAGE

015AZ8.2Z(TPL3) __________ 1-53

01ZA8.2(TPL3) ____________ 1-53

1SS388(TPL3) ____________ 1-53

2SB1462J-QR(TX).SO ______ 1-51

2SD2216J-QR(TX).SO ______ 1-51

AD1981BJSTZ-REEL _______ 1-2

ADM1032ARM-REEL _______ 1-3

AN12944A-VB _____________ 1-3

BD3532KN-E2 ____________ 1-4

BD6516F _________________ 1-4

DA82562ET ______________ 1-5

DF8A6.8FK(TE85R) ________ 1-53

EC10QS-04 _______________ 1-53

EC31QS03L-TE12L ________ 1-53

EP05Q03L-TE8L3__________ 1-53

FW82801DBMSL6DN _______ 1-5

HD64F2160BVTE10SNV ____ 1-9

HN1B01FU-TE85R _________ 1-51

HN1C05FE-B(TPLR3) ______ 1-51

HN3C61FU(TE85R) ________ 1-51

HN7G04FU-A/B(TE85R)_____ 1-51

HY5DU283222AFP-33 ______ 1-10

HYB25D128323C-3.3 _______ 1-13

ICS950819 _______________ 1-16

IRF7336D1TR _____________ 1-51

LM2724ASDX _____________ 1-17

LM2729SQX ______________ 1-19

LMV722MMX _____________ 1-21

LTC1799CS5#TR __________ 1-21

LTC3412EFE#TR __________ 1-22

LTC3728LCUH#TR-R4 ______ 1-23

M24C02-WDW6TP _________ 1-24

M93C46-WDW6T __________ 1-25

MA2S111-(K8).SO__________ 1-53

MA6S121-(TX) ____________ 1-53

MA8039-TX _______________ 1-53

MA8051-M-TX_____________ 1-53

MA8140-M-TX_____________ 1-53

MA8180-L-TX _____________ 1-53

MAX1908ETI+TG069 _______ 1-25

MAX1993ETG+TG069 ______ 1-28

MAX4374TEUB-TG069 _____ 1-31

MAX4737EUD _____________ 1-31

MB88153-111_____________ 1-33

MSQA6V1W5T2 ___________ 1-53

NTHS5404T1 _____________ 1-51

R3112N251A-TR ___________ 1-33

R3112N271A-TR ___________ 1-33

RD36SB _________________ 1-53

RG82855PMSL752 _________ 1-34

RN1104F(TPL3) ___________ 1-51

RN2911-TE85R ____________ 1-51

RN4904(TE85R) ___________ 1-51

RN5VD42AA-TL-FA________ 1-38

RSR025N03TL ____________ 1-51

S-24CS02AFT-TB-G ________ 1-39

SC338AIMSTRT___________ 1-39

SI5435DC-T1 _____________ 1-51

SI7840DP-T1 _____________ 1-51

SI7945DP-T1-E3___________ 1-52

SML-310MTT86 ___________ 1-53

SML-311BBTT86Q _________ 1-53

TYPE PAGE

SML-311DTT86____________ 1-53

SML-311YTT86 ____________ 1-53

SML-412MWT86 ___________ 1-53

SN0307009BZHK __________ 1-40

SN74AHC1G00DCKR ______ 1-45

SN74AHC1G02DCKR ______ 1-45

SN74AHC1G08DCKR ______ 1-45

SN74AHC1G86DCKR ______ 1-45

SN74AHC2G00HDCU3 _____ 1-45

SN74AHC2G04HDCU3 _____ 1-46

SN74AHC2G08HDCU3 _____ 1-46

SN74AHC2G14HDCU3 _____ 1-47

SN74CB3T3306DCUR ______ 1-47

SN74CBT3257PWR ________ 1-48

SN74CBTD3306PWR-12 ____ 1-48

SSM3J09FU(TE85L)________ 1-52

SSM3K15FS-TE85L ________ 1-52

TA75S01F ________________ 1-48

TAR5S15U (TE85R) ________ 1-49

TAR5S28U(TE85R) ________ 1-49

TAR5S45U _______________ 1-49

TC7S14FU(TE85R) ________ 1-49

TK11233CMCL-G __________ 1-50

TPC8107(TE12L) __________ 1-52

TPS2220ADBR ____________ 1-50

UDZ-TE-17-6.2B ___________ 1-53

XP4111-TXE ______________ 1-52

XP4213 __________________ 1-52

XP4501 __________________ 1-52

1-2

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(J/AM/AO)

Confidential

AD1981BJSTZ-REEL (ANALOG DEVICES)

SoundMAXRCODEC

1-3

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

ADM1032ARM-REEL (ADI)

SYSTEM TEMPERATURE MONITOR

TOP VIEW

(Not to Scale)

D+

SCLK

D–

THERM

ADM1032

GND

ALERT

SDATA

PIN FUNCTION DESCRIPTIONS

No. Mnemonic Description

Positive Supply, 3 V to 5.5 V.

2 D+ Positive Connection to Remote Temperature Sensor.

3 D– Negative Connection to Remote Temperature Sensor.

4THERM THERM is an open-drain output that can be used to turn a fan on/off or throttle a CPU clock in the event of

an overtemperature condition. Requires pull-up to V

5 GND Supply Ground Connection.

6ALERT Open-Drain Logic Output Used as Interrupt or SMBus Alert.

7 SDATA Logic Input/Output, SMBus Serial Data. Open-drain output. Requires pull-up resistor.

8 SCLK Logic Input, SMBus Serial Clock. Requires pull-up resistor.

ADM1032–SPECIFICATIONS

= T

MIN

to T

MAX

, V

= V

MIN

to V

MAX

, unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage, V

3.0 3.30 5.5 V

Average Operating Supply Current, I

170 215 µA 0.0625 Conversions/Sec Rate

5.5 10 µA Standby Mode

Undervoltage Lockout Threshold 2.35 2.55 2.8 V V

Input, Disables ADC, Rising Edge

Power-On Reset Threshold 1 2.4 V

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy ±1 ±3 °C 0 ≤T

≤100°C, V

= 3 V to 3.6 V

Resolution 1 °C

Remote Diode Sensor Accuracy ±1 °C 60°C ≤T

≤100°C, V

= 3 V to 3.6 V

±3 °C 0°C ≤T

≤120°C

Resolution 0.125 °C

Remote Sensor Source Current 230 µA High Level

13 µA Low Level

Conversion Time 35.7 142.8 ms From Stop Bit to Conversion Complete

(Both Channels) One-Shot Mode with

Averaging Switched On

5.7 22.8 ms One-Shot Mode with Averaging Off

(i.e., Conversion Rate = 32 or 64

Conversions per Second)

OPEN-DRAIN DIGITAL OUTPUTS

(THERM, ALERT)

Output Low Voltage, V

0.4 V I

OUT

= –6.0 mA

High Level Output Leakage Current, I

0.1 1 µA V

OUT

= V

DD2

SERIAL BUS TIMING

Logic Input High Voltage, V

2.1 V V

= 3 V to 5.5 V

SCLK, SDATA

Logic Input Low Voltage, V

0.8 V V

= 3 V to 5.5 V

Hysteresis 500 mV

SCLK, SDATA

SDATA Output Low Sink Current 6 mA SDATA Forced to 0.6 V

ALERT Output Low Sink Current 1 mA ALERT Forced to 0.4 V

Logic Input Current, I

, I

–1 +1 µA

Input Capacitance, SCLK, SDATA 5 pF

Clock Frequency 400 kHz

SMBus Timeout 25 64 ms Note 3

SCLK Clock Low Time, t

LOW

1.3 µs t

LOW

between 10% Points

SCLK Clock High Time, t

HIGH

0.6 µs t

HIGH

between 90% Points

Start Condition Setup Time, t

SU:STA

600 ns

Start Condition Hold Time, t

HD:STA

600 ns Time from 10% of SDATA to 90%

of SCLK

Stop Condition Setup Time, t

SU:STO

600 ns Time from 90% of SCLK to 10%

of SDATA

Data Valid to SCLK Rising Edge 100 ns Time for 10% or 90% of SDATA to

Time, t

SU:DAT

10% of SCLK

Data Hold Time, t

HD:DAT

300 ns

Bus Free Time, t

BUF

1.3 µs Between Start/Stop Condition

SCLK, SDATA Rise Time, t

300 ns

SCLK, SDATA Fall Time, t

300 ns

NOTES

See Table VI for information on other conversion rates.

Guaranteed by design, not production tested.

The SMBus timeout is a programmable feature. By default, it is not enabled. Details on how to enable it are available in the Serial Bus Interface section of this data sheet.

Specifications subject to change without notice.

FUNCTIONAL BLOCK DIAGRAM

ON-CHIP

TEMPERATURE

SENSOR

A/D

CONVERTER

BUSY RUN/STANDBY

EXTERNAL DIODE OPEN-CIRCUIT

ADDRESS POINTER

CONVERSION RATE

REMOTE TEMPERATURE

HIGH LIMIT REGISTER

CONFIGURATION

INTERRUPT

MASKING

LIMIT

COMPARATOR

REMOTE TEMPERATURE

VALUE REGISTER

LOCAL TEMPERATURE

VALUE REGISTER

GND SDATA SCLK

THERM

ALERT

D+

D– REMOTE TEMPERATURE

LOW LIMIT REGISTER

LOCAL TEMPERATURE

HIGH LIMIT REGISTER

LOCAL TEMPERATURE

LOW LIMIT REGISTER

ANALOG

MUX

ADM1032

LOCAL THERM LIMIT

EXTERNAL THERM LIMIT

DIGITAL MUX

STATUS REGISTER

SMBUS INTERFACE

REMOTE OFFSET

AN12944A-VB (PANASONIC)

2ch SPEAKER AMPLIFIER

BLOCK DIAGRAM

PIN FUNCTION DESCRIPTION

Pin No.

Pin Function

Pin No.

Pin Function

Pin name Function Pin name Function

1MUTE L Activist the Low Mute 25 FILT3 L Filter terminal 3

2MUTE H Activist the High Mute 26 FILT2 L Filter terminal 2

3BIAS30 3V Bias Output 27 FILT1 L Filter terminal 1

4EVR_VTL EVR Control Pin 28 EVROUT_L EVR Lch Output

5SPIN R SP Amp Rch Input 29 AMP I L The amplifier input for the gain adjustment

6AMPO R The amplifier output for the gain adjustment 30 GND GND

7GND GND 31 AMPO L The amplifier output for the gain adjustment

8AMP I R The amplifier input for the gain adjustment 32 SPIN_L SP Amp Lch Input

9EVROUT_R EVR Rch Output 33 DET C AGC demodulation Pin

10 FILT1 R Filter terminal 1 34 AGC MOD AGC-ON Level Control

11 FILT2 R Filter terminal 2 35 BIAS45 4.5V Bias Output

12 FILT3 R Filter terminal 3 36 VREF SP The VREG C terminal

13 FILT SW Filter ON/OFF Control 37 GNDSP L GND SP Lch

14 STB SW Standby ON/OFF Control 38 OUT_LN2 SP Amp Lch Output (-)

15 AUDIN L Rch Input 39 OUT LN1 SP Amp Lch Output (-)

16 TC The timing condenser for Precharge 40 OUT_LP2 SP Amp Lch Output (+)

17 GND GND 41 OUT LP1 SP Amp Lch Output (+)

18 VREG C The VREG C terminal 42 VCCSP L VCC SP Lch

19 VCC VCC 43 VCCSP R VCC SP Rch

20 BEEP IN Beep Signal Input 44 OUT RP1 SP Amp Rch Output (+)

21 VREF C The VREF C terminal 45 OUT_RP2 SP Amp Rch Output (+)

22 AUDIN_L Lch Input 46 OUT RN1 SP Amp Rch Output (-)

23 BEEP ADJ Beep signal level adjustment terminal 47 OUT RN2 SP Amp Rch Output (-)

24 AGC SW AGC ON/OFF Control 48 GNDSP R GND SP Rch

1-4

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

BD3532KN-E2 (ROHM)

REGULATOR IC FOR TERMINATIONS

BLOCK DIAGRAM

BD6516F (ROHM)

DUAL USB HIGH-SIDE POWER SWITCH

– TOP VIEW –

BLOCK DIAGRAM

PIN DESCRIPTIONS

PIN No. PIN NAME FUNCTION

1 PGND1 Power Ground Terminal 1

2 PGND2 Power Ground Terminal 2

3 SGND Sense Ground Terminal

4 EN Enable Input Terminal

5 N.C. No Connection Terminal

6 VTTS Termination Voltage Detection Terminal

7 N.C. No Connection Terminal

8 N.C. No Connection Terminal

9 N.C. No Connection Terminal

10 VREF Standard Voltage Output Terminal

11 VREFS Standard Voltage Detection Terminal

12 VDDQ Standard Input Voltage Terminal

13 N.C. No Connection Terminal

14 N.C. No Connection Terminal

15 N.C. No Connection Terminal

16 VCC Power Supply Terminal

17 N.C. No Connection Terminal

18 N.C. No Connection Terminal

19 VTT_IN1 Power Supply Terminal 1 for Termination

20 VTT_IN2 Power Supply Terminal 2 for Termination

21 N.C. No Connection Terminal

22 N.C. No Connection Terminal

23 N.C. No Connection Terminal

24 VTT1 Termination Output Terminal 1

25 VTT2 Termination Output Terminal 2

26 N.C. No Connection Terminal

27 N.C. No Connection Terminal

28 N.C. No Connection Terminal

PIN DESCRIPTION

PIN No. PIN NAME I/O PIN DESCRIPTION

1 CTRLA Control Input : High Input>2.5 V, Low Input<0.7 V

4 CTRLB Switch On at "High"

2 FLAGA Error Flag Output : Active-Low, Open-Drain Output

3 FLAGB "Low" at Over Current, Over Temperature Detection

8OUTA

5OUTB

6 GND - Ground

Power Supply

Input Terminal to Switch and Power Supply Input Terminal of

Internal Circuit

-VDD7

OUT

OUT Switch Output

1-5

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(J/AM/AO)

Confidential

DA82562ET (INTEL)

FAST ETHERNET PHYSICAL LAYER CHIP

– TOP VIEW –

VCC (DPS)

VCCA (APS)

VSSA (APS)

RBIAS10 (B)

RBIAS100 (B)

VSSA2 (APS)

VCCA2 (APS)

VSS (DPS)

VCCT (APS)

TOP (MLT)

TDN (MLT)

VCCT (APS)

VSS (DPS)

VCCT (APS)

RDP (MLT)

RDN (MLT)

VCCT (APS)

VSS (DPS)

VCCR (APS)

VSSR (APS)

TESTEN (I)

VSSR (APS)

VCCR (APS)

VSS (DPS) VCC (DPS)

TOUT (O)

LILED# (O)

ISOL_TI (I)

ISOL_TEX (I)

ISOL_TCK (I)

SPDLED# (O)

ACTLED# (O)

VSSP (DPS)

LAN_RXD0 (O)

LAN_RXD1 (O)

VCCP (DPS)

LAN_RXD2 (O)

VSSP (DPS)

LAN_CLK (O)

VCCP (DPS)

ADV10 (I)

LAN_RSTSYN

LAN_TXD0 (I)

LAN_TXD1 (I)

LAN_TXD2 (I)

X1 (I)

X2 (O)

VSS (DPS)

82562ET

PIN DIAGRAM

SSOP48

Rev 1.0

Top View

FW82801DBMSL6DN (INTEL)

I/O CONTROLLER HUB 4 MOBILE (ICH4-M)

1-6

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

1-7

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

1-8

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

1-9

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

BLOCK DIAGRAM

HD64F2160BVTE10SNV (HITACHI)

PROGRAMMABLE MICROCONTROLLER (FLASH-ROM TYPE)

– TOP VIEW –

1-10

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

DESCRIPTION

The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the

point-to-point applications which requires high bandwidth.

The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

2345 678910111213

DQS0

DQ4

DQ6

DQ7

DQ17

DQ19

DQS2

DQ21

DQ22

/CAS

/RAS

/CS

DQ5

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

/W/E

VDDQ

DM0

VSSQ

VDD

VDDQ

VDD

BA0

VSSQ

VSS

VSSQ

VSS

BA1

VDDQ

DQ3

VSSQ

VSS

Thermal

A10

DQ1

DQ2

VDD

VSS

VDD

A11

VDDQ

DQ0

VDD

VSS

VDD

VDDQ

DQ31

VSSQ

NC2

DQ30

DQ29

VSSQ

VSS

VSSQ

VSS

NC3

VDDQ

DQ28

VSSQ

VDD

CLK

A8/AP

VSSQ

DQ26

VDDQ

/CLK

CKE

VDDQ

DM3

DQ25

DQ24

MCL,

DSF

VREF

DQ27

DQS3

VDDQ

DQ14

DQ12

DQS1

DQ10

DQ8

DQ15

DQ13

DM1

DQ11

DQ9

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS VSS VSS VSS

141

Note :

1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.

2. Ball L9(NC2) is reserved for A12.

3. Ball M10(NC3) is reserved for BA2.

HY5DU283222AFP-33 (HYNIX)

128M (4Mx32) DDR SDRAM

– TOP VIEW –

PIN DESCRIPTION

PIN TYPE DESCRIPTION

CK, /CK Input

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

/CS Input

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

A0 ~ A11 Input

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

DM0 ~ DM3 Input

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

D Q S 0 ~ D Q S 3 I / O

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

DQ0 ~ DQ31 I/O Data input / output pin : Data Bus

VDD/VSS Supply Power supply for internal circuits and input buffers.

VDDQ/VSSQ Supply Power supply for output buffers for noise immunity.

VREF Supply Reference voltage for inputs for SSTL interface.

NC NC No connection.

FUNCTIONAL BLOCK DIAGRAM

4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM

Command

Decoder

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

DM(0~3)

Address

Buffer

A0-11

Bank

Control 1Mx32/Bank0

Column Decoder

Column Address

Counter

Sense AMP

2-bit Prefetch Unit

1Mx32 /Bank1

1Mx32 /Bank2

1Mx32 /Bank3

Mode

Row

Decoder

Input Buffer Output Buffer

Data Strobe

Transmitter

Data Strobe

Receiver

DQS(0~3)

Write Data Register

2-bit Prefetch Unit DS

DQ[0:31]

64 32

BA0,BA1

DLL

Block

CLK_DLL

CLK,

/CLK

Mode

SIMPLIFIED COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE

ADDR

A8/

AP BA Note

ExtendedModeRegisterSetH X LLLL OPcode 1,2

ModeRegisterSet H X LLLL OPcode 1,2

Device Deselect

HXXX

No Operation L H H H

Bank Active H X L L H H RA V 1

Read

H X LHLHCA

Read with Autoprecharge H1,3

Write

HXLHLLCA

Write with Autoprecharge H1,4

Precharge All Banks

HXLLHLX

HX1,5

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

AutoRefresh H HLLLH X 1

Self Refresh

EntryH L LLLH

Exit L H

HXXX

LHHH

Precharge Power

Down Mode

Entry H L

HXXX

LHHH 1

Exit L H

HXXX 1

LHHH 1

Active Power

Down Mode

Entry H L

HXXX

LVVV 1

Exit L H X 1

Note :

1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

WRITE MASK TRUTH TABLE

Function CKEn-1 CKEn /CS, /RAS,

/CAS, /WE DM(0~3) ADDR A8/

AP BA Note

Data Write H X X L X 1,2

Data-In Mask H X X H X 1,2

Note :

1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data.

2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23;

DM3 corresponds to the data on DQ24-Q31.

1-11

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

OPERATION COMMAND TRUTH TABLE - I

Current

State /CS /RAS /CAS /WE Address Command Action

IDLE

HXXX X DSEL NOP or power down

LHHH X NOP NOP or power down

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

L L H H BA, RA ACT Row Activation

L L H L BA, AP PRE/PALL NOP

LLLH X AREF/SREF Auto Refresh or Self Refresh

L L L L OPCODE MRS Mode Register Set

ROW

ACTIVE

HXXX X DSEL NOP

LHHH X NOP NOP

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP Begin read : optional AP

L H L L BA, CA, AP WRITE/WRITEAP Begin write : optional AP

LLHHBA,RA ACT ILLEGAL

LLHL BA,AP PRE/PALL Precharge

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

READ

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST Terminate burst

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

L L H L BA, AP PRE/PALL Term burst, precharge

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

WRITE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP

L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP

OPERATION COMMAND TRUTH TABLE - II

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

LLHHBA,RA ACT ILLEGAL

L L H L BA, AP PRE/PALL Term burst, precharge

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

READ

WITH

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

4,10

LLHL BA,AP PRE/PALL ILLEGAL

4,10

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

WRITE

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

4,10

LLHL BA,AP PRE/PALL ILLEGAL

4,10

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

PRE-

CHARGE

H X X X X DSEL NOP-Enter IDLE after tRP

L H H H X NOP NOP-Enter IDLE after tRP

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

4,10

LLHHBA,RA ACT ILLEGAL

4,10

L L H L BA, AP PRE/PALL NOP-Enter IDLE after tRP

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

OPERATION COMMAND TRUTH TABLE - III

Current

State /CS /RAS /CAS /WE Address Command Action

ROW

ACTIVATING

H X X X X DSEL NOP - Enter ROW ACT after tRCD

L H H H X NOP NOP - Enter ROW ACT after tRCD

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

4,10

LLHHBA,RA ACT ILLEGAL

4,9,10

LLHL BA,AP PRE/PALL ILLEGAL

4,10

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

WRITE

RECOVERING

H X X X X DSEL NOP - Enter ROW ACT after tWR

L H H H X NOP NOP - Enter ROW ACT after tWR

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

4,10

LLHL BA,AP PRE/PALL ILLEGAL

4,11

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

WRITE

RECOVERING

WITH

AUTOPRE-

CHARGE

H X X X X DSEL NOP - Enter precharge after tDPL

L H H H X NOP NOP - Enter precharge after tDPL

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

4,8,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

4,10

LLHHBA,RA ACT ILLEGAL

4,10

LLHL BA,AP PRE/PALL ILLEGAL

4,11

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

REFRESHING

H X X X X DSEL NOP - Enter IDLE after tRC

L H H H X NOP NOP - Enter IDLE after tRC

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

OPERATION COMMAND TRUTH TABLE - IV

Note :

1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,

BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.

2. All entries assume that CKE was active(high level) during the preceding clock cycle.

3. If both banks are idle and CKE is inactive(low level), then in power down mode.

4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of

that bank.

5. If both banks are idle and CKE is inactive(low level), then self refresh mode.

6. Illegal if tRCD is not met.

7. Illegal if tRAS is not met.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Illegal if tRRD is not met.

10. Illegal for single bank, but legal for other banks in multi-bank devices.

11. Illegal for all banks.

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

LLHL BA,AP PRE/PALL ILLEGAL

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

MODE

ACCESSING

H X X X X DSEL NOP - Enter IDLE after tMRD

L H H H X NOP NOP - Enter IDLE after tMRD

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA,RA ACT ILLEGAL

LLHL BA,AP PRE/PALL ILLEGAL

LLLH X AREF/SREF ILLEGAL

LLLLOPCODE MRS ILLEGAL

1-12

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

CKE FUNCTION TRUTH TABLE

Note :

When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.

1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.

2. All command can be stored after 2 clocks from low to high transition of CKE.

3. Illegal if CK is suspended or stopped during the power down mode.

4. Self refresh can be entered only from the all banks idle state.

5. Disabling CK may cause malfunction of any bank which is in active state.

Current

State

CKEn-

1CKEn /CS /RAS /CAS /WE /ADD Action

SELF

REFRESH

H XXXXXX INVALID

L HHXXXXExit self refresh, enter idle after tSREX

L H L H H H X Exit self refresh, enter idle after tSREX

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L HLLXXX ILLEGAL

L LXXXXX NOP,continueselfrefresh

POWER

DOWN

H XXXXXX INVALID

L HHXXXX Exitpower down, enter idle

L H L H H H X Exit power down, enter idle

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L HLLXXX ILLEGAL

L LXXXXXNOP,continue power down mode

ALL BANKS

IDLE

HHXXXXXSeeoperationcommand truth table

H L L L L H X Enter self refresh

H L H X X X X Exit power down

H L L H H H X Exit power down

H L L H H L X ILLEGAL

H L L H L X X ILLEGAL

H L L L H X X ILLEGAL

HLLLLLX ILLEGAL

L LXXXXX NOP

ANY STATE

OTHER

THAN

ABOVE

HHXXXXXSeeoperationcommand truth table

H LXXXXX ILLEGAL

L HXXXXX INVALID

L LXXXXX INVALID

DC CHARACTERISTICS I

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :

1. V

= 0 to 3.6V, All other pins are not tested under V

=0V. 2. D

OUT

is disabled, V

OUT

=0 to 2.7V

Parameter Symbol Min Max Unit Note

Input Leakage Current I

-2 2 uA 1

Output Leakage Current I

-5 5 uA 2

Output High Voltage V

+ 0.76 - V I

= -15.2mA

Output Low Voltage V

-V

- 0.76 V I

= +15.2mA

DC CHARACTERISTICS II

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :

1. I

DD1, IDD4

and I

DD5

depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of t

RFC

(Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Parameter Sym

bol Test Condition

Speed

Unit

Note

222 25 28 33 36

Operating Current I

DD0

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min);

DQ,DM and DQS inputs changing

twice per clock cycle; address and

control inputs changing once per

clock cycle

230 210 190 180 170 160 mA 1

Operating Current I

DD1

B u r s t l e n g t h = 2 , O n e b a n k a c t i v e

(min), I

=0mA 250 230 210 200 190 180 mA 1

Precharge Standby

Current in Power Down

Mode

DD2P

CKE dV

(max), t

=min 45 40 35 30 25 25 mA

Precharge Standby

Current in Non Power

Down Mode

DD2N

CKE tV

(min), /CS tV

(min),

= min, Input signals are

changed one time during 2clks

140 130 120 110 100 90 mA

Active Standby Cur-

rent in Power Down

Mode

DD3P

CKE dV

(max), t

=min 50 45 40 35 30 30 mA

Active Standby Cur-

rent in Non Power

Down Mode

DD3N

CKE tV

(min), /CS tV

(min),

=min, Input signals are

changed one time during 2clks

190 170 150 130 115 110 mA

Burst Mode Operating

Current I

DD4

(min), I

= 0 m A

All banks active 750 700 650 590 500 450 mA 1

Auto Refresh Current I

DD5

RFC

( m i n ) ,

All banks active 400 400 350 350 300 300 mA 1,2

Self Refresh Current I

DD6

CKE d0.2V 333333mA

Operating Current -

Four Bank Operation I

DD7

Four bank interleaving with BL=4,

Refer to the following page for

detailed test condition

1100 1000 900 800 700 600 mA

AC CHARACTERISTICS - I

(AC operating conditions unless otherwise noted)

Parameter Symbol

222 25

Unit Note

Min Max Min Max Min Max

Row Cycle Time t

RC 23 - 21 - 18 -

Auto Refresh Row Cycle Time t

RFC 26 - 24 - 21 -

Row Active Time t

RAS 16 120K 14 120K 12 120K

Row Address to Column Address Delay for Read t

RCDRD 7-7- 6 -

Row Address to Column Address Delay for Write t

RCDWR 4-3- 3 -

Row Active to Row Active Delay t

RRD 4-4- 4 -

Column Address to Column Address Delay t

CCD 2-2- 1 -

Row Precharge Time t

RP 7-7- 6 -

Write Recovery Time t

WR 4-4- 3 -

Last Data-In to Read Command t

DRL 2-2- 2 -

Auto Precharge Write Recovery + Precharge Time t

DAL 11 - 11 - 9 -

System Clock Cycle Time

CL=5

262.262.56

CL=4

---- - -

Clock High Level Width t

CH 0.45 0.55 0.45 0.55 0.45 0.55

Clock Low Level Width t

CL 0.45 0.55 0.45 0.55 0.45 0.55

Data-Out edge to Clock edge Skew t

AC -0.45 0.45 -0.45 0.45 -0.6 0.6

DQS-Out edge to Clock edge Skew t

DQSCK -0.45 0.45 -0.45 0.45 -0.6 0.6

DQS-Out edge to Data-Out edge Skew t

DQSQ - 0.25 - 0.35 - 0.35

Data-Out hold time from DQS t

QH tHPmin

-tQHS -tHPmin

-tQHS -

1,6

Clock Half Period t

HP tCH/L

min -tCH/L

min -

1,5

Data Hold Skew Factor t

QHS - 0.25 - 0.35 - 0.35

Input Setup Time t

IS 0.6 - 0.75 - 0.75 -

Input Hold Time t

IH 0.6 - 0.75 - 0.75 -

Write DQS High Level Width t

DQSH 0.45 0.55 0.4 0.6 0.4 0.6

Write DQS Low Level Width t

DQSL 0.45 0.55 0.4 0.6 0.4 0.6

Clock to First Rising edge of DQS-In t

DQSS 0.85 1.15 0.85 1.15 0.85 1.15

Data-In Setup Time to DQS-In (DQ & DM) t

DS 0.35 - 0.35 - 0.35 -

Data-In Hold Time to DQS-In (DQ & DM) t

DH 0.35 - 0.35 - 0.35 -

Read DQS Preamble Time t

RPRE 0.9 1.1 0.9 1.1 0.9 1.1

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).

tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and

output pattern effects, and p-channel to n-channel variation of the output drivers.

7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic.

Read DQS Postamble Time t

RPST 0.4 0.6 0.4 0.6 0.4 0.6

Write DQS Preamble Setup Time t

WPRES 0-0- 0 -

Write DQS Preamble Hold Time t

WPREH 0.35 - 0.35 - 0.35 -

Write DQS Postamble Time t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

Mode Register Set Delay t

MRD 2-2- 2 -

Exit Self Refresh to Any Execute Command t

XSC 200 - 200 - 200 -

Power Down Exit Time t

PDEX 2tCK

+ tIS -2tCK

+ tIS -

Average Periodic Refresh Interval t

REFI - 7.8 - 7.8 - 7.8

Parameter Symbol

222 25

Unit Note

Min Max Min Max Min Max

1-13

VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/

S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F

(J/AM/AO)

Confidential

AC CHARACTERISTICS - I (continue)

Parameter Symbol

28 33 36

Unit Note

Min Max Min Max Min Max

Row Cycle Time t

RC 16 - 14 - 14 -

Auto Refresh Row Cycle Time t

RFC 17 - 17 - 16 -

Row Active Time t

RAS 10 120K 9 120K 9 120K

Row Address to Column Address Delay for Read t

RCDRD 5- 5 -5 -

Row Address to Column Address Delay for Write t

RCDWR 2- 2 -2-

Row Active to Row Active Delay t

RRD 4- 3 -3 -

Column Address to Column Address Delay t

CCD 1- 1 -1 -

Row Precharge Time t

RP 5- 5 -5 -

Write Recovery Time t

WR 3- 3 -3 -

Last Data-In to Read Command t

DRL 2- 2 -2 -

Auto Precharge Write Recovery + Precharge Time t

DAL 8- 8 -8 -

System Clock Cycle Time

CL=5

2.86----

CL=4

--3.3103.610

CL=3

--4.5104.510

Clock High Level Width t

CH 0.45 0.55 0.45 0.55 0.45 0.55

Clock Low Level Width t

CL 0.45 0.55 0.45 0.55 0.45 0.55

Data-Out edge to Clock edge Skew t

AC -0.6 0.6 -0.6 0.6 -0.6 0.6

DQS-Out edge to Clock edge Skew t

DQSCK -0.6 0.6 -0.6 0.6 -0.6 0.6

DQS-Out edge to Data-Out edge Skew t

DQSQ - 0.35 - 0.35 - 0.4

Data-Out hold time from DQS t

QH tHPmin

-tQHS -tHPmin

-tQHS -

1,6

Clock Half Period t

HP tCH/L

min -tCH/L

min -

1,5

Data Hold Skew Factor t

QHS - 0.35 - 0.35 - 0.4

Input Setup Time t

IS 0.75 - 0.75 - 0.75 -

Input Hold Time t

IH 0.75 - 0.75 - 0.75 -

Write DQS High Level Width t

DQSH 0.4 0.6 0.4 0.6 0.4 0.6

Write DQS Low Level Width t

DQSL 0.4 0.6 0.4 0.6 0.4 0.6

Clock to First Rising edge of DQS-In t

DQSS 0.85 1.15 0.85 1.15 0.85 1.15

Data-In Setup Time to DQS-In (DQ & DM) t

DS 0.35 - 0.35 - 0.4 -