
4-1
SECTION 4
CIRCUIT DESCRIPTIONS
1. Serial Digital Signal Input Block
(HD SDI Module :HK-102)
The HD SDI signal input from the digital input terminal is
input to the HD SDI module (HK-102). The HD SDI module
(HK-102) is initialized by the RESET signal when the power
is turned on, and its mode is set by SYIF0 to SYIF7, SYSTA
0, 1, STRB, and SYCS.
The serial data signal is converted to the 10-bit parallel data
by the S/Pconverter via the auto equalizer circuit. The 10-bit
parallel data is output from CN3 and CN4 and input to IC102
(HD SDI signal processing).
2. HD SDI Signal Processing Block
IC102 is a programmable logic device. Data is loaded from
the IC101 ROM and determines the IC102 logic. IC102 is
input with 10-bit Y data, 10-bit C data, HD, VD, FRAME
signal, and 74.25 MHz CLK from the HD SDI module (HK-
102) (two in the case of BKM-42HD).When pin &ª of IC102
is “High”, INPUT 1 is selected. When “Low”, INPUT2
(BKM-42HD only) is selected.
The H SYNC and V SYNC of the monitor sync signal are
made by the HD, VD, FRAME signal, and CLK signal. The
SYNC phase can be changed by 16 stages by 4 bits of the
control signals P0 to P3 (pins ^§, ^•, ^ª, and &¡ of IC102) at
the maintenance menu. (P0:LSB, P3:MSB).
The Ydata and C data are latched by CLK to become the Y
data, PB data, and PR data. They are then adjusted to the
same delay time and output.
The V blanking period is counted from theVD signal to de-
termine the number of effective scanning lines 1080 or 1035.
D5 (RED LED) lights when the CRC ERROR is generated.
3. D.A Conversion, LPF Circuit Block
The Y data output from IC102 is converted to the analog
signal by the 74.25 MHz CLK at the D/A converter IC
(IC150). Likewise, the PB and PR data are converted to ana-
log signals by the 37.125 MHz CLK obtained by frequency-
dividingthe74.25 MHz CLK at theD/AconverterIC(IC501).
The Ysignal output from the D/A converter is band-limited
by the LPF (FL101), and input to the gain control IC (IC201)
via the amplification circuit (Q114, Q115).
Similarly, the PB, PR signals are band-limited by the LPF
(FL102 and FL103), and input to the gain control ICs (IC202,
IC203) via the amplification circuit (Q120, Q121:PB signal,
Q125, Q126:PR signal).
4. Analog Signal Block
The analog signals input from the analog input terminal are
turned ON by the “YPBPR” signal input to Q405 from pin
7of the IC1, output to the buffer, and are input to the gain
control ICs (IC201, IC202, IC203).
The digital and analogY, PB, and PR signals are adjusted for
their amplitudes byY LEVEL, PB LEVEL, and PR LEVEL
control signals respectively and output.
ThesesignalsareturnedONbythe“OE”signalinputtoQ117
frompin9of IC1, and output to the buffer, then to the mother
board.
5. Control Block
The CPU (IC1) performs serial communication with the sys-
tem controller of the main unit by the three signals MISO,
MOSI,andSCLK,andoutputscontrolsignalssuchasswitch-
ing signals according to the instructions of the system con-
troller of the main unit. Some control signals are output from
the extension board (IC13, IC14). The CPU reads the
adjustment data of the EEPROM (IC2) and outputs adjust-
ment voltage from the D/A converter IC (IC12). The CPU
also sends the fan stop signal and information on differentia-
tion between 1080 and 1035 to the system controller of the
main unit.
6. Power Supply Block
The HD SDI module (HK-102) requires 5V, 3.3V, 1.2V,
–2V, and –5V input power. These voltages are supplied by
the switching regulator circuit. The module uses two switch-
ing regulator control ICs (IC30, IC31) to output 3.3V and
1.2V, –2V respectively.
The oscillation frequency of this control IC is determined by
the resistor connected to pin 2and the capacitor connected
to pin 1. The voltage obtained by resistance-diving the ref-
erence voltage 2.5V made by IC32 and IC33 is input to pins
4and !¢, compared with the respective output voltage, and
pulse width-controlled to stabilize the output voltage.
The square wave output from pins 7and !º is amplified by
Q13 to Q16, Q23 to Q26, Q28 to Q31, and output by Q17
and Q18, and Q27, Q37, and Q32.
It is rectified by D20, D26, D29, D27, and D28, and inte-
grated by C59, C82, and C85 to generate the direct voltage.
The D5V power is used for 5V, while –5V is supplied from
the 3-pin regulator IC (IC21).