SST SST65P542R User manual

©2003 Silicon Storage Technology, Inc.
S74004-00-000 4/03
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SoftPartition is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Programming User’s Manual
Remote Controller
SST65P542R

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SST65P542R
Programming Reference Manual
©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03
TABLE OF CONTENTS
1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.0 MCU CORE AND INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Registers and Control Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.5 Processor Status Word (PSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.1 Inherent (INH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.2 Immediate (IMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.3 Direct (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.4 Extended (EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.5 Indexed, No Offset (IX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.6 Indexed, 8-bit Offset (IX1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.7 Indexed, 16-bit Offset (IX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.8 Relative (REL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.9 Bit Set/Clear (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.10 Bit test and branch (BTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.0 I/O REGISTERS DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.0 INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.0 RESETS AND CLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.0 POWER-DOWN MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2 IDLE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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10.0 THE CORE TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.1 Computer Operating Properly Watchdog Timer Control Register (CWTC) . . . . . . . . . . . . . . . . . . . . . 26
10.2 Timer Control and Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.1 Core Timer Overflow (CTOF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.2 Real-Time Interrupt Flag (RTIF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.3 Timer Overflow Enable (TOFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.4 Real-Time Interrupt Enable (RTIE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.5 Timer Overflow Flag Clear (TOFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.6 Real-Time Interrupt Flag Clear (RTFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2.7 Real-Time Interrupt Rate Select (RT1-RT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.3 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.4 COP Watchdog Timer (CWT) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.5 Timer During IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.0 CARRIER MODULATOR TRANSMITTER (CMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1 Carrier Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1.1 Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . . . . . 30
11.2 Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.1 Time mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.2.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.2.4 End Of Cycle (EOC) Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.2.5 Modulator Period Data Register (MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.0 PROGRAMMING FLOW DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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SST65P542R
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1.0 INTRODUCTION
The SST65P542R is a member of SST’s 8-bit, application-specific microcontroller family targeting IR remote con-
troller applications.
The SST65P542R microcontroller provides high-functionality to infrared remote controller products. The device
offers flexibility to store different remote control configurations for controlling multiple appliances. The configura-
tions are either programmed at the factory during the manufacturing process or updated through a web download
procedure using the serial interface.
Using the SuperFlash nonvolatile memory technology, the SST65P542R enhances the functionality of the conven-
tional universal remote controller devices by integrating multiple functions of a remote controller system in a single
chip solution. The built-in LED I/O ports can directly drive LED indicators. The IR transmitter port drives signals to
the infrared transmitter, which, in turn, remotely controls appliances.
The SoftPartition flash memory architecture allows seamless partition of the program code, protocol tables, and
user data in the small granularity of 128 Byte sectors. The small sector size and fast Erase/Write time greatly
increase the time and power efficiency when altering the contents of the flash memory.
The embedded controller is designed and manufactured using SST’s patented and proprietary SuperFlash EEPROM
technology.
SST’s highly reliable SuperFlash technology provides significant advantages over conventional flash memory tech-
nology. These advantages translate into significant overall cost savings and reliability benefits for customers.
PRODUCT FEATURES
• 8-bit MCU Core
– Enhanced 6502 Microprocessor Megacell
• 4 MHz Typical Oscillator Clock Frequency
• 8 MHz maximum clock frequency
• 16 KByte of user programmable flash memory
• 352 Bytes SRAM
• IR Input Pin for Learning Mode
• Power-down Modes
• Carrier Modulator Transmitter
– Supports Baseband, Pulse Length Modulator (PLM), and Frequency Shift Keying (FSK)
• Core Timer / Counter
– 14-stage multifunctional ripple counter
– Includes timer overflow, POR, RTI, and CWT
• General Registers:
– Accumulator (8-bit)
– Index Register (8-bit)
• Control registers:
– Program Counter (16-bit)
– Stack Pointer (16-bit / 6 addressable bits)
– Condition code register (8-bit)
• Addressing modes supported:
1. Immediate 3. Extended 5. Indexed, no offset 7. Indexed, 16-bit offset 9. Bit test and branch
2. Direct 4. Relative 6. Indexed, 8-bit offset 8. Bit set/clear 10. Inherent
• Data types supported:
1. Bit data (manipulation instructions)
2. Byte data

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2.0 BLOCK DIAGRAM
IRQ#
SuperFlash
EEPROM
16K x8
Interrupt
Control
MCU Core
RAM
352K x8
Port A
Port B
Timer/Counter Interrupt
IRO Carrier Modulator
Transmitter
Real-Time
Counter
Core Timer
/ Counter
4004 B2.5
COP Watchdog
Timer
Port C
FUNCTIONAL BLOCK DIAGRAM

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3.0 PIN ASSIGNMENTS
FIGURE 3-1: PIN ASSIGNMENTS FOR 28-PIN SOIC
TABLE 3-1: PIN DESCRIPTIONS
Pins Symbol Type1
1. I = Input
O = Output
Name and Functions
16-9 PA[7:0] I/O1Port A: The state of any pin in Port A is software programmable and every line is configured as
an input during any external reset.
8-1 PB[7:0] I/O with
internal
pull-ups
Port B: The state of any pin in Port B is software programmable and every line is configured as
an input during any external reset. Each I/O line contains a programmable interrupt/pull-up for
keyscan. PB[7] is used as a serial interface data line when the serial interface is enabled.
20-17 PC[3:0] I/O Port C: Every pin in Port C is a high-current pin and its state is software programmable. All lines
are configured as inputs during any external reset.
23 IRO O IRO: Suitable for driving IR LED biasing logic, the IRO pin is the high-current source and sink
output of the carrier modulator transmitter subsystem. Default state is low after any external
reset.
21 LPRST# I Low-Power Reset: An active-low pin, LPRST# function sets MCU to low-power reset mode.
The MCU, once in low-power reset mode, is held in reset with all processor clocks and crystal
oscillator halted. An internal Schmitt trigger is included in the LPRST# pin to improve noise
immunity.
24 RESET# I Reset: By setting the RESET# pin low the MCU is reset to a default state. An internal Schmitt
trigger is included in the RESET# pin to improve noise immunity.
28 OSC1 I Oscillator 1,2: These 2 pins interface with external oscillator circuits.
A crystal resonator, a ceramic resonator, or an external clock signal can be used.
27 OSC2 O
25 IRQ# I Interrupt Request: The IRQ# is negative edge-sensitive triggered. An internal Schmitt trigger
is included in the IRQ# pin to improve noise immunity.
26 VDD IPower Supply: Supply Voltage
22 VSS IGround: Circuit ground. (0V reference)
T3-1.5 4004
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA 0
PA 1
PA 2
PA 3
PA 4
PA 5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OSC1
OSC2
VDD
IRQ#
RESET#
IRO
VSS
LPRST#
PC3
PC2
PC1
PC0
PA 7
PA 6
28-pin SOIC
4004 F10.1

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4.0 MEMORY ORGANIZATION
The SST65P542R has a total of 64 KByte of addressable memory. A memory map is shown in Figure 4-1. The
memory consists of 32 Bytes of I/O registers, 352 Bytes of SRAM, 16 KByte of user flash memory, and 128 Bytes
of user vectors.
FIGURE 4-1: MEMORY MAP
FF7FH
FF80H
BFFFH
C000H
Flash Memory
(128 sectors)
127 Sectors
(128 Bytes per sector)
User
Memory
0000H
001FH
0020H
017FH
0180H
FFFFH
4004 F11.3
I/O
Registers
352 Bytes
SRAM
User
Vector
16,256
Bytes
0180H
BFFFH
Reserved
Reserved
Reserved
3FF0H
FF80H
FFF4H
FFFFH
CWT
Reset
Flash Memory
Read Protection
Reset and
Interrupt
Vectors

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5.0 MCU CORE AND INSTRUCTION SET
This section provides a description of the MCU core registers, the instruction set and the addressing modes.
5.1 Registers and Control Bit Assignments
The MCU contains five registers, as shown in the programming model of Figure 5-1. The interrupt stacking order is
shown in Figure 5-2.
FIGURE 5-1: PROGRAMMING MODEL
Unused
Unused
Unused
Half Carry
Interrupt Disable
Negative
Zero
Carry
4004 F01.4
PCL PCH
SP
0 0 0 0 0 0 0 0 1 1
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
PSW REGISTER 111H I NZC

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FIGURE 5-2: STACKING ORDER
Stacking decreases memory address and unstacking (Return) increases memory address.
5.1.1 Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of an arithmetic calculation
or data manipulations.
5.1.2 Index Register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective
address. The index register may also be used as a temporary storage area.
5.1.3 Program Counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
5.1.4 Stack Pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location 00FFH. The stack pointer
is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When
accessing memory, the 8 most significant bits are permanently set to 00H. These eight bits are appended to the
lower 8 significant register bits to produce an address within the range of 00C0H to 00FFH. Subroutines and inter-
rupts may use up to 256 (decimal) locations. If 64 locations are exceeded, i.e. if stack pointer is pointing to 00C0H
and stacking operation carried out, the stack pointer wraps around to 00FFH and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
4004 F02.3
Unstacking increasing address
Stacking decreasing address
PSW
ACCUMULATOR (A)
INDEX REGISTER (X)
PCH
PCL

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5.1.5 Processor Status Word (PSW)
The PSW is a 5-bit register. These bits can be individually tested by a program, and specific actions can be taken
as a result of their state. Each bit is explained in the following paragraphs.
5.1.5.1 Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry has occurred between bits 3 and 4 of the
accumulator during an ADD or ADC operation.
5.1.5.2 Interrupt (I)
When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is
latched and remains pending until the interrupt bit is cleared. After any reset, the interrupt mask is set and can be
cleared by software instruction (CLI).
5.1.5.3 Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative.
5.1.5.4 Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.
5.1.5.5 Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
5.2 Addressing Modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The
various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling
tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instruc-
tions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute
(extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in
most applications.
Extended addressing permits jump instructions to reach all memory locations. The term ‘effective address’ (EA) is
used in describing the various addressing modes. The effective address is defined as the address from which the
argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below.
Parentheses are used to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the
contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon
indicates concatenation of two bytes.
5.2.1 Inherent (INH)
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no
other arguments are included in this mode. These instructions are one byte long.
5.2.2 Immediate (IMM)
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode.
EA = PC+1; PC ←PC+2

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5.2.3 Direct (DIR)
In the direct addressing mode, the effective address of the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single
two-byte instruction.
EA = (PC+1); PC ←PC+2
Address bus high byte ←0, Address bus low byte ←(PC+1)
5.2.4 Extended (EXT)
In the extended addressing mode, the effective address of the argument is contained in the two bytes following the
opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in mem-
ory with a single three-byte instruction.
EA = (PC+1):(PC+2); PC ←PC+3
Address bus high byte ←(PC+1); Address bus low byte ←(PC+2)
5.2.5 Indexed, No Offset (IX)
In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index reg-
ister. This addressing mode can access the first 256 memory locations. These instructions are only one byte long.
This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or
I/O location.
EA = (X); PC ←PC+1
Address bus high byte ←0; Address bus low byte ←(X)
5.2.6 Indexed, 8-bit Offset (IX1)
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the
lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table.
EA = (X)+(PC+1); PC ←PC+2
Address bus high byte ←K; Address bus low byte ←(X)+(PC+1)
where K = the carry from the addition of (X) and (PC+1)
5.2.7 Indexed, 16-bit Offset (IX2)
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This address mode can be used in a manner simi-
lar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with
direct and extended addressing, the assembler determines the shortest form of indexed addressing.
EA = (X)+[(PC+1):(PC+2)]; PC ←PC+3
Address bus high byte ←(PC+1)+K; Address bus low byte ←(X)+(PC+2)
where K = the carry from the addition of (X) and (PC+2)

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5.2.8 Relative (REL)
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit
signed byte (the offset) following the opcode is sign-extended and added to the PC if, and only if, the branch condi-
tions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to
+129 from the opcode address. The programmer need not calculate the offset when using the assembler, since it
calculates the proper offset and checks to see that it is within the span of the branch.
EA = PC+2+(PC+1); PC ←EA if branch taken;
otherwise PC ←PC+2
5.2.9 Bit Set/Clear (BSC)
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the
opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the
first 256 locations of memory can be selectively set or cleared with a single two-byte instruction.
EA = (PC+1); PC ←PC+2
Address bus high byte ←0; Address bus low byte ←(PC+1)
5.2.10 Bit test and branch (BTB)
The bit test and branch addressing mode is a combination of direct addressing and relative addressing mode. The
bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in
the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte is sign-
extended and added to the PC if the specified bit is set or cleared in the specified memory location. This single
three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 loca-
tions of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC ←PC+2
Address bus high byte →0; Address bus low byte →(PC+1)
EA2 = PC+3+(PC+2); PC ←EA2 if branch taken;
otherwise PC ←PC+3

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5.3 Instruction Set
Table 5-1 summarizes the MCU instruction set. A description of the instructions and an explanation of abbrevia-
tions follows the table on page 18.
TABLE 5-1: MCU INSTRUCTION TABLE (1 OF 5)
Mnemonic Explanation Address Mode (n) Hex Opcode Number of Machine Cycles Number of Bytes Flags Affected
ADC Add memory to accumulator
with carry A+M+C →AIMM
DIR
EXT
IX
IX1
IX2
A9
B9
C9
F9
E9
D9
2
3
4
3
4
5
2
2
3
1
2
3
H – N Z C
ADD Add memory to accumulator
A+M →AIMM
DIR
EXT
IX
IX1
IX2
AB
BB
CB
FB
EB
DB
2
3
4
3
4
5
2
2
3
1
2
3
H – N Z C
AND “AND” memory with
accumulator
A&M →A
IMM
DIR
EXT
IX
IX1
IX2
A4
B4
C4
F4
E4
D4
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
ASR Shift right one bit
(accumulator or memory)
b0 →C
b7 held constant
INH (A)
INH (X)
DIR
IX
IX1
47
57
37
77
67
3
3
5
5
6
1
1
2
1
2
– – N Z C
ASL (same as LSL)
Shift left one bit
(accumulator or memory)
b7 →C
0→b0
INH (A)
INH (X)
DIR
IX
IX1
48
58
38
78
68
3
3
5
5
6
1
1
2
1
2
– – N Z C
BCC Branch on carry clear
Branch on C = 0 REL 24 3 2 – – – – –
BCLR Clear bit n BSC 11 + 2n 5 2 – – – – –
BCS Branch on carry set
Branch on C = 1 REL 25 3 2 – – – – –
BEQ Branch on result zero
Branch on Z = 1 REL 27 3 2 – – – – –
BHCC Branch if half carry clear
Branch on H = 0 REL 28 3 2 – – – – –
BHCS Branch if half carry set
Branch on H = 1 REL 29 3 2 – – – – –
BHI Branch if higher
Branch if accumulator
is higher than memory
(unsigned)
REL 22 3 2 – – – – –

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BHS Branch if higher or same
Branch if accumulator
is higher or same
as memory (C = 0)
REL 24 3 2 – – – – –
BIH Branch if interrupt line is high REL 2F 3 2 – – – – –
BIL Branch if interrupt line is low REL 2E 3 2 – – – – –
BIT Tests bits in memory: A^M
(logical compare) IMM DIR
EXT
IX
IX1
IX2
A5
B5
C5
F5
E5
D5
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
BLO Branch if lower
Branch if accumulator is lower
Branch on
REL 25 3 2 – – – – –
BLS Branch if low or same
Branch if accumulator is lower
than or equal
to memory
REL 23 3 2 – – – – –
BMC Branch if interrupt
mask bit is clear REL 2C 3 2 – – – – –
BMI Branch if minus branch
on N = 1 REL 2B 3 2 – – – – –
BMS Branch if interrupt
mask bit is set
Branch on I = 1
REL 2D 3 2 – – – – –
BNE Branch if not equal
Branch on Z = 0 REL 26 3 2 – – – – –
BPL Branch if plus
Branch on N = 0 REL 2A 3 2 – – – – –
BRA Branch always REL 20 3 2 – – – – –
BRN Branch never REL 21 3 2 – – – – –
BRCLR Branch if bit n is clear BTB 1 + 2n 5 3 – – – – C
BRSET Branch if bit n is set BTB 2n 5 3 – – – – C
BSET Set bit n BSC 10 + 2n 5 2 – – – – –
BSR Branch to subroutine REL AD 6 2 – – – – –
CLC Clear carry flag
0→CINH 98 2 1 – – – – 0
CLI Clear interrupt mask
bit 0 →IINH 9A 2 1 – 0 – – –
CLR Clear INH (A)
INH (X)
DIR
IX
IX1
4F
5F
3F
7F
6F
3
3
5
5
6
1
1
2
1
2
– – 0 1 –
TABLE 5-1: MCU INSTRUCTION TABLE (CONTINUED) (2 OF 5)
Mnemonic Explanation Address Mode (n) Hex Opcode Number of Machine Cycles Number of Bytes Flags Affected

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CMP Arithmetic compare
memory and accumulator
(unsigned)
A - M
IMM
DIR
EXT
IX
IX1
IX2
A1
B1
C1
F1
E1
D1
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z C
COM Component
(one’s complement) INH (A)
INH (X)
DIR
IX
IX1
43
53
33
73
63
3
3
5
5
6
1
1
2
1
2
– – N Z 1
CPX Arithmetic compare
memory and index X
(unsigned)
X-M
IMM
DIR
EXT
IX
IX1
IX2
A3
B3
C3
F3
E3
D3
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z C
DEC Decrement by one INH (A)
INH (X)
DIR
IX
IX1
4A
5A
3A
7A
6A
3
3
5
5
6
1
1
2
1
2
– – N Z –
EOR “Exclusive or” memory
with accumulator
A ^ M →A
IMM
DIR
EXT
IX
IX1
IX2
A8
B8
C8
F8
E8
D8
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
INC Increment by one INH (A)
INH (X)
DIR
IX
IX1
4C
5C
3C
7C
6C
3
3
5
5
6
1
1
2
1
2
– – N Z –
JMP Jump to new location
(PC + 1) →PCL
(PC + 2) →PCH
DIR
EXT
IX
IX1
IX2
BC
CC
FC
EC
DC
2
3
2
3
4
2
3
1
2
3
– – – – –
JSR Jump to new location
saving return address
PC + 2↓
(PC + 1) →PCL
(PC + 2) →PCH
DIR
EXT
IX
IX1
IX2
BD
CD
FD
ED
DD
5
6
5
6
7
2
3
1
2
3
– – – – –
TABLE 5-1: MCU INSTRUCTION TABLE (CONTINUED) (3 OF 5)
Mnemonic Explanation Address Mode (n) Hex Opcode Number of Machine Cycles Number of Bytes Flags Affected

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LDA Load accumulator
with memory
M →A
IMM
DIR
EXT
IX
IX1
IX2
A6
B6
C6
F6
E6
D6
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
LDX Load index X with memory
M →X IMM DIR
EXT
IX
IX1
IX2
AE
BE
CE
FE
EE
DE
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
LSL (same as ASL)
Shift left one bit
(accumulator or memory)
b7 →C
0 →b0
INH (A)
INH (X)
DIR
IX
IX1
48
58
38
78
68
3
3
5
5
6
1
1
2
1
2
– – N Z C
LSR Shift right one bit
(memory or accumulator)
b0 →C
0 →b7
INH (A)
INH (X)
DIR
IX
IX1
44
54
34
74
64
3
3
5
5
6
1
1
2
1
2
– – 0 Z C
MUL Multiplication
X * A →X: A INH (A) 42 11 1 0 – – – 0
NEG Negate
(Two’s complement) INH (A) INH (X)
DIR
IX
IX1
40
50
30
70
60
3
3
5
5
6
1
1
2
1
2
– – N Z C
NOP No operation INH 9D 2 1 – – – – –
ORA “OR” memory with
accumulator
A | M →A
IMM
DIR
EXT
IX
IX1
IX2
AA
BA
CA
FA
EA
DA
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z –
ROL Rotate one bit left
through carry (memory
or accumulator)
INH (A)
INH (X)
DIR
IX
IX1
49
59
39
79
69
3
3
5
5
6
1
1
2
1
2
– – N Z C
ROR Rotate one bit right
through carry (memory
or accumulator)
INH (A)
INH (X)
DIR
IX
IX1
46
56
36
76
66
3
3
5
5
6
1
1
2
1
2
– – N Z C
RSP Reset stack pointer INH 9C 2 1 – – – – –
RTI Return from interrupt PC; P INH 80 9 1 ? ? ? ? ?
TABLE 5-1: MCU INSTRUCTION TABLE (CONTINUED) (4 OF 5)
Mnemonic Explanation Address Mode (n) Hex Opcode Number of Machine Cycles Number of Bytes Flags Affected

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RTS Return from subroutine
PC ↑ ; PC + 1 →PC INH 81 6 1 – – – – –
SBC Subtract memory
from accumulator
with borrow
A-M-C →A
IMM
DIR
EXT
IX
IX1
IX2
A2
B2
C2
F2
E2
D2
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z C
SEC Set carry flag
1 →C INH 99 2 1 – – – – 1
SEI Set interrupt mask bit
I →1 INH 9B 2 1 – 1 – – –
STA Store accumulator in memory
A →M DIR EXT
IX
IX1
IX2
B7
C7
F7
E7
D7
4
5
4
5
6
2
3
1
2
3
– – N Z –
STX Store index X in memory
X →M DIR EXT
IX
IX1
IX2
BF
CF
FF
EF
DF
4
5
4
5
6
2
3
1
2
3
– – N Z –
SUB Subtract memory IMM
DIR
EXT
IX
IX1
IX2
A0
B0
C0
F0
E0
D0
2
3
4
3
4
5
2
2
3
1
2
3
– – N Z C
SWI Software interrupt INH 83 10 1 – 1 – – –
TAX Transfer accumulator
to index X
A →X
INH 97 2 1 – – – – –
TST Test for negative or
zero INH (A) INH (X)
DIR
IX
IX1
4D
5D
3D
7D
6D
3
3
4
4
5
1
1
2
1
2
– – N Z –
TXA Transfer index X to
accumulator
X →A
INH 9F 2 1 – – – – –
T5-1.5 4004
TABLE 5-1: MCU INSTRUCTION TABLE (CONTINUED) (5 OF 5)
Mnemonic Explanation Address Mode (n) Hex Opcode Number of Machine Cycles Number of Bytes Flags Affected

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Description
The following is the description of each instruction and the operation during the execution of each instruction.
The key for MCU instructions is as follows:
The first three letters are the opcode the actual mnemonic of the instruction. The possible addressing modes are
indicated by the letters following the opcode and they are as follows:
IMM: immediate addressing
INH (A): inherent addressing with respect to Accumulator
INH (X): inherent addressing with respect to Index Register
DIR: direct addressing
EXT: extended addressing
IX: indexed addressing (no offset)
IX1: indexed addressing with one byte offset
IX2: indexed addressing with two byte offset
BSC: bit set / clear
BTB: bit test and branch
REL: relative addressing
The following abbreviations are used besides the ones used for addressing mode:
A accumulator
Ccarryflag
H half carry flag
I interrupt flag
M memory
N negative flag
PC program counter
PCL program counter lower byte
PCH program counter higher byte
SP stack pointer
X index register
Z zero flag
| OR function
& AND function
^ Exclusive OR function
??? load PSW from stack
- not affected
Machine cycle is two oscillator clock cycles.

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6.0 I/O REGISTERS DEFINITION
The 32 Bytes of I/O registers occupy address locations from 0000H to 001FH and include general purpose I/O pin
registers, on-chip peripheral control registers, and SuperFlash Function Registers.
TABLE 6-1: I/O REGISTER DESCRIPTIONS
Address
Location Register Description
0000H Port A Data Register
0001H Port B Data Register
0002H Port C Data Register
0003H Reserved
0004H Port A Data Direction Register
0005H Port B Data Direction Register
0006H Port C Data Direction Register
0007H Reserved
0008H Core Timer Control Status Register
0009H Core Timer Counter Register
000AH Port B Interrupt Control Register
000BH SuperFlash Function Register (SFFR)
000CH Port B Pull-up Control Register
000DH COP Watchdog Timer Control Register (CWTC)
000EH Serial Interface Control Register (SICON_TR)
000FH Serial Interface Control Register (SICON_LSBF)
0010H Carrier Generator High Data Register1 (CHR1)
0011H Carrier Generator Low Data Register1 (CLR1)
0012H Carrier Generator High Data Register2 (CHR2)
0013H Carrier Generator Low Data Register2 (CLR2)
0014H Modulator Control and Status Register (MCSR)
0015H Modulator Data Register1 (MDR1)
0016H Modulator Data Register2 (MDR2)
0017H Modulator Data Register3 (MDR3)
0018H Power Save Control Register (PSCR)
0019H Serial Interface Control Register (SICON_SI)
001AH Serial Interface Data Register (SIDAT)
001BH Serial Interface Status Register (SISTA)
001CH Serial Interface Baud-Rate Register (SIBDR)
001DH Serial Interface Control Register (SICON_AP)
001EH Serial Interface Control Register (SICON_ENSI)
001FH IR Input Control Register
T6-1.3 4004

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TABLE 6-2: BIT DEFINITIONS OF I/O REGISTERS (1 OF 2)
Addr Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0000H Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
0001H Port B Data Register PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0002H Port C Data Register X X X X PC3 PC2 PC1 PC0
0003H Reserved X X X X X X X X
0004H Port A Data
Direction Register DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0005H Port B Data
Direction Register DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0006H Port C Data
Direction Register X X X X DDRC3 DDRC2 DDRC1 DDRC0
0007H Reserved X X X X X X X X
0008H Core Timer Control Sta-
tus Register CTOF RTIF TOFE RTIE TOFC TRFC RT1 RT0
0009H Core Timer Counter
Register XXXXXXX X
000AH Port B Interrupt
Control Register INPRB7 INPRB6 INPRB5 INPRB4 INPRB3 INPRB2 INPRB1 INPRB0
000BH SuperFlash
Function Register PREN MEREN SEREN X PROG MERA SERA X
000CH Port B Pull-up
Control Register XXXXXXPU1PU0
000DH CWT Control Register X X X X X X X CWT_EN
000EH Serial Interface
Control Register XXXXXXTRX
000FH Serial Interface
Control Register XXXXXLSBFX X
0010H Carrier Generator High
Data Register (CHR1) IROLN CMT-
POL PH5 PH4 PH3 PH2 PH1 PH0
0011H Carrier Generator Low
Data Register (CLR1) IROLP X PL5 PL4 PL3 PL2 PL1 PL0
0012H Carrier Generator High
Data Register 2(CHR2) X X SH5 SH4 SH3 SH2 SH1 SH0
0013H Carrier Generator Low
Data Register 2(CLR2) X X SL5 SL4 SL3 SL2 SL1 SL0
0014H Modulator Control and
Status Register (MCSR) EOC DIV2 EIMSK EXSPC BASE MODE EOCIE MCGEN
0015H Modulator Data
Register 1(MDR1) MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8
0016H Modulator Data
Register 2(MDR2) MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
0017H Modulator Data
Register 3(MDR3) SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
0018H Power Saving
Control Register (PSCR) ENXXXXXSTOPIDL
0019H Serial Interface
Control Register XXXXXXX SI
X = Reserved (Recommended to write “0” to reserved bits for future compatibility) T6-2.5 4004