ST STM32F103x6 User manual

Preliminary Data
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
July 2007 Rev 2 1/67
1
STM32F103x6
STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Features
■Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware
division
– Nested interrupt controller with 43
maskable interrupt channels
– Interrupt processing (down to 6 CPU
cycles) with tail chaining
■Memories
– 32-to-128 Kbytes of Flash memory
– 6-to-20 Kbytes of SRAM
■Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 32 kHz RC
– PLL for CPU clock
– Dedicated 32 kHz oscillator for RTC with
calibration
■Low power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC and backup registers
■2 x 12-bit, 1 µs A/D converters (16-channel)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Synchronizable with advanced control timer
– Temperature sensor
■DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
■Debug mode
– Serial wire debug (SWD) & JTAG interfaces
■Up to 80 fast I/O ports
– 32/49/80 5 V-tolerant I/Os
– All mappable on 16 external interrupt
vectors
– Atomic read/modify/write operations
■Up to 7 timers
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 16-bit, 6-channel advanced control timer:
up to 6 channels for PWM output
Dead time generation and emergency
stop
– 2 x 16-bit watchdog timers (Independent
and Window)
– SysTick timer: a 24-bit downcounter
■Up to 9 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
Table 1. Device summary
Reference Root part number
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8 STM32F103C8, STM32F103R8
STM32F103V8
STM32F103xB STM32F103RB STM32F103VB
LQFP64
10 x 10 mm
LQFP100
14 x 14 mm
LQFP48
7 x 7 mm BGA100
10 x 10 mm
www.st.com

STM32F103xx Description
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2.1 Device overview
Table 2. Device features and peripheral counts (STM32F103xx performance line)
Peripheral STM32F103Cx STM32F103Rx STM32F103Vx
Flash - Kbytes 32 64 32 64 128 64 128
SRAM - Kbytes 10 20 10 20 20
Timers
General purpose 232 3 3
Advanced Control 111
Communication
SPI 121 2 2
I2C121 2 2
USART 232 3 3
USB 111 1 1
CAN 1 1 1 1 1
GPIOs 32 49 80
12-bit synchronized ADC
Number of channels 2
10 channels 2 16 channels
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature -40 to +85 °C / -40 to +105 °C
Packages LQFP48 LQFP64 LQFP100,
BGA100

Description STM32F103xx
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Figure 1. STM32F103xx performance line block diagram
1. TA= –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
USBDP/CANTX
PA[15:0]
EXTI
WWDG
12bit ADC1
JTAG & SWD
16AF
JTDI
JTCK/SWCLK
JTMS/SWDIO
JNTRST
JTDO
NRST
V
DD
= 2 to 3.6V
80AF
PB[15:0]
PC[15:0]
AHB2
MOSI,MISO,SCK,NSS
SRAM
2x(8x16bit)
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 72MHz
V
SS
SCL,SDA
I2C2
V
REF+
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1 : F
max
=24 / 36 MHz
PCLK1
HCLK CLOCK
MANAGT
PCLK2
as AF
as AF
FLASH 128 KB
VOLT. REG.
3.3V TO 1.8V
POWER
Backup interface
as AF
TIM 4
BusMatrix
64 bit
Interface
20 KB
RTC
RC 8 MHz
CORTEX M3 CPU
Ibus
Dbus
pbus
obl
flash
SRAM 512B
Trace
Controller
USART1
USART2
SPI2
bxCAN
7 channels
Backup
reg
4 Channels
TIM1
3 compl. Channels
SCL,SDA,SMBAL
I2C1 as AF
RX,TX, CTS, RTS,
USART3
Temp sensor
V
REF-
PD[15:0] GPIOD
PE[15:0] GPIOE
AHB:Fmax=48/72 MHz
Brk input
4 Channels
4 Channels
8 Channels
FCLK
RC 32 kHz
Standby
IWDG
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
SmartCard as AF
RX,TX, CTS, RTS,
SmartCard as AF
RX,TX, CTS, RTS,
SmartCard as AF
APB2 : F
max
=48 / 72 MHz
NVIC
SPI1
MOSI,MISO,
SCK,NSS as AF
12bit ADC2
IF
IFIF
interface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2 APB1
AWU ANTI_TAMP
@VDD
USB 2.0 FS USBDM/CANRX
System
ai14390

STM32F103xx Pin descriptions
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3 Pin descriptions
Figure 2. STM32F103xx performance line LQFP100 pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4 PA5 PA6 PA7
PC4 PC5
PB0 PB1 PB2 PE7 PE8 PE9
PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11
VSS_1
VDD_1
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0-WKUP
PA1
PA2
ai14391
LQFP100

Pin descriptions STM32F103xx
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Figure 3. STM32F103xx performance line LQFP64 pinout
Figure 4. STM32F103xx performance line LQFP48 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4 PA5 PA6 PA7
PC4 PC5
PB0 PB1 PB2
PB10 PB11
VSS_1
VDD_1
LQFP64
ai14392
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
PA3 PA4 PA5 PA6 PA7
PB0 PB1 PB2
PB10 PB11
VSS_1
VDD_1
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14
LQFP48
ai14393

STM32F103xx Pin descriptions
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Figure 5. STM32F103xx performance line BGA100 ballout
AI16001
PE10
PC14-
OSC32_IN
PC5PA5
PC3
PB4
PE15
PB2
PC4PA4
H
PE14
PE11PE7
D PD4
PD3
PB8PE3
C
PD0
PC12
PE5
PB5
PC0
PE2
B PC11PD2
PC15-
OSC32_OUT
PB7
PB6
A
87654321
VSS_5 OSC_IN
OSC_OUT VDD_5
G
F
E
PC1
VREF–
PC13-
ANTI_TAMP PB9 PA15
PB3
PE4 PE1
PE0
VSS_1 PD1PE6NRST PCD VSS_3 VSS_4
NCVDD_3 VDD_4
PB15
VBAT PD5
PD6
BOOT0 PD7
VSS_2
VSSA
PA1
VDD_2 VDD_1
PB14
PA0-WKUP
109
K
J
PD10
PD11
PA8
PA9
PA10
PA11
PA12
PC10
APA13 PA14
PC9 PC7
PC6
PD15
PC8
PD14
PE12
PB1PA7 PB11
PE8
PB0PA6 PB10
PE13PE9VDDA
PB13
VREF+
PA3 PB12
PA2
PD8
PD9 PD13
PD12

Pin descriptions STM32F103xx
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Table 3. Pin definitions
Pins
Pin name
Type(1)
I / O Level(2)
Main function(3)
(after reset) Default alternate functions
BGA100
LQFP48 LQFP64
LQFP100
A3 - - 1 PE2/TRACECK I/O FT PE2 TRACECK
B3 - - 2 PE3/TRACED0 I/O FT PE3 TRACED0
C3 - - 3 PE4/TRACED1 I/O FT PE4 TRACED1
D3 - - 4 PE5/TRACED2 I/O FT PE5 TRACED2
E3 - - 5 PE6/TRACED3 I/O FT PE6 TRACED3
B2 1 1 6 VBAT SV
BAT
A2 2 2 7 PC13-ANTI_TAMP(4) I/O PC13 ANTI_TAMP
A1 3 3 8 PC14-OSC32_IN(4) I/O PC14-OSC32_IN
B1 4 4 9 PC15-OSC32_OUT(4) I/O PC15-OSC32_OUT
C2 - - 10 VSS_5 SV
SS_5
D2 - - 11 VDD_5 SV
DD_5
C1 5 5 12 OSC_IN I OSC_IN
D1 6 6 13 OSC_OUT O OSC_OUT
E1 7 7 14 NRST I/O NRST
F1 - 8 15 PC0/ADC_IN10 I/O PC0 ADC_IN10
F2 - 9 16 PC1/ADC_IN11 I/O PC1 ADC_IN11
E2 - 10 17 PC2/ADC_IN12 I/O PC2 ADC_IN12
F3 - 11 18 PC3/ADC_IN13 I/O PC3 ADC_IN13
G1 8 12 19 VSSA SV
SSA
H1 - - 20 VREF- SV
REF-
J1 - - 21 VREF+ SV
REF+
K1 9 13 22 VDDA SV
DDA
G2 10 14 23 PA0-WKUP/ USART2_CTS/
ADC_IN0/TIM2_CH1_ETR I/O PA0 WKUP/USART2_CTS(6)/AD
C_IN0/
TIM2_CH1_ETR(6)
H2 11 15 24 PA1/USART2_RTS/
ADC_IN1/TIM2_CH2 I/O PA1 USART2_RTS(6)/
ADC_IN1/
TIM2_CH2(6)
J2 12 16 25 PA2/USART2_TX/
ADC_IN2/ TIM2_CH3 I/O PA2 USART2_TX(6)/
ADC_IN2/ TIM2_CH3(6)
K2 13 17 26 PA3/USART2_RX/
ADC_IN3/TIM2_CH4 I/O PA3 USART2_RX(6)/
ADC_IN3/TIM2_CH4(6)
E4 - 18 27 VSS_4 SV
SS_4
F4 - 19 28 VDD_4 SV
DD_4

STM32F103xx Pin descriptions
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G3 14 20 29 PA4/SPI1_NSS/
USART2_CK/ADC_IN4 I/O PA4 SPI1_NSS(6)/
USART2_CK(6)/ ADC_IN4
H3 15 21 30 PA5/SPI1_SCK/ ADC_IN5 I/O PA5 SPI1_SCK(6)/ ADC_IN5
J3 16 22 31 PA6/SPI1_MISO/
ADC_IN6/TIM3_CH1 I/O PA6 SPI1_MISO(6)/
ADC_IN6/TIM3_CH1(6)
K3 17 23 32 PA7/SPI1_MOSI/
ADC_IN7/TIM3_CH2 I/O PA7 SPI1_MOSI(6)/
ADC_IN7/TIM3_CH2(6)
G4 - 24 33 PC4/ADC_IN14 I/O PC4 ADC_IN14
H4 - 25 34 PC5/ADC_IN15 I/O PC5 ADC_IN15
J4 18 26 35 PB0/ADC_IN8/ TIM3_CH3 I/O PB0 ADC_IN8/TIM3_CH3(6)
K4 19 27 36 PB1/ADC_IN9/ TIM3_CH4 I/O PB1 ADC_IN9/TIM3_CH4(6)
G5 20 28 37 PB2 / BOOT1 I/O FT PB2/BOOT1
H5 - - 38 PE7 I/O FT PE7
J5 - - 39 PE8 I/O FT PE8
K5 - - 40 PE9 I/O FT PE9
G6 - - 41 PE10 I/O FT PE10
H6 - - 42 PE11 I/O FT PE11
J6 - - 43 PE12 I/O FT PE12
K6 - - 44 PE13 I/O FT PE13
G7 - - 45 PE14 I/O FT PE14
H7 - - 46 PE15 I/O FT PE15
J7 21 29 47 PB10/I2C2_SCL/
USART3_TX I/O FT PB10 I2C2_SCL/USART3_TX(5)(6)
K7 22 30 48 PB11/I2C2_SDA /
USART3_RX I/O FT PB11 I2C2_SDA/
USART3_RX(5)(6)
E7 23 31 49 VSS_1 SV
SS_1
F7 24 32 50 VDD_1 SV
DD_1
K8 25 33 51 PB12/SPI2_NSS / I2C2_SMBAl/ USART3_CK /
TIM1_BKIN I/O FT PB12
SPI2_NSS(5)
/I2C2_SMBAl(5)/
USART3_CK(5)(6)/
TIM1_BKIN(6)
J8 26 34 52 PB13/SPI2_SCK / USART3_CTS /
TIM1_CH1N I/O FT PB13 SPI2_SCK(5)/
USART3_CTS(5)(6)/
TIM1_CH1N (6)
H8 27 35 53 PB14/SPI2_MISO / USART3_RTS /
TIM1_CH2N I/O FT PB14 SPI2_MISO(5)
/USART3_RTS(5)(6)
TIM1_CH2N (6)
Table 3. Pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main function(3)
(after reset) Default alternate functions
BGA100
LQFP48 LQFP64
LQFP100

Pin descriptions STM32F103xx
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G8 28 36 54 PB15/SPI2_MOSI
TIM1_CH3N I/O FT PB15 SPI2_MOSI(5)/
TIM1_CH3N(6)
K9 - - 55 PD8 I/O FT PD8
J9 - - 56 PD9 I/O FT PD9
H9 - - 57 PD10 I/O FT PD10
G9 - - 58 PD11 I/O FT PD11
K10 - - 59 PD12 I/O FT PD12
J10 - - 60 PD13 I/O FT PD13
H10 - - 61 PD14 I/O FT PD14
G10 - - 62 PD15 I/O FT PD15
F10 - 37 63 PC6 I/O FT PC6
E10 38 64 PC7 I/O FT PC7
F9 39 65 PC8 I/O FT PC8
E9 - 40 66 PC9 I/O FT PC9
D9 29 41 67 PA8/USART1_CK/
TIM1_CH1/MCO I/O FT PA8 USART1_CK/
TIM1_CH1(6)/MCO
C9 30 42 68 PA9/USART1_TX/
TIM1_CH2 I/O FT PA9 USART1_TX(6)/
TIM1_CH2(6)
D10314369 PA10/USART1_RX/
TIM1_CH3 I/O FT PA10 USART1_RX(6)/
TIM1_CH3(6)
C10324470 PA11 / USART1_CTS/ CANRX / USBDM/
TIM1_CH4 I/O FT PA11 USART1_CTS/
CANRX(6)/
TIM1_CH4(6) / USBDM
B10334571 PA12 / USART1_RTS/ CANTX / USBDP/
TIM1_ETR I/O FT PA12 USART1_RTS/
CANTX(6) /
TIM1_ETR(6) / USBDP
A10344672 PA13/JTMS/SWDIO I/O FT JTMS/SWDIO PA13
F8 - - 73 Not connected
E6 35 47 74 VSS_2 SV
SS_2
F6 36 48 75 VDD_2 SV
DD_2
A9 37 49 76 PA14/JTCK/SWCLK I/O FT JTCK/SWCLK PA14
A8 38 50 77 PA15/JTDI I/O FT JTDI PA15
B9 - 51 78 PC10 I/O FT PC10
B8 - 52 79 PC11 I/O FT PC11
C8 - 53 80 PC12 I/O FT PC12
Table 3. Pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main function(3)
(after reset) Default alternate functions
BGA100
LQFP48 LQFP64
LQFP100

STM32F103xx Pin descriptions
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D8 5 5 81 PD0 I/O FT OSC_IN(7)
E8 6 6 82 PD1 I/O FT OSC_OUT(7)
B7 54 83 PD2/TIM3_ETR I/O FT PD2 TIM3_ETR
C7 - - 84 PD3 I/O FT PD3
D7 - - 85 PD4 I/O FT PD4
B6 - - 86 PD5 I/O FT PD5
C6 - - 87 PD6 I/O FT PD6
D6 - - 88 PD7 I/O FT PD7
A7 39 55 89 PB3/JTDO/TRACESWO I/O FT JTDO PB3/TRACESWO
A6 40 56 90 PB4/JNTRST I/O FT JNTRST PB4
C5 41 57 91 PB5/I2C1_SMBAl I/O PB5 I2C1_SMBAl
B5 42 58 92 PB6/I2C1_SCL/ TIM4_CH1 I/O FT PB6 I2C1_SCL(6)/
TIM4_CH1(5)(6)
A5 43 59 93 PB7/I2C1_SDA/ TIM4_CH2 I/O FT PB7 I2C1_SDA(6)/
TIM4_CH2(5) (6)
D5 44 60 94 BOOT0 I BOOT0
B4 45 61 95 PB8/TIM4_CH3 I/O FT PB8 TIM4_CH3(5) (6)
A4 46 62 96 PB9/TIM4_CH4 I/O FT PB9 TIM4_CH4(5) (6)
D4 - - 97 PE0/TIM4_ETR I/O FT PE0 TIM4_ETR(5)
C4 - - 98 PE1 I/O FT PE1
E5 47 63 99 VSS_3 SV
SS_3
F5 48 64 100 VDD_3 SV
DD_3
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. Refer to Table 2 on page 7.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.
7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
Table 3. Pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main function(3)
(after reset) Default alternate functions
BGA100
LQFP48 LQFP64
LQFP100

Memory mapping STM32F103xx
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4 Memory mapping
The memory map is shown in Figure 6.
Figure 6. Memory map
reserved
1 Kbit
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 0C00
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 3800
0x4000 3C00
0x4000 4400
0x4000 4800
0x4000 4C00
0x4001 0C00
0x4001 1000
0x4001 1400
0x4001 1800
0x4002 1400
APB memory space
DMA
0x4002 1000
TIM2
Reserved
0x4001 0800
0x4001 1C00
0x4001 2400
0x4001 2800
0x4001 2C00
0x4001 3000
0x4001 3400
0x4001 3800
TIM3
TIM4
reserved
RTC
WWDG
IWDG
reserved
SPI2
USART2
USART3
AFIO
Port A
Port C
Port D
reserved
ADC1
reserved
USART1
reserved
0x4002 0400
0x4002 0000
0x4001 3C00
0x4000 5400
0x4000 5800
reserved
ADC2
TIM1
SPI1
reserved
I2C1
BKP
0x4000 6000
0x4000 5C00
1 Kbit
35 Kbits
1 Kbit
1 Kbit
2 Kbits
1 Kbit
1 Kbit
2 Kbits
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
7 Kbits
1 Kbit
Port E
PWR
Port B
1 Kbit
1 Kbit
1 Kbit
3 Kbits
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
2 Kbits
1 Kbit
1 Kbit
1 Kbit
I2C2
reserved
bxCAN
EXTI
reserved
RCC
reserved
Flash Interface
reserved
reserved
reserved
0x4000 6400
0x4000 6800
0x4000 6C00
0x4000 7000
0x4000 7400
0x4001 0000
0x4001 0400
0x4002 2000
0x4002 2400
0x4002 3000
0x4002 3400
0x6000 0000
0xE010 0000
reserved
0xFFFF FFFF
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
3 Kbits
1 Kbit
3 Kbits
1 Kbit
4 Kbits
USB Registers
reserved
0
1
2
3
4
5
6
7
0x2000 0000
0x4000 0000
0x6000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0xE000 0000
0xFFFF FFFF
0x0000 0000
CODE
0xFFFF F000
PERIPHERALS
SRAM
FLASH
reserved
reserved
0x0800 0000
0x0801 FFFF
0x1FFF F000
0x1FFF FFFF
SYSTEM MEMORY
OPTION BYTES
0x1FFF F800
0x1FFF F9FF
Cortex-M3 Internal
Peripherals
0xE010 0000
ai14394
shared 512 byte
USB/CAN SRAM

Electrical characteristics STM32F103xx
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5.1.6 Power supply scheme
Figure 9. Power supply scheme
Figure 7. Pin loading conditions Figure 8. Pin input voltage
ai14141
C = 50 pF
STM32F103xx pin
ai14142
STM32F103xx pin
VIN
ai14125
3.3V
VDD
1/2/3/4/5
Analog:
RCs, PLL,
...
Power switch
VBAT 3.3 V
GP I/Os
OUT
IN
Kernel logic
(CPU,
Digital
& Memories)
Backup circuitry
(OSC32K,RTC,
Backup registers)
Wake-up logic
5 × 100 nF
+ 1 × 10 µF
1.8-3.6 V
Regulator
VSS
1/2/3/4/5
VDDA
VREF+
VREF-
VSSA
ADC
Level shifter
IO
Logic
VDD
10 nF
+ 1 µF
VREF
10 nF
+ 1 µF
VDD

STM32F103xx Electrical characteristics
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5.1.7 Current consumption measurement
Figure 10. Current consumption measurement scheme
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD

Electrical characteristics STM32F103xx
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5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,
Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 4. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS External 3.3 V supply voltage (including VDDA
and VDD)(1)
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
–0.3 4.0
V
VIN Input voltage on five volt tolerant pin(2)
2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN < VSS.
VSS −0.3 +5.5
Input voltage on any other pin(2) VSS −0.3 VDD+0.3
|∆VDDx| Variations between different power pins 50 50 mV
|VSSX −VSS| Variations between all the different ground pins 50 50
VESD(HBM) Electrostatic discharge voltage (human body
model)
see Section 5.3.11:
Absolute maximum ratings
(electrical sensitivity)
Table 5. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD power lines (source)(1)
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
150
mA
IVSS Total current out of VSS ground lines (sink)(1) 150
IIO Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin −25
IINJ(PIN) (2)(3)
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
Injected current on NRST pin ± 5
Injected current on HSE OSC_IN and LSE OSC_IN pins ± 5
Injected current on any other pin(4)
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
± 5
ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25

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5.3 Operating conditions
5.3.1 General operating conditions
5.3.2 Operating conditions at power-up / power-down
The parameters given in Table 8 are derived from tests performed under the ambient
temperature condition summarized in Table 7.
Table 8. Operating conditions at power-up / power-down
Table 6. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature (see Thermal characteristics)
Table 7. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 72
MHzfPCLK1 Internal APB1 clock frequency 0 36
fPCLK2 Internal APB2 clock frequency 0 72
VDD Standard operating voltage 2 3.6 V
VBAT Backup operating voltage 1.8 3.6 V
TAAmbient temperature range −40 105 °C
Symbol Parameter Conditions Min Typ Max Unit
tVDD VDD rise/fall time rate 20 µs/V
20 ms/V

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5.3.3 Embedded reset and power control block characteristics
The parameters given in Table 9 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
5.3.4 Embedded reference voltage
The parameters given in Table 10 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 9. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
VPVDhyst PVD hysteresis 100 mV
VPOR/PDR Power on/power down reset
threshold Falling edge 1.8 1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst PDR hysteresis 40 mV
TRSTTEMPO Reset temporization 1 2.5 4.5 mS
Table 10. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage −45°C < TA< +105°C 1.16 1.20 1.26 V
−45°C < TA< +85°C 1.16 1.20 1.24 V

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5.3.5 Supply current characteristics
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
●All I/O pins are in input mode with a static value at VDD or VSS (no load)
●All peripherals are disabled except if it is explicitly mentioned
●The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz and 2 wait states above)
The parameters given in Table 11 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 11. Maximum current consumption in Run and Sleep modes(1)
Symbol Parameter Conditions FHCLK Typ(2) Max(3) Unit
TA=
85 °C TA= 105 °C
IDD
Supply
current in
Run mode
External clock with PLL, code running from
Flash, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
72 MHz 36 TBD TBD
mA
48 MHz 30 TBD TBD
36 MHz 22 TBD TBD
24 MHz 21 TBD TBD
External clock, PLL stopped, code running
from Flash, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
8 MHz 10 TBD TBD
External clock with PLL, code running from
RAM, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
72 MHz 32 45 47
48 MHz 22 31 33
36 MHz 13 18 20
24 MHz 11 15 17
External clock, PLL stopped, code running
from RAM, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
8 MHz 4.5 TBD TBD
Supply
current in
Sleep mode
External clock with PLL, code running from
RAM or Flash, all peripherals enabled (see
RCC register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
72 MHz 22 35 37
mA
48 MHz 14 23 25
36 MHz 13 22 24
24 MHz 10 17 19
External clock, PLL stopped, code running
from RAM or Flash, all peripherals enabled
(see RCC register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
8 MHz 3.5 TBD TBD
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, and VDD = 3.3 V
3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM.

Electrical characteristics STM32F103xx
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Table 12. Maximum current consumption in Stop and Standby modes(1)
Symbol Parameter Conditions
Typ(2) Max(3)
Unit
VDD/VBAT
= 2.4 V VDD/VBAT = 3.3 V TA= 85 °C TA= 105 °C
IDD
Supply current
in Stop mode
Regulator in Run mode,
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
TBD 24 TBD TBD
µA
Regulator in Low Power mode,
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
TBD(4) 14(4) TBD(4) TBD(4)
Supply current
in Standby
mode(5)
Low-speed internal RC oscillator and
independent watchdog OFF, low-
speed oscillator and RTC OFF TBD(4) 2(4) TBD(4) TBD(4)
IDD_VBAT Backup domain
supply current Low-speed oscillator and RTC ON 1(4) 1.4(4) TBD(4) TBD(4)
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified.
3. Data based on characterization results, tested in production at VDD max, fHCLK max. and TAmax (for other temperature.
4. Values expected for next silicon revision.
5. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).

STM32F103xx Electrical characteristics
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Typical current consumption
The MCU is placed under the following conditions:
●All I/O pins are in input mode with a static value at VDD or VSS (no load).
●All peripherals are disabled except if it is explicitly mentioned.
●The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHZ and 2 wait states above).
●Ambient temperature and VDD supply voltage conditions summarized in Table 7.
Table 13. Typical current consumption in Run and Sleep modes(1)
1. TBD stands for to be determined.
Symbol Parameter Conditions fHCLK Typ(2)
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Unit
IDD
Supply
current in
Run mode
Oscillator running at 8 MHz with PLL, code
running from Flash, all peripheral disabled
(see RCC register description): fPCLK1=
fHCLK/2, fPCLK2=fHCLK
72 MHz 21
mA
48 MHz 18
36 MHz TBD
24 MHz 13
16 MHz TBD
Running on HSI clock, code running from
Flash, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
8 MHz 7.8
mA
4 MHz 7
2 MHz 6.3
1 MHz 6.2
500 kHz 6.1
125 kHz 5.95
Running on HSI clock, code running from
RAM, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
8 MHz 2.3
mA
4 MHz 1.6
2 MHz 1.2
1 MHz 1
500 kHz 0.88
125 kHz 0.82
Supply
current in
Sleep mode
Oscillator running at 8MHz with PLL, code
running from Flash, all peripheral disabled
(see RCC register description): fPCLK1=
fHCLK/2, fPCLK2=fHCLK
72 MHz 6 mA
48 MHz TBD
36 MHz TBD
24 MHz TBD
16 MHz 1
Running on HSI clock, code running from
Flash, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
8 MHz TBD
mA
4 MHz TBD
2 MHz TBD
1 MHz TBD
500 kHz TBD

Electrical characteristics STM32F103xx
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Table 14. Typical current consumption in Stop and Standby modes(1)
Symbol Parameter Conditions VDD Typ(2) Unit
IDD
Supply current in
Stop mode
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators OFF
High-speed oscillator OFF (no
independent watchdog)
3.3 V 24
µA
2.4 V TBD
Regulator in Low Power mode,
Low-speed and high-speed internal RC
oscillators OFF,
High-speed oscillator OFF (no
independent watchdog)
3.3 V 14(3)
2.4 V TBD(3)
Supply current in
Standby mode(4)
Low-speed internal RC oscillator and
independent watchdog OFF 3.3 V 2(3)
µA
2.4 V TBD(3)
Low-speed internal RC oscillator and
independent watchdog ON 3.3 V 3.1(3)
2.4 V TBD(3)
Low-speed internal RC oscillator ON,
independent watchdog OFF 3.3 V 2.9(3)
2.4 V TBD(3)
IDD_VBAT Backup domain
supply current
Low-speed oscillator and RTC ON 3.3 V 1.4(3)
µA
2.4 V 1(3)
Low-speed oscillator OFF, RTC ON 3.3 V 0.5(3)
2.4 V TBD(3)
1. TBD stands for to be determined.
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
3. Values expected for next silicon revision.
4. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD
Standby.