ST M29W128GH User manual

November 2007 Rev 2 1/9
UM0453
User manual
M29W128GH/L Flash memory VHDL model v1.1
1 Introduction
This user manual describes the VHDL (VHSIC hardware description language) v1.1
behavioral model for the M29W128GH and M29W128GL Flash memory devices.
Organization of the VHDL model delivery package
The VHDL model delivery package is organized into a main directory, named
ST_M29W128G_V11.zip, containing six subdirectories with their related files (see
Figure 1).
■code subdirectory: contains the code
■lib subdirectory: contains library source files
■sim subdirectory: contains the simulation initialization files
■stim subdirectory: contains the stimuli files used for simulation
■top subdirectory: contains the testbench file used for simulation
■doc subdirectory: contains the application note for the model
Figure 1. Package architecture
Note: See the readme.txt file for the complete list of files contained in each folder.
Ai14413b
ST_M29W128G_V11.zip
doc
sim
code stim
readme.txt
run_ncsim
m29w128g.vhd VHDL model
M29W128G_V1.1_UserManual.pdf
memory_file
CFImemory_file
NVMP_file
Autoselect.vhd
BlockErase.vhd
CFIAutoSelect.vhd
ChipErase.vhd
BufferProgram.vhd
EraseProgramSuspend.vhd
EraseSuspend.vhd
ExtendedBlock.vhd
Program.vhd
ProgramSuspend.vhd
ReadCFI.vhd
SpecialBusOp.vhd
UnlockBypass.vhd
VPPBypass.vhd
top
TestBench.vhd tesbench file
lib
block_data.vhd
extended_memory.vhd
generic_data.vhd
protection_group.vhd
string_util.vhd
utility_pack.vhd
www.st.com

Contents UM0453
2/9
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 VHDL behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Testbench and stimuli files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Simulation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Launching a simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Simulation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 memory_file file format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 VHDL types used in model ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

UM0453 List of tables
3/9
List of tables
Table 1. Simulation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Model ports for the M29W128G devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Device description UM0453
4/9
2 Device description
The M29W128GH and M29W128GL are 128 Mbit (8 Mb x16 or 16 Mb x8 or) non-volatile
Flash memories that can be read, erased, and reprogrammed. These operations can be
performed using a single low voltage (2.7 to 3.6 V) supply. Upon power-up, the memory
defaults to read mode.
The memory array is divided into 64 Kword/128 Kbyte uniform blocks that can be erased
independently so it is possible to preserve valid data while old data is erased. Program and
erase commands are written to the command interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
managing all of the special operations that are required to update the memory contents. The
end of a program or erase operation can be detected and any error conditions are identified.
The command set required to control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable, and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The M29W128GH and M29W128GL support asynchronous random read and page read
from all blocks of the memory array. The devices also feature a write to buffer program
capability that improves the programming throughput by programming in one instance a
buffer of 32 words/64 bytes. The VPP/WP signal can be used to enable faster programming
of the device.
The M29W128GH and M29W128GL have an extra block, the extended block, of 128 words
in x16 mode or of 256 bytes in x8 mode that can be accessed using a dedicated command.
The extended block can be protected and, therefore, is useful for storing security
information. However, the protection is not reversible; once protected, the protection cannot
be undone.
The device features different levels of hardware and software block protection to avoid
unwanted program or erase (modify):
●Hardware protection:
–TheV
PP/WP provides hardware protection of the highest and lowest block on the
M29W128GH , M29W128GL, respectively.
●Software protection:
– Volatile protection
– Non-volatile protection
– Password protection

UM0453 VHDL behavioral model
5/9
3 VHDL behavioral model
The M29W128G VHDL behavioral model v1.1 is located in the M29W128G.vhd file of the
code subdirectory. The following two VHDL generic parameters in the
code/m29w128g.vhd file decide which device is used:
●select_dev = 1 for M29W128GH
●select_dev = 0 for M29W128GL
The behavioral model includes a set of libraries that implement all the device functions listed
in the device datasheets. SeeSection 3.1 for the description of the libraries.
This model was validated using a Cadence NC-SIM 5.4 simulator. The use of this model
with other simulators is not guaranteed.
3.1 Model libraries
The code/M29W128G.vhd VHDL file and libraries code files must be compiled in the same
order as listed in this section, and specified in the run_ncsim file.
1. string_util.vhd
This library contains the utilities used for string management.
2. generic_data.vhd
This library contains generic constants.
3. utility_pack.vhd
This library contains some generic procedures.
4. protection_group.vhd
This library contains functions for protection group management.
5. extended_memory.vhd
This library contains generic constants for extended memory management.
6. timing_data.vhd
This library contains the definition of constants related to the timing constraints of the
device.
7. block_data.vhd
This library contains generic constants and functions for blocks management
3.2 Testbench and stimuli files
The top subdirectory of the VHDL model delivery package contains a testbench file,
TestBench.vhd.
Stimuli files in VHDL format are available in the stim subdirectory. These files cover many
operational conditions of the device, in particular, the CUI (command user interface)
commands.
The testbench and the stimuli files are written using the standard VHDL version.

Simulation guidelines UM0453
6/9
4 Simulation guidelines
4.1 Launching a simulation
The run_ncsim file (located in the main directory) is an example of the script used to launch
a simulation using a Cadence NC-SIM simulator. This script compiles and elaborates the
VHDL model file and the stimuli files contained into the stim directory.
4.2 Simulation timings
Table 1 lists program and erase times in the VHDL simulation model.
4.3 memory_file file format
To simplify the testing of the memory array behavior and of the model functionality, the
memory array must be loaded with specific data at power-up.
The format of the memory_file, located in the sim subdirectory, must be:
hex_first_address/hex_data
For example: 07FFFF/7FFF.
The file name must be written to the entity file (this filename path cannot be empty):
generic(memoryfile: string := path/filename).
If the initialization file is not provided, all the memory bits are set to'1', and the whole array is
erased.
Similarly, the CFImemory_file file loads the model CFI area of the M29W128GH/L. All
these files are located in the sim subdirectory.
Not all sectors are protected. To protect one group, the Boolean value of the relative index
group in the Protection Group Init array in file NVMP_file must be modified.
Table 1. Simulation timings
Timing Real time Simulation time Unit
Block erase 0.5 500*10-6 s
Chip erase 40 400*10-6 s
Word program 16 16 µs
Program suspend latency 5 5 µs
Erase suspend latency 50 50 µs

UM0453 VHDL types used in model ports
7/9
5 VHDL types used in model ports
The port section of M29W128G VHDL model defines the port name and related port type for
each signal of the device, as shown in Table 2.
Table 2. Model ports for the M29W128G devices
Port Type Description
A0-A22 Standard logic (22 down to 0) Address inputs
DQ0-DQ14 Standard logic (14 down to 0) Data input/output
Dq15A-1 Standard logic Data input/output or address input
BYTE Standard logic Byte/word organization select
E_N Standard logic Chip Enable
G_N Standard logic Output Enable
W_N Standard logic Write Enable
RP_N Real Reset/block temporary unprotect
VPP/WP_N Real VPP/Write protect
RB Standard logic Read/busy output
VSS Real Ground
VCC Real Supply voltage
VCCQ Real Supply voltage

Revision history UM0453
8/9
6 Revision history
Table 3. Document revision history
Date Revision Changes
10-Sep-2007 1 Initial release.
20-Nov-2007 2
Updated the document to reflect increment in software version (1.0
to 1.1). In Table 1: Simulation timings: added the unit column,
changed the Chip erase times from 80, 800*10-6
to 40, 400*10-6 respectively.

UM0453
9/9
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com