Sycard Technology PCCextend 100 User manual
SYCARD
TECHNOLOGY
Sycard
Technology
1180-F
Miraloma
Way
Sunnyvale, CA 94086
(408) 749-0130
(408) 749-1323
FAX
PCCextend 100
User's Manual
Preliminary
M200001-00
Apri/3,
1995
BLACKBERRY Ex. 1004, page 1
BLACKBERRY Ex. 1004, page 2
PCCextend 100 User’s Manual Page 1
M200001-00 1994-95 Sycard Technology
1.0 Introduction1.0 Introduction
Sycard Technology's PCCextend 100 PCMCIA extender card is a debug tool for PCMCIA development and test.
PCCextend offers the following features:
•PCCswitch simulates card removal/insertion cycle
•Low profile design compatible with type I, II and III sockets
•4 layer construction to insure low noise environment
•All 68 pins available as test points
•Both I/O and memory mode signals clearly marked
•Vcc, Vpp1 and Vpp2 can be isolated through jumper blocks for current measurements
•Surface mount resistors and/or capacitors can be added to any signal line
•Vcc LEDs indicate 3.3V or 5V operation
•Convenient grounding posts for scope probes or other test equipment
2.0 Using the PCCextend 1002.0 Using the PCCextend 100
Using the PCCextend is relatively straightforward. The extender card is inserted into the desired slot in the host
system. Then the PC Card under test is inserted into the card connector.
CautionCaution: Insertion and removal of the extender and PC card should be done with care. The PC Card's
fragile connectors may be broken or bent if improper force is used. Both card and extender should be
inserted straight without any lateral movement or force. Proper care and use of the extender card will insure
years of trouble free operation.
BLACKBERRY Ex. 1004, page 3
Page 2PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
PCMCIA
CARD EXTENDER
PCCextend
Figure 2.0-1 The PCCextend 100Figure 2.0-1 The PCCextend 100
BLACKBERRY Ex. 1004, page 4
PCCextend 100 User’s Manual Page 3
M200001-00 1994-95 Sycard Technology
2.1 Test points2.1 Test points
All 68-pins of the interface are available to probe through clearly marked headers.
WP
IOIS16
D1
A0
A2
A4
A6
A12
A16
Vcc
-WE
A13
A9
-OE
-CE1
D6
D4
GND
GND
D2
D0
A1
A3
A5
A7
A15
Vpp1
RDY
-IRQ
A14
A8
A11
A10
07
05
03
-C02
D9
BVD1/
-STCHG
-REG
-WAIT
-VS2
A24
A22
Vcc
A20
A18
-IOWR
-VS1
D15
D13
D11
GND
GND
D10
D8
BVD2
-SPKR
INPACK
RESET
A25
A23
VPP2
A21
A19
A17
-IORD
-CE2
D14
D12
-CD1
PWR5V
CD2
CD1
SW1
Vpp1
Vcc
Vpp2
JP6
JP5
Vcc Gnd
Gnd
Vcc
2.2 Power Indicators2.2 Power Indicators
Two LED power indicators display the status of the socket’s Vcc. The PWR LED indicates that power is applied to
the board. When both the PWR LED and the 5V LED are lit, a Vcc of greater than approximately 3.5V is present.
When only the PWR LED is lit, the Vcc is at a level of less than 3.5V.
NoteNote: The power LEDs are designed to indicate the presence of power on the Vcc supply pins. The LEDs
do not provide an accurate measurement of Vcc. Use a voltmeter to determine the actual operating voltage.
2.2 Current Measurements2.2 Current Measurements
Vcc, Vpp1 and Vpp2 power buses may be isolated from the PC Card socket through three sets of jumper blocks.
Each jumper block consists of two sets of jumpers. Both jumpers must be removed to isolate the power. A current
meter can be inserted to measure card current consumption.
CautionCaution: Care must be taken to insure that the current measuring device is inserted before turning on power
to the host socket. Improper power sequencing may cause a damaging latchup condition.
2.3 Using the PCCswitch2.3 Using the PCCswitch
PCCextend 100 includes the PCCswitch, which can be used to momentarily interrupt the CD1 and CD2 signals.
The PCCswitch is centrally located on the PCCextend 100 between the termination area and test points. When
properly configured, the PCCswitch can interrupt the card detect signals (-CD1 and -CD2) to simulate a card
removal/insertion cycle. Two three pin headers are used to configure the PCCswitch. When both CD1 and CD2
headers are in the “A” position, CD1 and CD2 are routed directly from the host socket to the PCCextend socket.
BLACKBERRY Ex. 1004, page 5
Page 4PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
When the jumpers are in this position the PCCswitch is not in the circuit. In the “B” position, the host socket’s CD1
and CD2 is routed through the PCCswitch to the CD1 signal on the PCCextend socket. When a card is inserted, CD1
and CD2 may be momentarily interrupted by pressing the PCCswitch.
CD2
CD1
CD2
CD1
Position A Position B
Figure 2.3-1 Card Detect SwitchFigure 2.3-1 Card Detect Switch
To test the operation of the PCCswitch, be sure that your PC Card Software drivers are loaded. Momentarily press
the PCCtest switch. Most software drivers will issue a removal beep followed by an insertion beep. The software
may also remove power from the socket when the card is removed.
2.4 Termination and Prototype Area2.4 Termination and Prototype Area
A termination area located between the test points and the card connector allows access to all PC Card signals. A
series of surface mount pads allows the user to add series resistors, pull-down resistor, or capacitance to any signal.
The SMT pads are arranged as follows:
When shipped from the factory, the resistor pads are shorted with PCB traces. In order to insert series resistor, these
traces must be cut prior to soldering the resistor to the board. Pull-down resistors may be inserted by adding a resistor
to the corresponding SMT capacitor pad. Filter capacitors may be added by inserting a small capacitor into the
corresponding SMT capacitor pad. Figure 2.4-1 and 2.4-2 illustrate the termination areas located on both sides of the
PCCextend board. Use this guide when making modifications to the board, since the silk-screen designations may be
difficult to read.
R60 C60
R3
R1
R18
R20
R22
R24
R42
C3
C1
C18
C20
C22
C24
C42
R51 C51
R31
R25
R28
R27
R8
R6
R43
C31
C25
C28
C27
C8
C6
C43
R59 C59
R2
R17
R19
R21
R23
R32
R29
C32
C29
C23
C21
C19
C17
C2
R50 C50
C30R30
C26
C46
R44 C44
C7
C5
C4R4
R5
R7
R46
R26
WP
-CD1
A0
A2
A4
A6
A12
A16
-WE
A13
-CD2
D2
D0
A1
A3
A5
A7
A15
RDY
A14
A8
A11
A10
D7
D5
-CD1D3
D4
D6
-OE
-CE1
A9
CD2
CD1
SW1
Figure 2.4-1 TerFigure 2.4-1 Termination Area - Component Sidemination Area - Component Side
BLACKBERRY Ex. 1004, page 6
PCCextend 100 User’s Manual Page 5
M200001-00 1994-95 Sycard Technology
C10 R10
R58C58
C56
R54C54
C52
R41
R38C38
C39
R52
R56
C11 R11
R9
C57 R57
R55
R53
R40
R39
R37
R35
R33
R48
R45
R15
R13C13
C15
C45
C48
C33
C37
C41
C40
C53
C55
C9
C35
C36 R36
C12
C14
R12
R14
C16
C47
C49
C34
R16
R34
R47
R49
D9
BVD1
-REG
-WAIT
-VS2
A23
A25
RESET
-INPACK
BVD2
D8
D10
A24
A22
A20
A18
-IOWR
-VS1
D15
D13
D11
A21
A19
A17
-IORD
-CE2
D14
D12
Figure 2.4-2 Termination Area - Solder SideFigure 2.4-2 Termination Area - Solder Side
2.5 PCCextend Current Protection Device2.5 PCCextend Current Protection Device
A resettable fuse protects the host from excessive current consumption from the card. Located at R61, the,
PolySwitch resettable fuse provides low resistance operation up to 900mA. The PolySwitch fuse may be by passed
by soldering a shorting wire across JP4.
BLACKBERRY Ex. 1004, page 7
Page 6PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
AppendixAppendix
A. PC Card 68-Pin InterfaceA. PC Card 68-Pin Interface
PC Card Pinout - Memory ModePC Card Pinout - Memory Mode
PinPin NameName DescriptionDescription PinPin NameName DescriptionDescription
1GND Ground 35 GND Ground
2D3 Data Bit 3 36 CD1# Card Detect 1
3D4 Data Bit 4 37 D11 Data Bit 11
4D5 Data Bit 5 38 D12 Data Bit 12
5D6 Data Bit 6 39 D13 Data Bit 13
6D7 Data Bit 7 40 D14 Data Bit 14
7CE1# Card Enable 1 41 D15 Data Bit 15
8A10 Address Bit 10 42 CE2# Card Enable 2
9OE# Output Enable 43 VS1# Voltage Sense 1
10 A11 Address Bit 11 44 RFU Reserved
11 A9 Address Bit 9 45 RFU Reserved
12 A8 Address Bit 8 46 A17 Address Bit 17
13 A13 Address Bit 13 47 A18 Address Bit 18
14 A14 Address Bit 14 48 A19 Address Bit 19
15 WE# Write Enable 49 A20 Address Bit 20
16 READY Ready/Busy 50 A21 Address Bit 21
17 VCC Card Power 51 VCC Card Power
18 VPP1 Programming Supply
Voltage 1 52 VPP2 Programming Supply
Voltage 2
19 A16 Address Bit 16 53 A22 Address Bit 22
20 A15 Address Bit 15 54 A23 Address Bit 23
21 A12 Address Bit 12 55 A24 Address Bit 24
22 A7 Address Bit 7 56 A25 Address Bit 25
23 A6 Address Bit 6 57 VS2# Voltage Sense 2
24 A5 Address Bit 5 58 RESET Card Reset
25 A4 Address Bit 4 59 WAIT# Extend Bus Cycle
26 A3 Address Bit 3 60 RFU Reserved
27 A2 Address Bit 2 61 REG# Register Select
28 A1 Address Bit 1 62 BVD2 Battery Voltage Detect
2
29 A0 Address Bit 0 63 BVD1 Battery Voltage Detect
1
30 D0 Data Bit 0 64 D8 Data Bit 8
31 D1 Data Bit 1 65 D9 Data Bit 9
32 D2 Data Bit 2 66 D10 Data Bit 10
33 WP Write Protect 67 CD2# Card Detect 2
34 GND Ground 68 GND Ground
BLACKBERRY Ex. 1004, page 8
PCCextend 100 User’s Manual Page 7
M200001-00 1994-95 Sycard Technology
PC Card Pinout - I/O Mode
PinPin NameName DescriptionDescription PinPin NameName DescriptionDescription
1GND Ground 35 GND Ground
2D3 Data Bit 3 36 CD1# Card Detect 1
3D4 Data Bit 4 37 D11 Data Bit 11
4D5 Data Bit 5 38 D12 Data Bit 12
5D6 Data Bit 6 39 D13 Data Bit 13
6D7 Data Bit 7 40 D14 Data Bit 14
7CE1# Card Enable 1 41 D15 Data Bit 15
8A10 Address Bit 10 42 CE2# Card Enable 2
9OE# Output Enable 43 VS1# Voltage Sense 1
10 A11 Address Bit 11 44 IORD# I/O Read Strobe
11 A9 Address Bit 9 45 IOWR# I/O Write Strobe
12 A8 Address Bit 8 46 A17 Address Bit 17
13 A13 Address Bit 13 47 A18 Address Bit 18
14 A14 Address Bit 14 48 A19 Address Bit 19
15 WE# Write Enable 49 A20 Address Bit 20
16 IREQ# Interrupt Request 50 A21 Address Bit 21
17 VCC Card Power 51 VCC Card Power
18 VPP1 Programming Supply
Voltage 1 52 VPP2 Programming Supply
Voltage 2
19 A16 Address Bit 16 53 A22 Address Bit 22
20 A15 Address Bit 15 54 A23 Address Bit 23
21 A12 Address Bit 12 55 A24 Address Bit 24
22 A7 Address Bit 7 56 A25 Address Bit 25
23 A6 Address Bit 6 57 VS2# Voltage Sense 2
24 A5 Address Bit 5 58 RESET Card Reset
25 A4 Address Bit 4 59 WAIT# Extend Bus Cycle
26 A3 Address Bit 3 60 INPACK# Input Port Acknowledge
27 A2 Address Bit 2 61 REG# Register and I/O select
enable
28 A1 Address Bit 1 62 SPKR# Digital Audio
Waveform
29 A0 Address Bit 0 63 STSCHG# Card Status Changed
30 D0 Data Bit 0 64 D8 Data Bit 8
31 D1 Data Bit 1 65 D9 Data Bit 9
32 D2 Data Bit 2 66 D10 Data Bit 10
33 IOIS16# IO Port is 16 bits 67 CD2# Card Detect 2
34 GND Ground 68 GND Ground
BLACKBERRY Ex. 1004, page 9
Page 8PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
SurfaceA
SurfaceB
Pin1
Pin35
Pin34
Pin68
68 pinCardSideConnector-5Volt
68 pinSocket-5Volt(Systemside)
Pin35 Pin68
Pin1Pin34
Front view
Right angle connector hole pattern - Top side
#1
#2
#35 #36
#33#34
#67
#68
INSERTCARD
Right angle connector hole pattern - Bottom Side
#1
#2
#35
#36
#33
#34
#67
#68
INSERTCARD
BLACKBERRY Ex. 1004, page 10
PCCextend 100 User’s Manual Page 9
M200001-00 1994-95 Sycard Technology
B. PC Card Timing ReferenceB. PC Card Timing Reference
B.1 I/O Read TimingB.1 I/O Read Timing
T100 T102
T101
T109
T108
T103
T110
T112
T105
T106
T107
T114
T111
REG#
Dout
T113
A[25:0]
CE[1:0]#
IORD#
INPACK#
IOIS16#
WAIT#
T104 T115
I/O Read TimingI/O Read Timing
RefRef SymbolSymbol DescriptionDescription MinMin MaxMax
T100 tsuREG REG# setup to IORD# 5ns
T101 thA Address hold after IORD# de-asserted 20ns
T102 thREG REG# hold after IORD# de-asserted 0ns
T103 tsuCE CE# to IORD# setup time 5ns
T104 tsuA (IORD) Address setup before IORD# 70nS
T105 twIORD IORD# strobe width 165ns
T106 tdfINPACK INPACK# delay from IORD# active 0ns 45ns
T107 tdrINPACK INPACK# delay from IORD# inactive 45ns
T108 tdfIOIS16 IOIS16# delay from Address valid 35ns
T109 td (IORD) Data Valid after IORD# 100ns
T110 tdWT IORD# to WAIT# delay 35ns
T111 tw WAIT# width 12us
T112 td (WT) Data Valid after WAIT# inactive 0ns
T113 th (IORD) Data hold after IORD# de-asserted 0ns
T114 tdrIOIS16
(ADR) IOIS16# delay from address invalid 35ns
T115 thCE CE# hold after IORD# inactive 20ns
BLACKBERRY Ex. 1004, page 11
Page 10 PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
B.2 I/O Write TimingB.2 I/O Write Timing
T100 T102
T101
T109
T108
T103
T110
T112
T105
T114
T111
REG#
Din
T113
A[25:0]
CE[1:0]#
IOWR#
IOIS16#
WAIT#
T104
T115
I/O Write TimingI/O Write Timing
RefRef SymbolSymbol DescriptionDescription MinMin MaxMax
T100 tsuREG (IOWR) REG# setup to IOWR# 5ns
T101 thA (IOWR) Address hold after IOWR# de-asserted 20ns
T102 thREG (IOWR) REG# hold after IOWR# de-asserted 0ns
T103 tsuCE (IOWR) CE# to IOWR# setup time 5ns
T104 tsuA (IOWR) Address setup before IOWR# 70nS
T105 twIOWR IOWR# strobe width 165ns
T108 tdfIOIS16 IOIS16# delay from Address valid 35ns
T109 tsu (IOWR) Data Setup before IOWR# 60ns
T110 tdWT (IOWR) IOWR# to WAIT# delay 35ns
T111 tw WT WAIT# width 12us
T112 tdr IOWR (WT) WAIT# deasserted to IOWR# deasserted 0ns
T113 th (IOWR) Data hold after IOWR# de-asserted 30ns
T114 tdrIOIS16
(ADR) IOIS16# delay from address invalid 35ns
T115 thCE(IOWR) CE# hold after IOWR# de-asserted 20ns
BLACKBERRY Ex. 1004, page 12
PCCextend 100 User’s Manual Page 11
M200001-00 1994-95 Sycard Technology
B.3 Memory Read TimingB.3 Memory Read Timing
T100
T102
T101
T106 T107
Din
A[25:0], REG#
CE[1:0]#
WAIT#
OE#
T105
T108
T103
T104
T111
T109 T110
T114
T115
T112
Memory Read TimingMemory Read Timing
RefRef SymbolSymbol DescriptionDescription 600ns600ns 250ns250ns
MinMin MaxMax MinMin MaxMax
T100 tcR Read Cycle Time 600ns 250ns
T101 ta(A) Address access time 600ns 250ns
T102 th (A) Address hold time 35ns 20ns
T103 ta (CE) CE# access time 600ns 250ns
T104 ta (OE) OE# access time 300ns 125ns
T105 tsu (A) Address setup time 100ns 30ns
T106 tv (WT-OE) WAIT# Valid from OE# 100ns 35ns
T107 tw (WT) WAIT# Pulse width 12us 12us
T109 ten (OE) Output enable time from OE# 5ns 5ns
T110 tv (WT) Data setup for WAIT# released 0ns 0ns
T111 tdis (OE) Output disable inactive to data float 150ns 100ns
T112 ten(CE) Output enable time from CE# 5ns 5ns
T114 tsu(CE) CE# setup time 0ns 0ns
T115 th(CE) CE# hold after OE# inactive 35ns 20ns
NoteNote: All timing for 250ns accesses to common memory. 600ns cycle times apply for 3.3V operation.
BLACKBERRY Ex. 1004, page 13
Page 12 PCCextend 100 User’s Manual
1994-95 Sycard Technology M200001-00
B.4 Memory Write TimingB.4 Memory Write Timing
T100
T102
T101
T109T108
T103
T110
T112
T106
Din
T113
A[25:0], REG#
CE[1:0]#
WAIT#
T104
OE#
WE#
T105
T107
T111
Dout
T114
T115
T116
T118
T117
Memory WriteMemory Write TimingTiming
RefRef SymbolSymbol DescriptionDescription 600ns600ns 250ns250ns
MinMin MaxMax MinMin MaxMax
T100 tcW Write cycle time 600ns 250ns
T101 tsu(CE - WEH) CE# active to WE# high 300ns 180ns
T102 tsu(A-WEH) Address valid to WE# high 350ns 180ns
T103 trc(WE) Write recover time 70ns 30ns
T104 tsu(OE-WE) Output enable setup OE# to WE# 35ns 10ns
T105 th(CE) CE# hold time 35ns 20ns
T106 tw(WE) WE# pulse width 300ns 150ns
T107 tsu(A) Address setup time 50ns 30ns
T108 tv(WT-WE) WAIT# valid from WE# active 100ns 35ns
T109 tw(WT) WAIT# pluse width 12us 12us
T110 tv(WT) WE# high from WAIT# inactive 0ns 0ns
T111 tsu(D-WEH) Data setup time 150ns 80ns
T112 th(D) Data hold time 70ns 30ns
T113 tdis(OE) Output disable time from OE# inactive 150ns 100ns
T114 ten(OE) Output enable time from OE# active 5ns 5ns
T115 ten(WE) Output enable time from WE# inactive 5ns 5ns
T116 tdis(WE) Output disable from WE# active 150ns 100ns
T117 tsu(CE) CE# setup time 0ns 0ns
T118 th(OE-WE) Output enable hold from WE# 35ns 10ns
NoteNote: All timing for 250ns speed version. 600ns cycle times apply for 3.3V operation. See PC Card
Standard for other speed versions.
BLACKBERRY Ex. 1004, page 14
PCCextend 100 User’s Manual Page 13
M200001-00 1994-95 Sycard Technology
C. PCCextend 100 SchematicC. PCCextend 100 Schematic
BLACKBERRY Ex. 1004, page 15
Date: April 4, 1995 Sheet 1 of 4
Size Document Number REV
B 140002 A
Title PCCextend 100 - Host Connector
Sycard Technology
1
2
3
CD1
HEADER 3
SW1
PUSHBUTTON
CD[0..15] CD[0..15]
GND
1
D3
2
D4
3
D5
4
D6
5
D7
6
CE1
7
A10
8
OE
9
A11
10
A9
11
A8
12
A13
13
A14
14
WE/PGM
15
RDY/BSY
16
VCCX
17
VPP1
18
A16
19
A15
20
A12
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
A0
29
D0
30
D1
31
D2
32
WP
33
GND
34
GND 35
CD1 36
D11 37
D12 38
D13 39
D14 40
D15 41
CE2 42
RFSH 43
IORD 44
IOWR 45
A17 46
A18 47
A19 48
A20 49
A21 50
VCCX 51
VPP2 52
A22 53
A23 54
A24 55
A25 56
RFU 57
RESET 58
WAIT 59
INPACK 60
REG 61
BVD2 62
BVD1 63
D8 64
D9 65
D10 66
CD2 67
GND 68
P1
PCMCIA
1
2
3
CD2
HEADER 3
*CD1 CD1
WP
CA0
CA2
CA4
CA6
CA12
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
J1
2 X 17
CD2
CD0
CA1
CA3
CA5
CA7
CA15
VPP1
RDY/*BSY
CA14
CA8
CA11
CA10
CD7
CD5
CD3
CA16
CA13
CA9
*OE
*CE1
CD6
CD4
*WE/*PGM
VCC
*CD2
*CE2
*IORD
*IOWR
VS1
CD11
CD12
CD13
CD14
CD15 *CE2
*IORD
*IOWR
CA17
VS1
*CD1P
CA10
CA11
CA9
CA8
CD3
CD4
CD5
CD6
CD7
*CE1
*OE
*CE1
*OE
VPP1
*WE/*PGM
RDY/*BSY
VPP1
*WE/*PGM
RDY/*BSY
VCC
CA13
CA14
CA16
CA15
CA12
CA7
CA6
CA5
CA18
CA19
CA20
CA21
CA22
CA23
CA24
CA25
VS2
VPP2
CRESET
VPP2
CRESET
VCC
*CD2
CD9
BVD1
*REG
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
J2
2 X 17
CD10
CD8
BVD2
CD14
*CE2
*IORD
*INPACK
CA25
CA23
VPP2
CA21
CA19
CA17
CRESET
*IOWR
CD13
CD15
VS1
*WAIT
VS2
CA22
CA18
CA20
CA24
VCC
*WAIT
BVD2
BVD1
*REG
*INPACK
*WAIT
*REG
BVD2
BVD1
*INPACK
*CD2P
CD8
CD9
CD10
CA4
CA3
CA2
CA1
CA0
CD0
CD1
CD2
WP WP
CA[0..25] CA[0..25]
VS2
VS2 CD11 CD12
*CD1
HOST SIDE CONNECTOR
FILE=PCCEXT1.S31
BLACKBERRY Ex. 1004, page 16
Date: April 4, 1995 Sheet 2 of 4
Size Document Number REV
B 140002 A
Title
PCCextend 100 - Data/Address Filters
Sycard Technology
CAF[0..25]
C32 CAP
CAF16
CAF[0..25]
R32
0 OHM
CA16
C17 CAP
CAF0
R17
0 OHM
R18
0 OHM
CDF[0..15]
CA0
C1 CAP
C2 CAP
CDF0
CDF1
CDF[0..15]
R1
0 OHM
R2
0 OHM
CD0
CD1
CD[0..15] CD[0..15]
R3
0 OHM
R4
0 OHM
R5
0 OHM
CD2
CD3 C3 CAP
C4 CAP
CDF2
CDF3
R19
0 OHM
R20
0 OHM
CA1
CA2
CA3
C18 CAP
C19 CAP
C20 CAP
CAF1
CAF2
CAF3
R33
0 OHM
R34
0 OHM
R35
0 OHM
CA17
CA18
CA19
C33 CAP
C34 CAP
CAF17
CAF18
CAF19
C35 CAP
C36 CAP
C37 CAP
CAF20
CAF21
R36
0 OHM
R37
0 OHM
CA20
CA21
C21 CAP
C22 CAP
CAF4
CAF5
R21
0 OHM
R22
0 OHM
CA4
CA5
C5 CAP
C6 CAP
C7 CAP
CDF4
CDF5
CDF6
R6
0 OHM
R7
0 OHM
CD4
CD5
CD6
R8
0 OHM
R9
0 OHM
CD7
CD8 C8 CAP
C9 CAP
CDF7
CDF8
R23
0 OHM
R24
0 OHM
R25
0 OHM
CA6
CA7
CA8
C23 CAP
CAF6
CAF7
CAF8
C24 CAP
R38
0 OHM
R39
0 OHM
R41
0 OHM
CA22
CA23 C38 CAP
C41 CAP
CAF22
CAF23
C39 CAP
C40 CAP
CAF24
CAF25
R40
0 OHM
CA25
CA24
CAF9
CAF10
C25 CAP
C26 CAP
C27 CAP
R26
0 OHM
R27
0 OHM
CA9
CA10
C10 CAP
C11 CAP
CDF9
CDF10
R10
0 OHM
R11
0 OHM
R12
0 OHM
CD9
CD10
R13
0 OHM
R14
0 OHM
CD11
CD12
CD13
C12 CAP
C13 CAP
C14 CAP
CDF11
CDF12
CDF13
R28
0 OHM
R29
0 OHM
CA11
CA12
C29 CAP
CAF11
CAF12
C28 CAP
C30 CAP
C31 CAP
CAF13
CAF14
CAF15
R30
0 OHM
R31
0 OHM
R42
0 OHM
CA13
CA14
CA15
C15 CAP
C16 CAP
CDF14
CDF15
R15
0 OHM
R16
0 OHM
CD14
CD15
FILE=PCCEXT2.S31
CA[0..25] CA[0..25] C42 CAP
BLACKBERRY Ex. 1004, page 17
Date: January 11, 1995 Sheet 3 of 4
Size Document Number REV
B 140002 A
Title PCCextend 100 - SIGNAL FILTERS
Sycard Technology
C43 CAP
C44 CAP
*CD1F
*CE1F
*CD1F
*CE1F
R43
0 OHM
R44
0 OHM
*CD1
*CE1
*CD1
*CE1
*CE2
*OE
*CE2
*OE
R45
0 OHM
R46
0 OHM
R47
0 OHM
C45 CAP
C46 CAP
*CE2F
*OEF
*CE2F
*OEF
C47 CAP
C48 CAP
C49 CAP
VS1F
*IORDF
*IOWRF
VS1F
*IORDF
*IOWRF
R48
0 OHM
R49
0 OHM
*IORD
*VS1
*IOWR
VS1
*IORD
*IOWR
*WE/*PGM
RDY/*BSY
*WE/*PGM
RDY/*BSY
R50
0 OHM
R51
0 OHM
C50 CAP
C51 CAP
*WE/*PGMF
RDY/*BSYF
*WE/*PGMF
RDY/*BSYF
C52 CAP
C53 CAP
VS2F
RESETF
VS2F
RESETF
R52
0 OHM
R53
0 OHM
R54
0 OHM
VS2
CRESET
VS2
CRESET
*WAIT
*INPACK
*REG
*WAIT
*INPACK
*REG
R55
0 OHM
R56
0 OHM
C54 CAP
C55 CAP
C56 CAP
*WAITF
*INPACKF
*REGF
*WAITF
*INPACKF
*REGF
C57 CAP
C58 CAP
BVD2F
BVD1F
BVD2F
BVD1F
R57
0 OHM
R58
0 OHM
BVD2
BVD1
BVD2
BVD1
FILE=PCCEXT3.S31
*CD2
WP WP
*CD2
R59
0 OHM
R60
0 OHM
C59 CAP
C60 CAP
WPF
*CD2F
WPF
*CD2F
BLACKBERRY Ex. 1004, page 18
Date: April 6, 1995 Sheet 4 of 4
Size Document Number REV
B 140002 A
Title PCCextend 100 - Card Connector
Sycard Technology
*CD1F
*CD1F
5V LED
D1
LED
D2
3.3V ZENER
R62
100 ohm
R61
VARISTOR
JP4
JUMPER
VCC
R63
220 ohm POWER LED
D3
LED
JP3
JUMPER
CDF[0..15]
VCC2
CDF[0..15]
GND
1
D3
2
D4
3
D5
4
D6
5
D7
6
CE1
7
A10
8
OE
9
A11
10
A9
11
A8
12
A13
13
A14
14
WE/PGM
15
RDY/BSY
16
VCCX
17
VPP1
18
A16
19
A15
20
A12
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
A0
29
D0
30
D1
31
D2
32
WP
33
GND
34
GND 35
CD1 36
D11 37
D12 38
D13 39
D14 40
D15 41
CE2 42
RFSH 43
IORD 44
IOWR 45
A17 46
A18 47
A19 48
A20 49
A21 50
VCCX 51
VPP2 52
A22 53
A23 54
A24 55
A25 56
RFU 57
RESET 58
WAIT 59
INPACK 60
REG 61
BVD2 62
BVD1 63
D8 64
D9 65
D10 66
CD2 67
GND 68
J3
PCMCIA
CDF3 *CD1F
*CE2F
VS1F
*IORDF
*IOWRF
*CE2F
*IORDF
*IOWRF
VS1F
CDF11
CDF12
CDF13
CDF14
CDF15
CAF17
CAF18
CAF19
CDF4
CDF5
CDF6
CDF7
CAF10
CAF11
CAF9
CAF8
CAF13
CAF14
*CE1F
*OEF
C63
10uF
C64
0.1uF
*CE1F
*OEF
C65
0.1uF
JP5
JUMPER
JP6
JUMPER
VPP1
VPP2
VPP1
VPP2
JP1
JUMPER
JP2
JUMPER
VPP2A C61
0.1uF
*WE/*PGMF
RDY/*BSYF
VCC2 *WE/*PGMF
RDY/*BSYF
VPP1A CAF16
CAF15
CAF12
CAF7
CAF6
CAF5
CAF4
CAF3
CAF20
CAF21
CAF22
CAF23
CAF24
CAF25
VS2F
*WAITF
*INPACKF
RESETF
*WAITF
*INPACKF
RESETF
VPP2A
VCC2
*REGF
BVD2F
BVD1F
*CD2F
VS2F
*CD2F
VS2F
*REGF
BVD2F
BVD1F
CDF8
CDF9
CDF10
CAF2
CAF1
CAF0
CDF0
CDF1
CDF2
WPF WPF
C62
0.1uF
CAF[0..25] CAF[0..25]
SOCKET SIDE CONNECTOR
FILE=PCCEXT4.S31
BLACKBERRY Ex. 1004, page 19
Table of contents
