Xilinx Virtex-4 QV FPGA User manual

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Virtex-4 QV
FPGA Ceramic
Packaging and
[Guide Subtitle]
[optional]
UG496 (v1.1) June 8, 2012 [optional]
Virtex-4 QV FPGA
Ceramic Packaging and
Pinout Specifications
UG496 (v1.1) June 8, 2012

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
04/02/08 1.0 Initial Xilinx release.
06/08/12 1.1 Added Chapter 6, “Guidelines for Xilinx CF Package Handling and Assembly.”
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 1: Device Packaging Overview
Device/Package Combinations and Available I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 2: Pinout Tables
CF1140 (SX55) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . . 15
CF1144 (FX60) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . . 47
CF1509 (FX140) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . . 79
CF1509 (LX200) Ceramic Flip-Chip Column Grid Package . . . . . . . . . . . . . . . . . . . 120
Chapter 3: Pinout Diagrams
CF1140 Package Pinout Diagram (SX55). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
CF1140 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 163
CF1144 Package Pinout Diagram (FX60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
CF1144 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 165
CF1509 Package Pinout Diagram (LX200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CF1509 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 167
CF1509 Package Pinout Diagram (FX140). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
CF1509 Color-Coded SelectIO Interface and Bank Information . . . . . . . . . . . . . . 169
Chapter 4: Mechanical Drawings
CF1140 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 172
CF1144 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 173
CF1509 Ceramic Flip-Chip Column Grid Package Specifications . . . . . . . . . . . . 174
Chapter 5: Thermal Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CF Package Construction and Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Thermal Resistance and Package Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table of Contents

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Chapter 6: Guidelines for Xilinx CF Package Handling and Assembly
Product Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Product Handling and Inspection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Board Level Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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Preface
About This Guide
This guide provides complete packing information for Virtex®-4 QPro™-V (QV)
Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF)
packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-
chip column grid array (CF) packages that are optimally designed for improved thermal
cycle reliability.
Guide Contents
This manual contains the following chapters:
•Chapter 1, “Device Packaging Overview,” provides an introduction to the Virtex-4 QV
family with a summary of maximum I/Os available in each device/package
combination. Also includes table of pin definitions.
•Chapter 2, “Pinout Tables,” provides pinout information for all Virtex-4 QV
Radiation-Hardened FPGAs.
•Chapter 3, “Pinout Diagrams,” provides pinout diagrams for all Virtex-4 QV
Radiation-Hardened package/device combinations.
•Chapter 4, “Mechanical Drawings,” provides mechanical drawings of all Virtex-4 QV
Radiation-Hardened FPGAs.
•Chapter 5, “Thermal Specifications,” provides thermal data associated with Virtex-4
QV Radiation-Hardened FPGA packaging. Discusses Virtex-4 QV FPGA power
management strategy and thermal management options.
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.

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Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold Literal commands that you enter
in a syntactical statement ngdbuild design_name
Helvetica bold
Commands that you select from
a menu File ∅Open
Keyboard shortcuts Ctrl+C
Italic font
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Square brackets [ ]
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [option_name]
design_name
Braces { } A list of items from which you
must choose one or more lowpwr ={on|off}
Vertical bar | Separates items in a list of
choices lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Repetitive material that has
been omitted
allow block block_name loc1
loc2 ... locn;

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Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text Cross-reference link to a location
in the current document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text Cross-reference link to a location
in another document
See Figure 2-5 in the Virtex-II
Platform FPGA User Guide.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.

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Chapter 1
Device Packaging Overview
This section describes the pinouts for Virtex-4 QV Radiation Hardened FPGAs in 1.00-mm
pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened
FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are
optimally designed for improved thermal cycle reliability. All of these packages are pinout
compatible with a commercial grade equivalent BGA (Table 1-1).
Each device I/O ring is split into eight or more I/O banks to allow for flexibility in the
choice of I/O standards (see UG070,Virtex-4 User Guide). Global pins, including JTAG,
configuration, and power/ground pins, are listed at the end of each table. Table 1-3
provides the definitions for all pin types.
Note: Check www.xilinx.com for the latest pinout information.
Device/Package Combinations and Available I/Os
Table 1-1 lists the available CF packages and their pin compatible flip-chip packages.
Table 1-2 lists the number of available I/Os and differential I/O pairs for each Virtex-4 QV
FPGA. The number of I/Os per package includes all user I/Os except the fifteen control
pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS,
HSWAPEN, DXN, DXP, AND RSVD).
Table 1-1: Ceramic Flip-Chip Packages and Compatible BGA
Ceramic Package CF1140 CF1144 CF1509
Pitch 1.00 mm 1.00 mm 1.00 mm
Size 35 mm ×35 mm 35 mm ×35 mm 40 mm ×40 mm
Compatible BGA
XQR4VSX55 FF1148
XQR4VFX60 FF1152
XQR4VFX140 FF1517
XQR4VLX200 FF1513

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Pin Definitions
Table 1-3 provides a description of each pin type listed in Virtex-4 QV FPGA pinout tables.
The "_#" suffix appended to some pin descriptions indicates the bank in which that pin
resides. Pins without this suffix appended are not associated with any particular bank.
Note: RocketIO™transceivers are not supported for Virtex-4 QV FPGAs.
Table 1-2: Virtex-4 QV FPGA Available I/Os per Device/Package Combination
Virtex-4 QV
Device User and Differential I/Os Virtex-4 QV CF Package
CF1140 CF1144 CF1509
XQR4VSX55 Available User I/Os 640
Differential I/O Pairs 320
XQR4VFX60 Available User I/Os 576
Differential I/O Pairs 288
XQR4VFX140 Available User I/Os 768
Differential I/O Pairs 384
XQR4VLX200 Available User I/Os 960
Differential I/O Pairs 480
Table 1-3: Virtex-4 QPro FPGA Pin Definitions
Pin Name Direction Description
User I/O Pins
IO_LXXY_# Input/Output
All user I/O pins are capable of differential signalling and can implement
LVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is
labeled “IO_LXXY_#”, where:
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y
= [P|N] for the positive/negative sides of the differential pair.
Multi-Function Pins
IO_LXXY_ZZZ_# Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZ represents
one or more of the functions described below.
For a given multi-function pin, ZZZ is one or more of the following:
ADCn Input/Output ADC1 through ADC7 input pins are reserved for future use but can be
used for I/O or other designated functions.
Dn Input/Output In SelectMAP mode, D0 through D31 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.
CC(2) Input/Output
These lower capacitance clock pins connect to Clock Capable I/Os. These
pins do not support LVDS outputs, and they become regular user I/Os
when not needed for clocks.

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GC (2) Input/Output
These lower capacitance clock pins connect to Global Clock Buffers. These
pins do not support LVDS outputs, and they become regular user I/Os when
not needed for clocks. For single-ended clock inputs, use P-side pins only.
LC (2) Input/Output These lower capacitance pins do not support LVDS outputs.
SMn Input/Output SM1 through SM7 input pins are reserved for future use but can be used
for I/O or other designated functions.
VREF Input/Output These are input threshold voltage pins. They become user I/Os when an
external threshold voltage is not needed (per bank).
VRN Input/Output This pin is for the DCI voltage reference resistor of N transistor (per bank,
to be pulled High with reference resistor).
VRP Input/Output This pin is for the DCI voltage reference resistor of P transistor (per bank,
to be pulled Low with reference resistor).
Dedicated Configuration Pins (1)
CCLK_0 Input/Output Configuration clock. Output and input in Master mode or Input in Slave
mode.
CS_B_0 Input In SelectMAP mode, this is the active-low Chip Select signal.
D_IN_0 Input In bit-serial modes, D_IN is the single-data input.
DONE_0 Input/Output
DONE is a bidirectional signal with an optional internal pull-up resistor. As
an output, this pin indicates completion of the configuration process. As an
input, a Low level on DONE can be configured to delay the start-up sequence.
DOUT_BUSY_0 Output
In SelectMAP mode, BUSY controls the rate at which configuration data is
loaded.
In bit-serial modes, DOUT gives preamble and configuration data to
down-stream devices in a daisy chain.
HSWAPEN Input Enable I/O pull-ups during configuration
INIT_B_0 Bidirectional
(open-drain)
When Low, this pin indicates that the configuration memory is being
cleared. When held Low, the start of configuration is delayed. During
configuration, a Low on this output indicates that a configuration data
error has occurred.
M0_0, M1_0, M2_0 Input Configuration mode selection
PROG_B_0 Input Active Low asynchronous reset to configuration logic. This pin has a
permanent weak pull-up resistor.
PWRDWN_B_0 Input
(unsupported)
Active Low power-down pin (unsupported). Driving this pin Low can
adversely affect device operation and configuration. PWRDWN_B is internally
pulled High, which is its default state. It does not require an external pull-up.
Do not connect this pin—leave floating.
RDWR_B_0 Input In SelectMAP mode, this is the active-low Write Enable signal.
TCK_0 Input Boundary-Scan Clock
TDI_0 Input Boundary-Scan Data Input
Table 1-3: Virtex-4 QPro FPGA Pin Definitions (Cont’d)
Pin Name Direction Description

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TDO_0 Output Boundary-Scan Data Output
TMS_0 Input Boundary-Scan Mode Select
TDP_0, TDN_0 N/A Temperature-sensing diode pins (Anode: TDP, Cathode: TDN).
Reserved Pins
AVDD_SM Input This pin is reserved and should be connected to 2.5V (sharing the same
PCB supply distribution as VCCAUX is acceptable).
AVSS_SM Input This pin is reserved for future use and should be connected to GND.
VN_SM Input This pin is reserved for future use and should be connected to GND.
VP_SM Input This pin is reserved for future use and should be connected to GND.
VREFN_SM Input This pin is reserved for future use and should be connected to GND.
VREFP_SM Input This pin is reserved for future use and should be connected to GND.
AVDD_ADC Input This pin is reserved and should be connected to 2.5V (sharing the same
PCB supply distribution as VCCAUX is acceptable).
AVSS_ADC Input This pin is reserved for future use and should be connected to GND.
VN_ADC Input This pin is reserved for future use and should be connected to GND.
VP_ADC Input This pin is reserved for future use and should be connected to GND.
VREFN_ADC Input This pin is reserved for future use and should be connected to GND.
VREFP_ADC Input This pin is reserved for future use and should be connected to GND.
RSVD N/A Reserved pin —do not connect
Other Pins
GND Input Ground.
VBATT_# Input Decryptor key memory backup supply. If unused, this pin should be tied to
VCC or GND.
VCCAUX Input Power-supply pins for auxiliary circuits
VCCINT Input Power-supply pins for the internal core logic
VCCO_# Input Power-supply pins for the output drivers (per bank)
RocketIO Multi-Gigabit Transceiver (MGT) Pins
AVCCAUXRXA_#,
AVCCAUXRXB_# Input Analog power supply for receive circuitry of the RocketIO MGT (1.2V).
AVCCAUXTX_# Input Analog power supply for transmit circuitry of the RocketIO MGT (1.2V).
AVCCAUXMGT_# Input Analog power supply for global bias (2.5V).
GNDA_# Input Ground for the analog circuitry of the RocketIO MGT.
MGTCLK_# Input Differential reference clock for the RocketIO MGT.
Table 1-3: Virtex-4 QPro FPGA Pin Definitions (Cont’d)
Pin Name Direction Description

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RXPPADA_#,
RXPPADB_# Input Positive differential receive port of the RocketIO MGT.
RXNPADA_#,
RXNPADB_# Input Negative differential receive port of the RocketIO MGT.
TXPPADA_#,
TXPPADB_# Output Positive differential transmit port of the RocketIO MGT.
TXNPADA_#,
TXNPADB_# Output Negative differential transmit port of the RocketIO MGT.
VTRXA_#,
VTRXB_# Input Receive termination supply for the RocketIO MGT (0V - 2.5V).
VTTXA_#,
VTTXB_# Input Transmit termination supply for the RocketIO MGT (1.2V - 1.5V).
Notes:
1. All dedicated pins (JTAG and configuration) are powered by VCC_CONFIG.
2. For more information on lower capacitance pins, see the UG070, Virtex-4 User Guide.
3. For more information on RocketIO pins, see the UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide.
Table 1-3: Virtex-4 QPro FPGA Pin Definitions (Cont’d)
Pin Name Direction Description

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Chapter 2
Pinout Tables
This chapter provides pinout information for the following packages:
•CF1140 (SX55) Ceramic Flip-Chip Column Grid Package (for XQR4VSX55 only)
•CF1144 (FX60) Ceramic Flip-Chip Column Grid Package (for XQR4VFX60 only)
•CF1509 (FX140) Ceramic Flip-Chip Column Grid Package (for XQR4VFX140 only)
•CF1509 (FX140) Ceramic Flip-Chip Column Grid Package (for XQR4VLX200 only)
Note: Check www.xilinx.com for the latest pinout information. ASCII package pinout files are also
available for download from the Xilinx website.
CF1140 (SX55) Ceramic Flip-Chip Column Grid Package
As shown in Table 2-1, the Virtex-4 QV XQR4VSX55 FPGA is available in the CF1140
ceramic flip-chip column grid package. The "No Connect" column in Table 2-1 lists pins not
available for this footprint.
Table 2-1: CF1140 Package Pinout (SX55)
Bank Pin Description Pin
Number No Connects
0 HSWAPEN_0T18
0 CCLK_0R17
0 D_IN_0T16
0 PROG_B_0 U22
0 INIT_B_0 U21
0 CS_B_0 U17
0 DONE_0U15
0 RDWR_B_0 U13
0 VBATT_0 V22
0 M2_0 V20
0 PWRDWN_B_0 W21
0 TMS_0V13
0 M0_0 W20
0 TDO_0V18
0 TCK_0V14
0 M1_0 W19
0 DOUT_BUSY_0 Y18

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0 TDI_0 W17
0 TDN_0 F15
0 TDP_0 D15
1 IO_L1P_D31_LC_1 N19
1 IO_L1N_D30_LC_1 N18
1 IO_L2P_D29_LC_1 L15
1 IO_L2N_D28_LC_1 L14
1 IO_L3P_D27_LC_1 E21
1 IO_L3N_D26_LC_1 D21
1 IO_L4P_D25_LC_1 J14
1 IO_L4N_D24_VREF_LC_1 K14
1 IO_L5P_D23_LC_1 N20
1 IO_L5N_D22_LC_1 M20
1 IO_L6P_D21_LC_1 H14
1 IO_L6N_D20_LC_1 H13
1 IO_L7P_D19_LC_1 H22
1 IO_L7N_D18_LC_1 J21
1 IO_L8P_D17_CC_LC_1 F13
1 IO_L8N_D16_CC_LC_1 G13
1 IO_L9P_GC_LC_1 M18
1 IO_L9N_GC_LC_1 L18
1 IO_L10P_GC_LC_1 M17
1 IO_L10N_GC_LC_1 N17
1 IO_L11P_GC_LC_1E19
1 IO_L11N_GC_LC_1D19
1 IO_L12P_GC_LC_1 C17
1 IO_L12N_GC_VREF_LC_1 D17
1 IO_L13P_GC_LC_1 C19
1 IO_L13N_GC_LC_1 C18
1 IO_L14P_GC_LC_1 D16
1 IO_L14N_GC_LC_1 C15
1 IO_L15P_GC_LC_1 D20
1 IO_L15N_GC_LC_1 C20
1 IO_L16P_GC_CC_LC_1 M16
1 IO_L16N_GC_CC_LC_1 N15
1 IO_L17P_CC_LC_1 B20
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description Pin
Number No Connects

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1 IO_L17N_CC_LC_1 A20
1 IO_L18P_VRN_LC_1 K16
1 IO_L18N_VRP_LC_1 L16
1 IO_L19P_LC_1 J20
1 IO_L19N_LC_1 L19
1 IO_L20P_LC_1 H15
1 IO_L20N_VREF_LC_1 J15
1 IO_L21P_LC_1 G21
1 IO_L21N_LC_1 H20
1 IO_L22P_LC_1 G15
1 IO_L22N_LC_1 F14
1 IO_L23P_LC_1 F21
1 IO_L23N_LC_1 F20
1 IO_L24P_LC_1 A15
1 IO_L24N_LC_1 B15
2 IO_L1P_D15_CC_LC_2 AJ22
2 IO_L1N_D14_CC_LC_2 AJ21
2 IO_L2P_D13_LC_2 AC15
2 IO_L2N_D12_LC_2 AB15
2 IO_L3P_D11_LC_2 AG22
2 IO_L3N_D10_LC_2 AH22
2 IO_L4P_D9_LC_2 AL14
2 IO_L4N_D8_VREF_LC_2 AK14
2 IO_L5P_D7_LC_2 AG21
2 IO_L5N_D6_LC_2 AF20
2 IO_L6P_D5_LC_2 AF14
2 IO_L6N_D4_LC_2 AG13
2 IO_L7P_D3_LC_2 AE21
2 IO_L7N_D2_LC_2 AF21
2 IO_L8P_D1_LC_2 AP15
2 IO_L8N_D0_LC_2 AN15
2 IO_L9P_GC_CC_LC_2 AC19
2 IO_L9N_GC_CC_LC_2 AB18
2 IO_L10P_GC_LC_2 AD16
2 IO_L10N_GC_LC_2 AF15
2 IO_L11P_GC_LC_2 AN20
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description Pin
Number No Connects

18 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
2 IO_L11N_GC_LC_2 AP20
2 IO_L12P_GC_LC_2 AD17
2 IO_L12N_GC_VREF_LC_2 AC17
2 IO_L13P_GC_LC_2 AM20
2 IO_L13N_GC_LC_2 AL19
2 IO_L14P_GC_LC_2 AB17
2 IO_L14N_GC_LC_2 AB16
2 IO_L15P_GC_LC_2 AL18
2 IO_L15N_GC_LC_2 AM18
2 IO_L16P_GC_LC_2 AM17
2 IO_L16N_GC_LC_2 AM16
2 IO_L17P_LC_2 AD21
2 IO_L17N_LC_2 AD20
2 IO_L18P_LC_2 AM15
2 IO_L18N_LC_2 AL15
2 IO_L19P_LC_2 AJ20
2 IO_L19N_LC_2 AL20
2 IO_L20P_LC_2 AJ15
2 IO_L20N_VREF_LC_2 AJ14
2 IO_L21P_LC_2 AG20
2 IO_L21N_LC_2 AH20
2 IO_L22P_LC_2 AG15
2 IO_L22N_LC_2 AH14
2 IO_L23P_VRN_LC_2 AD19
2 IO_L23N_VRP_LC_2 AE19
2 IO_L24P_CC_LC_2 AL16
2 IO_L24N_CC_LC_2 AK16
3 IO_L1P_GC_CC_LC_3 F18
3 IO_L1N_GC_CC_LC_3 G18
3 IO_L2P_GC_VRN_LC_3 H17
3 IO_L2N_GC_VRP_LC_3 J17
3 IO_L3P_GC_LC_3 H19
3 IO_L3N_GC_LC_3 H18
3 IO_L4P_GC_LC_3 E18
3 IO_L4N_GC_VREF_LC_3 E17
3 IO_L5P_GC_LC_3 K18
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description Pin
Number No Connects

Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com 19
UG496 (v1.1) June 8, 2012
CF1140 (SX55) Ceramic Flip-Chip Column Grid Package
R
3 IO_L5N_GC_LC_3 K17
3 IO_L6P_GC_LC_3 E16
3 IO_L6N_GC_LC_3 F16
3 IO_L7P_GC_LC_3 K19
3 IO_L7N_GC_LC_3 J19
3 IO_L8P_GC_LC_3 G17
3 IO_L8N_GC_LC_3 G16
4 IO_L1P_GC_LC_4 AF18
4 IO_L1N_GC_LC_4 AE18
4 IO_L2P_GC_LC_4 AG16
4 IO_L2N_GC_LC_4 AF16
4 IO_L3P_GC_LC_4 AH19
4 IO_L3N_GC_LC_4 AH18
4 IO_L4P_GC_LC_4 AK18
4 IO_L4N_GC_VREF_LC_4 AK17
4 IO_L5P_GC_LC_4 AG18
4 IO_L5N_GC_LC_4 AG17
4 IO_L6P_GC_LC_4 AE17
4 IO_L6N_GC_LC_4 AE16
4 IO_L7P_GC_VRN_LC_4 AJ19
4 IO_L7N_GC_VRP_LC_4 AK19
4 IO_L8P_GC_CC_LC_4 AJ17
4 IO_L8N_GC_CC_LC_4 AH17
5 IO_L1P_ADC7_5 B23
5 IO_L1N_ADC7_5 A23
5 IO_L2P_ADC6_5 A26
5 IO_L2N_ADC6_5 B26
5 IO_L3P_ADC5_5 A24
5 IO_L3N_ADC5_5 A25
5 IO_L4P_5 G25
5 IO_L4N_VREF_5 H25
5 IO_L5P_ADC4_5 C23
5 IO_L5N_ADC4_5 C24
5 IO_L6P_ADC3_5 F25
5 IO_L6N_ADC3_5 F26
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description Pin
Number No Connects

20 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
Chapter 2: Pinout Tables
R
5 IO_L7P_ADC2_5 D24
5 IO_L7N_ADC2_5 D25
5 IO_L8P_CC_ADC1_LC_5 B27
5 IO_L8N_CC_ADC1_LC_5 C27
5 IO_L17P_5 C22
5 IO_L17N_5 B22
5 IO_L18P_5 A30
5 IO_L18N_5 B30
5 IO_L19P_5 K24
5 IO_L19N_5 J24
5 IO_L20P_5 C29
5 IO_L20N_VREF_5 C30
5 IO_L21P_5 B21
5 IO_L21N_5 A21
5 IO_L22P_5 E28
5 IO_L22N_5 F28
5 IO_L23P_VRN_5 E22
5 IO_L23N_VRP_5 D22
5 IO_L24P_CC_LC_5 A31
5 IO_L24N_CC_LC_5 B31
5 IO_L9P_CC_LC_5 F23
5 IO_L9N_CC_LC_5 E23
5 IO_L10P_5 D26
5 IO_L10N_5 E26
5 IO_L11P_5F24
5 IO_L11N_5E24
5 IO_L12P_5 D27
5 IO_L12N_VREF_5 E27
5 IO_L13P_5 G23
5 IO_L13N_5 H24
5 IO_L14P_5 A28
5 IO_L14N_5 A29
5 IO_L15P_5 B25
5 IO_L15N_5 C25
5 IO_L16P_5 J25
5 IO_L16N_5 K26
5 IO_L25P_CC_LC_5 B28
5 IO_L25N_CC_LC_5 C28
Table 2-1: CF1140 Package Pinout (SX55) (Cont’d)
Bank Pin Description Pin
Number No Connects