Symmetricom bc620 User manual

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bc620 / 627AT
Time and Frequency
Processor
Revision B
User’s Guide
8500-0011
March, 2004
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COPYRIGHT NOTICE
Copyright 1997 Symmetricom, Inc. All Rights Reserved
This User's Guide is provided to assist the user in the operation and maintenance of the supplied equipment. It is
recognized that multiple copies may be required to support even a single unit, and for this reason, permission is hereby
granted to reproduce the supplied User's Guide for the purpose stated above, provide that this notice is included as part
of the copy. Additional copies are also available from Symmetricom Inc for a nominal fee.
In no case, however, does the supply of these User's Guide’s or the granting of rights to reproduce the User's Guide’s,
grant any rights to use information contained within to reproduce the supplied equipment or software, either in whole or
part.
The equipment and software described in this User's Guide has been developed solely at the expense of Symmetricom
Inc and is proprietary. No unlimited rights in technical data are granted. Limited Rights as per DFARS 252.227-7013
shall be effective for ten years from the copyright date.
FEDERAL COMMUNICATIONS COMMISSION (FCC) STATEMENT
This equipment is certified to comply with the limits for a Class A computing device pursuant to Part 15,
Subpart B of FCC Rules.
This equipment generates and uses radio frequency (RF) energy. If not installed and used properly, that is, in
strict accordance with the manufacturer's instructions, it may cause interference to radio or television
reception.
If this equipment does cause interference to radio or television reception, which can be determined by turning
the equipment on and off, the user is encouraged to correct the interference by one or more of the following
measures:
•Reorient the radio/television receiving antenna.
•Move the antenna leads away from any wire runs to the personal computer with the Symmetricom
module.
•If using an indoor antenna, have a quality outdoor antenna installed.
•Relocate the personal computer with respect to the radio/television receiver.
•Connect the AC transformer to a different outlet so the personal computer and the radio/television are on
different branch circuits.
If necessary, the user should consult the dealer or an experienced radio/television technician for suggestions
or reference the following booklet, prepared by the Federal Communications Commission, helpful: How to
Identify and Resolve Radio-TV Interference Problems. This booklet is available from the U.S: Government
Printing Office, Washington D.C. 20402. Stock No. 004--000-00345-4.
Properly shielded and grounded cables and connectors must be used for connection to peripherals in order to
meet FCC emission limits. Symmetricom Inc. is not responsible for any radio or television interference
caused by using other than recommended cables or by unauthorized modifications to this equipment. It is the
responsibility of the user to correct such interference.
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Symmetricom, Inc. bc620/627AT Time and Frequency Processor i
bc620/627AT
TIME AND FREQUENCY PROCESSOR
TABLE OF CONTENTS
SECTION PAGE
CHAPTER ONE
INTRODUCTION
1.0 General.................................................................................................................................. 1-1
1.1 Key Features ......................................................................................................................... 1-1
1.2 Physical and Functional Overview ....................................................................................... 1-2
1.3 Performance Specifications .................................................................................................. 1-4
1.3.1 Time Code Reader ................................................................................................. 1-4
1.3.2 Time Code Generator............................................................................................. 1-4
1.3.3 Bus Characteristics ................................................................................................ 1-4
1.3.4 Digital Inputs ......................................................................................................... 1-4
1.3.5 Digital Outputs....................................................................................................... 1-5
1.3.6 External 10 MHz Input .......................................................................................... 1-5
1.3.7 Environmental Specifications ................................................................................ 1-5
1.3.8 Digital Synchronization Signals ............................................................................ 1-5
CHAPTER TWO
INSTALLATION AND SETUP
2.0 General.................................................................................................................................. 2-1
2.1 Base Address Selection......................................................................................................... 2-1
2.2 Installation Procedure ........................................................................................................... 2-4
2.3 Demonstration Programs ...................................................................................................... 2-5
2.4 MS-DOS Device Driver........................................................................................................ 2-5
CHAPTER THREE
SOFTWARE INTERFACE
3.0 General.................................................................................................................................. 3-1
3.0.1 Glossary of Key Terms .......................................................................................... 3-1
3.1 Registers................................................................................................................................ 3-2
3.1.1 PAGE Select Register ............................................................................................ 3-2
3.1.2 TIMEREQ and TIME0-TIME7 Registers ............................................................. 3-2
3.1.3 CR0 Control Register 0 ......................................................................................... 3-8
3.1.4 EVENT0-EVENT8 Time Capture Registers ......................................................... 3-8
3.1.5 UNLOCK Register................................................................................................. 3-8
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TABLE OF CONTENTS
ii bc620/627AT Time and Frequency Processor Symmetricom, Inc.
3.1.6 ACK Register......................................................................................................... 3-8
3.1.7 Mask Interrupt MASK Register........................................................................... 3-10
3.1.8 INTSTAT Interrupt Status Register..................................................................... 3-10
3.1.9 FIFO Register ...................................................................................................... 3-11
3.1.10 STROBE2-STROBE6 Time Coincident Strobe Registers ................................ 3-11
3.2 Functional Description........................................................................................................ 3-11
3.2.1 Changing the Active Page.................................................................................... 3-11
3.2.2 Reading Time on Demand ................................................................................... 3-11
3.2.3 Event Time Capture ............................................................................................ 3-11
3.2.3.1 External Event Input ............................................................................ 3-12
3.2.3.2 Programmable Periodic Output............................................................. 3-12
3.2.3.3 Time Capture Lockout ......................................................................... 3-12
3.2.4 Time Coincidence Strobe Output ........................................................................ 3-12
3.2.5 FIFO Interface - Programming the bc620AT ...................................................... 3-13
3.3 PC AT Interrupts................................................................................................................. 3-13
CHAPTER FOUR
FIFO DATA PACKETS
4.0 General.................................................................................................................................. 4-1
4.1 Writing Data Packets ............................................................................................................ 4-1
4.1.1 Packet “A” - Select Operational Mode ................................................................ 4-1
4.1.2 Packet “B” - Set Major Time............................................................................... 4-2
4.1.3 Packet “C” - Command Input .............................................................................. 4-4
4.1.4 Packet “D” - Load the D/A Converter ................................................................. 4-4
4.1.5 Packet “F” - Heartbeat (Periodics) Control ......................................................... 4-5
4.1.6 Packet “G” - Propagation Delay Offset Control.................................................. 4-7
4.1.7 Packet “H” - Set Time Code Format for Mode 0................................................. 4-8
4.1.8 Packet “I” - Clock Source Select ......................................................................... 4-9
4.1.9 Packet “J” - Send Data to the GPS Receiver ....................................................... 4-9
4.1.10 Packet “K” - Select Generator Code.................................................................. 4-9
4.1.11 Packet “L” - Set Real Time Clock ................................................................... 4-10
4.1.12 Packet “M” - Local Time Offset Select ........................................................... 4-10
4.1.13 Packet “O” - Request Data from the bc620AT................................................ 4-11
4.1.14 Packet “P” - Path Selection.............................................................................. 4-15
4.1.15 Packet “Q” - Set Disciplining Gain ................................................................. 4-16
4.1.16 Packet “R” - Generator Time Offset Select ..................................................... 4-16
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TABLE OF CONTENTS
Symmetricom, Inc. bc620/627AT Time and Frequency Processor iii
CHAPTER FIVE
PROGRAMMING EXAMPLES
5.0 General.................................................................................................................................. 5-1
5.1 Reading Time on Demand .................................................................................................... 5-1
5.2 External Event Time Capture ............................................................................................... 5-2
5.3 Program Periodic Frequency of 1000 Hz............................................................................. 5-2
5.4 Set Mode 1 and the Major Time ........................................................................................... 5-2
5.5 Select Mode 0 (IRIG B) and Advance TFP 2.5 Milliseconds .............................................. 5-3
CHAPTER SIX
INPUT AND OUTPUT SIGNALS
6.0 General.................................................................................................................................. 6-1
6.1 Connector I/O ...................................................................................................................... 6-1
6.2 Jumper Selections ................................................................................................................. 6-2
CHAPTER SEVEN
ADJUSTMENTS
7.0 General.................................................................................................................................. 7-1
7.1 Time Code Phase Lock Loop Adjustment ............................................................................ 7-1
7.2 Time Code Output Amplitude Adjustment........................................................................... 7-2
APPENDIX A
IRIG TIME CODE FORMAT
A.0 General ................................................................................................................................ A-1
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TABLE OF CONTENTS
iv bc620/627AT Time and Frequency Processor Symmetricom, Inc.
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Symmetricom Inc bc620/627AT Time and Frequency Processor 1-1
CHAPTER ONE
INTRODUCTION
1.0 GENERAL
This bc620/627AT Time and Frequency Processor (TFP) User's Guide provides the following
information:
•Introduction and key feature description.
•Installation and setup.
•Detailed operation and programming interfaces.
•Programming examples.
•Input and output signals.
1.1 KEY FEATURES
The bc620/627AT has been designed with the following key features:
•Time on demand (days through microseconds) with zero latency. This feature is
implemented with hardware registers which latch the current time upon host request.
•Event logging (days through 0.1 microseconds). This feature is implemented with a second
set of hardware registers. Time is captured on a positive or negative input edge or secondary
bus time request.
•Four operational modes are supported. Modes are distinguished by the reference source.
Mode Source Of Synchronization
0Time code - IRIG A, IRIG B, XR3, 2137, NASA36 (modulated or
DC).
1Free running - on board 10 MHz oscillator (VCXO) used as
reference.
21 PPS - synchronizes to external one pulse per second.
3RTC - uses on board battery backed real time clock IC.
4GPS - uses Acutime GPS receiver as reference (bc627AT only).
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CHAPTER ONE
1-2 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
•Provides an output clock synchronized to the selected reference; programmable 1, 5, or 10
MHz TTL.
•All modes of operation are supplemented by flywheel operation (i.e. if synchronization
source is lost the TFP will continue to function at the last known reference rate).
•Generates synchronized IRIG B time code. Modulated and DC level shift formats are
produced simultaneously.
•Programmable frequency output (periodics) is provided. Pulse rates from 2.3 MHz to 2.5
MHz are supported.
•A time coincidence strobe output is provided. Programmable from days through
milliseconds. This strobe also has an “each second” mode programmable to milliseconds.
•Five maskable interrupt sources are supported. IRQ levels 3-7, 9-12, 14, and 15 can be
selected via jumper JP1.
Interrupt # Source of Interrupt
0 External event input has occurred.
1 A periodic output has occurred.
2 The time coincidence strobe has occurred.
3 A one second epoch (1pps output) has occurred.
4 An output FIFO data packet is available.
1.2 PHYSICAL AND FUNCTIONAL OVERVIEW
The bc620/627AT is a half length PC AT I/O expansion bus board. Operation is controlled via
two 16 byte pages of 8 bit registers written and read by the host via the PCbus. The bc620/627
AT occupies 16 bytes in the AT I/O address space. The I/O signals are accessible via two 15 pin
“D” connectors mounted on the rear panel. The bc620/627 AT is shown in Figure 1-1.
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INTRODUCTION
Symmetricom, Inc. bc620/627AT Time and Frequency Processor 1-3
Figure 1-1
bc620/627AT Time and Frequency Processor
Datum Inc, bc620AT
ASSY 11573 J
U1
C11
U8
C4
Y1
C15
U11
C13
U10
C12
U9
C50
R34
U3
C2 C1
U2
U6 U5
C5
U12
RP1
C6
C8
R1
C51
R35
R2
R3
+
C10
R4R5
R13
R7
R14
R5
C7
U13
C17
C18
U7
C7
C9
U28
C52
U29
C53
C19
RV1
RV2
J3
U23
C39
U24
C41
R20
U25
Q1 Q2
R23
R22
R21
R25
R24
C44
+ +
B1
C28
U17
SW1
C21 C20
C23 C22
C25 C24
U20
C30
U18
C20
R9 R8 R10
C31
U21
C37
C33
U19
C32
C34 C35
R12 R11
R15
R16
R17
U22
CR1 CR2
R26 R27 R28
R29 R30 R31
2 4
JP2
R32 R33
U27U26
C45
1
3
5
7
9
11
13
15
17
19
21
23
R15
R14
R12
R11
R10
R9
R7
R6
R5
R4
R3
JP1
On IRQ
C43
+
C42
Y2
C40
SN
C46
+
C47
+
C49
+
J1
J2
TD1
C38
R18
R19
C48
U14 U15 U16
Q3
C27 C28
C36
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CHAPTER ONE
1-4 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
1.3 PERFORMANCE SPECIFICATIONS
1.3.1 TIME CODE READER
Format IRIG A, and IRIG B. XR3, 2137; NASA36.
Carrier Range +/- 50ppm.
Flywheel Accuracy Drift < 2 millisecond per hour (applies to all operational modes).
Modulation Ratio 3:1 to 6:1.
Input Amplitude 0.5 to 5 volts peak-to-peak.
Input Impedance 10KΩAC coupled.
1.3.2 TIME CODE GENERATOR
Format IRIG B.
Modulation Ratio 3:1.
Output Amplitude 0 to 0 volts peak-to-peak.
Dc Level Shift TTL/CMOS compatible.
1.3.3 BUS CHARACTERISTICS
Address Space 16 bytes in PC I/O Address Space (0x100 - 0x3FF).
Data Transfer D08 (eight bit).
Interrupts IRQ 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 (jumper selectable).
Power +5 @ 450 milliamperes -12 @ 20 milliamps.
+12 @ 55 milliamps (250 milliamps - bc627AT).
1.3.4 DIGITAL INPUTS
Event Capture TTL / CMOS positive or negative edge triggered.
20 nanoseconds minimum width 250 nanoseconds min. period.
External 1pps TTL / CMOS positive edge on time.
20 nanoseconds minimum width.
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INTRODUCTION
Symmetricom, Inc. bc620/627AT Time and Frequency Processor 1-5
1.3.5 DIGITAL OUTPUTS
1 PPS TTL / CMOS positive edge on time (200 msec pulse width).
Periodics TTL / CMOS positive edge on time (variable pulse width).
Strobe TTL / CMOS positive edge on time (1 msec pulse width).
1, 5, 10 MHz Clock TTL / CMOS positive edge on time.
1.3.6 EXTERNAL 10 MHz INPUT
Digital Input (or) TTL / CMOS 45% to 55% duty cycle.
10MHz Input 1.5 to 4 volts peak-to-peak.
1.3.7 ENVIRONMENTAL SPECIFICATIONS
Temperature Operating. 0oto 70ocentigrade.
Non-Operating. -50oto 125ocentigrade.
Relative Humidity Operating. 5% to 95% non-condensing.
Altitude Operating. -400 to 18,000 meters MSL.
1.3.8 DIGITAL SYNCHRONIZATION SIGNALS
Format DSS.
Signal RS-422.
Communication 9600 bps, 8 bit, 1 stop bit, no parity.
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CHAPTER ONE
1-6 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
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CHAPTER TWO
2-2 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
Table 2-1
Section One
PC Bus Base Address Selection (SW1)
Base
Addr
S1
A9
S2
A8
S3
S7
S4
A6
S5
A5
S6
A4 A3 A2 A1 A0
100H ON OFF ON ON ON ON 0000
110H ON OFF ON ON ON OFF 0000
120H ON OFF ON ON OFF ON 0000
130H ON OFF ON ON OFF OFF 0000
140H ON OFF ON OFF ON ON 0000
150H ON OFF ON OFF ON OFF 0000
160H ON OFF ON OFF OFF ON 0000
170H ON OFF ON OFF OFF OFF 0000
180H ON OFF OFF ON ON ON 0000
190H ON OFF OFF ON ON OFF 0000
1A0HONOFFOFFONOFFON0000
1B0HONOFFOFFONOFFOFF0000
1C0HONOFFOFFOFFONON0000
1D0HONOFFOFFOFFONOFF0000
1E0HONOFFOFFOFFOFFON0000
1F0HONOFFOFFOFFOFFOFF0000
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INSTALLATION AND SETUP
Symmetricom, Inc. bc620/627AT Time and Frequency Processor 2-3
Table 2-1
Section Two
PC Bus Base Address Selection (SW1)
Base
Addr
S1
A9
S2
A8
S3
S7
S4
A6
S5
A5
S6
A4 A3 A2 A1 A0
200H OFF ON ON ON ON ON 0000
210H OFF ON ON ON ON OFF 0000
220H OFF ON ON ON OFF ON 0000
230H OFF ON ON ON OFF OFF 0000
240H OFF ON ON OFF ON ON 0000
250H OFF ON ON OFF ON OFF 0000
260H OFF ON ON OFF OFF ON 0000
270H OFF ON ON OFF OFF OFF 0000
280H OFF ON OFF ON ON ON 0000
290H OFF ON OFF ON ON OFF 0000
2A0HOFFONOFFONOFFON0000
2B0HOFFONOFFONOFFOFF0000
2C0HOFFONOFFOFFONON0000
2D0HOFFONOFFOFFONOFF0000
2E0HOFFONOFFOFFOFFON0000
2F0HOFFONOFFOFFOFFOFF0000
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CHAPTER TWO
2-4 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
Table 2-1
Section Three
PC Bus Base Address Selection (SW1)
2.2 INSTALLATION PROCEDURE
To install the bc620/627AT module in your computer chassis:
•Remove the computer chassis cover.
•Select a vacant expansion slot and remove the blank rear panel bracket. Save the screw.
•Slide the bc620/627AT Module straight down to engage the motherboard connectors.
•Fasten the top of the bracket to the chassis using the screw that was saved from Step 2.
•Replace the chassis cover.
Base
Addr
S1
A9
S2
A8
S3
S7
S4
A6
S5
A5
S6
A4 A3 A2 A1 A0
300H OFF OFF ON ON ON ON 0000
310H OFF OFF ON ON ON OFF 0000
320H OFF OFF ON ON OFF ON 0000
330H OFF OFF ON ON OFF OFF 0000
340H OFF OFF ON OFF ON ON 0000
350H OFF OFF ON OFF ON OFF 0000
360H OFF OFF ON OFF OFF ON 0000
370H OFF OFF ON OFF OFF OFF 0000
380H OFF OFF OFF ON ON ON 0000
390H OFF OFF OFF ON ON OFF 0000
3A0HOFFOFFOFFONOFFON0000
3B0HOFFOFFOFFONOFFOFF0000
3C0HOFFOFFOFFOFFONON0000
3D0HOFFOFFOFFOFFONOFF0000
3E0HOFFOFFOFFOFFOFFON0000
3F0HOFFOFFOFFOFFOFFOFF0000
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INSTALLATION AND SETUP
Symmetricom, Inc. bc620/627AT Time and Frequency Processor 2-5
2.3 DEMONSTRATION PROGRAMS
The following demonstration program is provided with the bc620/627AT. A detailed
explanation of the programs operation is included in the text file bc620.hlp. This file can be
viewed by executing the README.EXE batch file.
bc620.c / bc620.exe
This program is written in Turbo C, and is intended to illustrate how to exercise the bc620 from
a PC or compatible. Both the source code and an executable file have been provided. The
modules base address is controlled by the value of the constant “base.” Section 3.2.5 of the
User’s Guide describes the packet protocol used by this program. All the usual disclaimers
concerning programming style and liability for use apply to this software.
2.4 MSDOS DEVICE DRIVER
bc620/627AT DOS Clock Device Driver v2.0
========================================
A device driver is supplied with the bc620/627AT. This driver is intended to replace the PC real
time clock in all aspects; time and date stamping of files, high level language calls, time and date
requests from the DOS prompt, and any other applications which use the DOS clock (INT21
funcs 2A, 2B, 2C or 2D).
The driver is installed by adding a line to the config.sys file containing a device load statement.
The following statement shows the syntax for the bc620 driver.
device=<path>bc620.sys {- / \}{AMOY}<switch data>
Note: If the path is not included, the system will search for the device driver in the root
directory of the boot disk.
Also, there are three allowed switch delimiters: dash(-), slash(/) and the backslash(\).
The switch ids are defined as follows:
Axxx
Address
Three digits of hex base address
Allowed values: 100-3F0
Default: 300
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CHAPTER TWO
2-6 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
Mx
Mode
One digit to select mode. If the board is not already in the requested mode the driver
initialization routine will set the board to the requested mode.
Allowed values:
0 (IRIG Decoder Mode)
1 (Free Running Mode)
2 (External 1 PPS Mode)
3 (Battery Backed RTC Mode)
4 (GPS Mode [bc627AT only])
Default: doesn't change mode
Osxx
Offset
One digit of sign (optional) immediately followed by one or two digits of offset in hours from
GMT.
Allowed values:
Sign “+” or “-”
hours 0-12
Default: 0
Yxx
Year
One or two digits of year information.
Allowed values: 91-10
Default: 94
Note: Year values less than ninety-one will be assumed to mean twenty-first century.
None of the switches are “required” and the switches may be added in any order. The user is
free to set only those switches which are necessary for the particular implementation. Any
switches not set will result in the default behavior noted above.
Some possible device load statements are shown and explained in the following section.
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INSTALLATION AND SETUP
Symmetricom, Inc. bc620/627AT Time and Frequency Processor 2-7
device=c:\bc620/627AT\bc620.sys /A300 /M4 /Y94 /O-08
Description:
/A300 Sets the location where the driver will find the board to 300H.
/M4 Puts the board in GPS mode (if it is not already there).
/Y94 Sets the driver initial year to 1994.
/O-08 Sets the time returned by the driver to reflect 8 hrs behind GMT.
device=bc620.sys -A240 -Y01 -05
Description:
A240 Sets the location where the driver will find the board to 240H.
Y01 Sets the driver initial year value to 2001.
-05 Sets the time returned by the driver to reflect 5 hrs ahead of GMT.
device=bc620.sys \A310 \Y4 \O+03 \M2
Description:
\A310 Sets the location where the driver will find the board to 310H.
\Y4 Sets the driver initial year value to 2004.
\O+03 Sets the time returned by the driver to reflect 3 hrs ahead of GMT.
\M2 Puts the board in External 1 PPS mode (if it is not already there).
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CHAPTER TWO
2-8 bc620/627AT Time and Frequency Processor Symmetricom, Inc.
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