Synaptic Laboratories HyperBus Operation instructions
Synaptic Labs'
HyperBus Memory Controller (HBMC)
Tutorial
T001A: A Qsys base Nios II Reference esign with a
simple self test of the HyperFlash an HyperRAM evice
using S/Labs' HBMC IP
This tutorial describes a simple reference design for S/Labs HBMC IP targeted specifically to Intel
Cyclone 1 LP evaluation board or devboards GmbH HyperMAX 1 M25 and 1 M5 boards. Most
HBMC customers using any of these boards board will want to start with this tutorial. This tutorial
describes key aspects of a pre-configured .qsys reference project and then walks through the process of
generating and compiling that .Qsys project. This tutorial then describes how to compile the example
Nios II source code, integrate the firmware into the FPGA bitstream and then run the reference design
on the development board.
After completing this tutorial, readers may like to proceed to the second tutorial called “T 1B: A
Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM
device usng S/Labs' HBMC IP”. This tutorial shows how to download the Nios II firmware into the
FPGA device using the Nios II development environment.
Table of Contents
T 1A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and
HyperRAM device using S/Labs' HBMC IP.............................................................................................1
Set-Up Requirements:................................................................................................................................3
Step 1: Obtain core materials.....................................................................................................................3
Step 2: License Setup.................................................................................................................................3
Step 3: Install HBMC Qsys Component into the project IP Folder...........................................................4
1. Contents of the reference project...........................................................................................................5
2. Open the reference Quartus Project.......................................................................................................6
2.1 Check the correct FPGA device is selected..........................................................................................6
3. Open the reference Qsys project............................................................................................................7
4. Explore and configuring the reference Qsys project..............................................................................8
4.1 Components employed in the reference project...................................................................................8
4.2 Nios II/f processor configuration.........................................................................................................9
4.3 Configuring S/Labs HyperBus Memory Controller...........................................................................1
4.4 Configuration of Altera’s On-Chip Memory......................................................................................16
5. Generating the Qsys Design.................................................................................................................17
6. Preparing the firmware.........................................................................................................................18
6.1 Open the NIOS II Software Built Tools for Eclipse...........................................................................18
6.2 Create a simple application and BSP.................................................................................................19
6.3 Configure the Board Support Package (BSP)....................................................................................22
6.4 Generate the BSP and clean the project.............................................................................................26
6.5 Copy the memory testing source code...............................................................................................27
6.6 Build the Nios II Application.............................................................................................................28
6.7 Generate memory initialization files..................................................................................................29
7. Update the memory initialization field(s) in Qsys...............................................................................3
8. Synthesize and assemble the Design....................................................................................................31
9. Program the FPGA Bitstream into the FPGA device...........................................................................32
1 . Run the nios2-terminal application....................................................................................................33
Set-Up Requirements:
Step 1: Obtain core materials
1. Download and install Quartus Prime Standard/Lite 17.0 on your PC, please
ensure t at your PC meets t e required minimum specification.
2. For Intel's C10LP Evaluation board :
◦Create a folder/directory for your work. We suggest: C:\C10_lab\
◦ Download reference design HyperNios_Project_C10LP from:
http://media.synaptic-labs.com/pub/2 17-Designs/SynapticLabs-HBMC-Tutorial-
1/HyperNios_Project_C1 LP.zip
◦Extract to: C:\C10_lab\
3. For devboards HyperMAX board :
◦Create a folder/directory for your work. We suggest: C:\HyperMAX_lab
◦ Download reference design HyperNios_Project_HM10M25 from:
http://media.synaptic-labs.com/pub/2017-Designs/SynapticLabs-HBM -Tutorial-
001/HyperNios_Project_HM10M25.zip
◦Extract to: C:\HyperMAX_lab\
Step 2: License Setup
1. Next you need to apply for Synaptic Labs' HyperBus Memory Controller license.
You can skip t is step if you already installed t e license at some earlier stage.
Free enrollment can be obtained from:
http://opencore_license_ 1.synaptic-labs.com/
2. Synaptic Labs offers two Installation Guides t at:
a. Begin by preparing you to enroll to receive a Basic Edition (OpenCore)
license
b. Guide you on ow to install t e license file you will receive after enrolment
c. Guide you on ow to install t e Qsys components t at you will receive after
enrollment
3. Please download and read one of t ose Installation Guides:
a. Developers familiar wit installing t ird party IP into Quartus will probably
prefer t e streamlined:
HBMC IP Installation Guide for Experience Developers.
b. All ot er developers s ould download t e:
HBMC IP Installation Guide with Detailed Step-by-Step Instructions.
Step 3: Install HBMC Qsys Component into the project IP Fol er
1. In t is tutorial we assume t at S/Labs HyperBus Memory Controller (HBMC) will
be located in t e Project directory.
a. Ot er Qsys component installation met ods are described in t e above
mentioned installation Guides.
2. Download t e latest version of Synaptic Labs' HBMC IP from:
http://media.synaptic-labs.com/pub/SoftIP/latest_sll_ca_hbmc_ 1_be_cots.zip
3. For Intel's C10LP Evaluation board :
◦Extract to t e project/ip directory :
C:\C10_lab\HyperNios_Project_C10LP\ip
4. For devboards HyperMAX board :
◦Extract to t e project/ip directory :
C:\HyperMAX_lab\HyperNios_Project_HM10M25\ip
Step 4: Cyclone 10 LP Development Boar DIP Switches
You ave t e Cyclone 10 LP evaluation board and mini USB cable provided.
Note: the board is powered over US so no power supply is required.
Ensure that DIP Switch 4 on the Cyclone 10 boar is set to ON, this
bypasses the virtual JTAG system an simplifies boar programming.
1. Contents of the reference project
Synaptic Labs' HyperBus Memory Controller (HBMC) Reference design projects includes the
following files and directories:
HyperNios_Project_C10LP(HyperNios_Project_HM10M25) folder contains the Quartus
Prime and Qsys project files for the first reference project.
The HyperNios_Project_C10LP(HyperNios_Project_HM10M25) → ip folder will contain
S/Labs HBMC encrypted ip (refer to Setup requirements: step3 for more info)
The HyperNios_Project_C10LP(HyperNios_Project_HM10M25) → software folder is the
workspace folder for Eclipse
The HyperNios_Project_C10LP(HyperNios_Project_HM10M25) →source folder contains
the source code for:
• TestHyperRAM program as used in this HBMC Tutorial 1.
•S/Labs’ TestM s memory bandwidth benchmark for HyperRAM program which is used
in the HBMC Tutorial 2.
Note: Synaptic Labs' HyperBus Memory Controller (HBMC) IP can ONLY be simulated with
Altera's Modelsim Simulator. Please contact Synaptic Labs for a simulation model if required.
2. Open the reference Quartus Project
•In the menu bar of Quartus Prime, select File → Open Project…
•Select the file NIOS_HyperRAM.qpf in the project directory
•Click the [ Open ] button.
2.1 Check the correct FPGA evice is selecte
•Every Quartus project is targeted to a specific FPGA device. For devboards GmbH
HyperMAX 1 M25 and 1 M5 boards, check that the FPGA device matches the one
being used. This step is not needed for Intel C1 LP evaluation board.
•The HyperMAX 1 M25 board employs the 10M25DAF256C7G device.
The HyperMAX 1 M5 board employs the 10M50DAF256I7G device.
•The Intel C1 LP Evaluation board employs the 10CL025YU256I7G device
•If you need to change the FPGA device for your specific board:
◦Ensure that there are no instances of the Qsys application running.
◦Right click on the device name.
◦Select “Devices…” in the pop up window.
◦A new window will open. Select the “Device” tab.
◦Copy the required device name into the “Name filter:” field.
◦A popup window will ask: “Do you want to remove all location assignments?”
Click on the [ No ] button.
◦Select the requested device in the “available devices:” field so that it is highlighted in
blue.
◦Then click on the [ Okay ] button.
•The Quartus project and the Qsys project are now configured for the FPGA device you
selected.
4. Explore an configuring the reference Qsys
project
4.1 Components employe in the reference project
The reference Qsys project in this tutorial employs a NiosII/f processor, Synaptic Labs'
HyperBus Memory Controller (HBMC) IP, Altera’s On-chip Memory module to store code and
data in on chip SRAM, and various peripherals such as Altera’s JTAG UART and timer modules
as illustrated below. All these Qsys components are connected together.
Please note that the 5 MHz clock pin of the FPGA is mapped to the in_clk port of S/Labs
HyperBus Memory Controller instance. The HBMC instance includes an integrated PLL that
generates the clocks to drive the Avalon bus and the HyperBus memory channel.
In particular the o_av_out_clk port of the HBMC is used to drive the Avalon bus and all
of the components illustrated above.
4.2 Nios II/f processor configuration
In this example, the Nios II/f Reset and Exception vectors are mapped to onchip_memory as
illustrated below. This means that the Nios II/f processor will look for the boot code and
exception handling / interrupt code in the onchip_memory module.
As illustrated below, the instruction and data caches of the Nios II/f core have both been set to
4Kbytes in size to accelerate software performance. The instruction and data caches have both
been configured with their urstcount signal ena led so that both caches issue burst memory
transfer requests. This is done because: (a) the HyperBus protocol employs burst memory
transfer requests with closed page mode of operation; and (b) SLL’s HBMC employs an Avalon
interface with burst mode of operation.
4.3 Configuring S/Labs HyperBus Memory Controller
Synaptic Labs' HyperBus Memory Controller has been pre-configured in this reference project.
In this section we will describe various configuration options that you may wish to change.
In the "Master Configuration" ta
The open-core edition of SLL HBMC IP only supports HyperRAM. The full edition of SLL
HBMC IP supports any combination of HyperFlash and HyperRAM. Both editions offer
preconfigured memory options for supported COTS FPGA development boards. The full
edition of SLL HBMC IP also includes the option to manually configure the HyperBus devices.
To configure the project to just use HyperRAM on the Intel C1 LP/HyperMAX board:
•The FPGA oard type field is set to either:
◦Dev oards - HyperMAX 10M25 (HyperRAM) or
◦Dev oards - HyperMAX 10M50 (HyperRAM) or
◦Intel – Cyclone 10LP Evaluation Kit (HyperRAM)
To configure the project to use both HyperFlash and HyperRAM on the HyperMAX board:
•The FPGA oard type field is set to either:
◦Dev oards - HyperMAX 10M25 (HyperFlash and HyperRAM) or
◦Dev oards - HyperMAX 10M50 (HyperFlash and HyperRAM)
urrently, Intel's yclone 10LP evaluation board does not contain a HyperFlash device.
S/Labs recommends using the HyperRAM only configuration if this is your first time through
the tutorial.
In the Clock and PLL Configuration Ta (Basic Edition (OpenCore)
•The Avalon and HyperBus clock configuration field is set to One clock
•The HyperBus channel clock frequency field is set to 100 MHz
In the Clock and PLL Configuration Ta (Full Featured edition)
•The Avalon and HyperBus clock configuration field is set to Two clocks
•The HyperBus channel clock frequency field is set to 150 MHz
•The Shared Avalon clock frequency field is set to 100 MHz
15
In the Ingress Avalon Slave 0 (IAVS0) configuration ta
The IAVS port is used to access all HyperBus memories connected to the HyperBus Memory
Controller IP. The most common configuration of the IAVS port is as follows:
IAVS : Ingress Avalon port stage
•The Ena le Avalon write capa ility field is checked
•The Ena le Avalon yte-ena le capa ility field is checked
•The Register Avalon Write data field is left unchecked
IAVS : Burst Converter and address decoder stage
•The max BurstSize (in Words) field is set to 8 words
•The lineWrapBursts field is set to true
IAVS : Ingress Avalon return stage
•The Register Avalon Read data path field is left unchecked
•The Use Avalon Transaction Response field is left unchecked
The GUI interface includes significant inbuilt documentation. Moving your mouse over a
configuration field pops up the on-screen help for that field.
In the Device 0 Info ta
The “Device Info” tab provides information about the HyperBus device connected to chip
select . If in the "Master Configuration" tab, the FPGA oard type field is set to Dev oards -
HyperMAX 10M25/50 (HyperRAM) or Intel – Cyclone 10LP Evaluation Kit (HyperRAM),
these fields remain empty.
If in the "Master Configuration" tab, the FPGA oard type field is set to Dev oards -
HyperMAX 10M25/50 (HyperFlash and HyperRAM), the following table will show the
parameters, configuration and timing for the HyperFlash memory.
Device Configuration
•In this tutorial the Use factory default settings for this HyperBus device field is left
checked
The Device1 Info Ta
The table below will show the parameters, configuration and timing for the HyperRAM memory.
Device 1 Configuration
•In this tutorial the Use factory default settings for this HyperBus device field is left
checked
The exact parameters on your screen may be different because:
•The HyperMAX 1 M25 board employs a 64 Megabit HyperRAM device.
•The HyperMAX 1 M5 board employs a 128 Megabit HyperRAM device.
•The Intel C1 LP Evaluation kit employs a 128 Megabit HyperRAM device.
4.4 Configuration of Altera’s On-Chip Memory
In this reference project, Altera's On-Chip Memory is configured as a 4 Kilobyte single port
RAM. We will setup this memory to be initialized by the Nios II SBT for Eclipse
•Please ensure that:
◦[x] Initialize memory content is Ticked
◦[x] Ena le non-default initialization file is Ticked
◦[x] User created initialization file is onchip_memory.hex
Note: If you do not specify an initial .hex filename, Nios II SBT will not generate the
memory initialization file. After we have generated that file, we will then need to
update Qsys with the relative/full path to the .hex file.
•In the Synthesis section, set the Create HDL design files for synthesis field to Verilog.
•In the Simulation section, set the Create simulation model field to None.
•Then click on the [ Generate ] button.
•You may see a Save System window. Click the [ Close ] button to close the save window.
•Generating the .qsys project updates the .SOPC file which will be used by the Nios II
Software Build Tools (SBT) environment.
•Click the [ Close ] button to close the generate window.
•You may want to close the Qsys window.
6. Preparing the firmware
6.1 Open the NIOS II Software Built Tools for Eclipse
•In Quartus Prime, go to the menu bar and select
Tools → NIOS II Software Built Tools for Eclipse.
•Click the [Browse…] button. A new file selector window will open. In this tutorial we
are going to select the software folder located inside the project folder as the
workspace and then click the [ OK ] button.
•Be sure to leave the [ ] Use this as the default field unticked.
•Click the [ OK ] button.
MAX1 _HyperNios_Project/software
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