Systran SCRAMNet SC150 Application guide

SCRAMNetÒSC150 Network
Rehostable Adapter
Hardware Reference
Document No. D-T-MR-REHOST##-A-0-A3

FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Systran reserves the right to make changes without notice.
Systran makes no warranty of any kind with regard to this printed material, including, but not limited to,
the implied warranties of merchantability and fitness for a particular purpose.
©Copyright 2000 Systran Corporation. All rights reserved.
SCRAMNetÒis a registered trademark of Systran Corporation. US Patent # 4,928,289.
Ôis a trademark of Systran Corporation.
TRI-STATEÒis a registered trademark of National Semiconductor Corporation.
References to products and/or services of other manufacturers as provided in this document do not constitute
endorsement by Systran Corporation.
Revised: April 18, 2000
Systran Corporation
4126 Linden Avenue
Dayton, OH 45432-3068 USA
[phone]

FCC
This product is intended for use in industrial, laboratory or military environments. This product uses and
emits electromagnetic radiation, which may interfere with other radio and communication devices. The
user may be in violation of FCC regulations if this device is used in other than the intended market
environments.
CE
As a component part of another system, this product has no intrinsic function and is therefore not subject
to the European Union CE EMC directive 89/336/EEC.

Copyright 2000 i SCRAMNet SC150 REHOSTABLE REFERENCE
TABLE OF CONTENTS
1. INTRODUCTION......................................................................................................................................1-1
1.1 How to Use This Manual..........................................................................................................1-1
1.1.1 Purpose...................................................................................................................1-1
1.1.2 Scope......................................................................................................................1-1
1.1.3 Style Conventions..................................................................................................1-1
1.2 Related Information..................................................................................................................1-1
1.3 Quality Assurance.....................................................................................................................1-2
1.4 Technical Support.....................................................................................................................1-2
1.5 Ordering Process.......................................................................................................................1-3
2. PRODUCT OVERVIEW ...........................................................................................................................2-1
2.1 Overview...................................................................................................................................2-1
2.2 Description................................................................................................................................2-1
2.3 Specifications............................................................................................................................2-1
3. SIGNAL DEFINITION..............................................................................................................................3-1
3.1 Overview...................................................................................................................................3-1
3.2 Pinout Description ....................................................................................................................3-1
3.3 CSR Registers...........................................................................................................................3-3
3.4 Detailed Description of Signals ................................................................................................3-4
4. DESIGN GUIDELINES.............................................................................................................................4-1
4.1 Overview...................................................................................................................................4-1
4.2 Software Compatibility.............................................................................................................4-1
4.2.1 Interrupt Vector Register........................................................................................4-1
4.2.2 Interrupt Pending and the SCRAMNet Interrupt system........................................4-1
4.2.3 SCRAMNet Memory and CSR mapping...............................................................4-1
4.3 Design Requirements................................................................................................................4-2
4.3.1 Transaction Definition ...........................................................................................4-2
4.3.2 Transaction Setup Information...............................................................................4-2
4.3.3 Transaction Start: HREQ and HREQ_PEND Handshake ......................................4-5
4.3.4 Transaction End: HACK Considerations................................................................4-6
4.4 Throughput considerations........................................................................................................4-6
4.4.1 User Throughput With No Network Traffic...........................................................4-6
4.4.2 User Throughput With Light Network Traffic.......................................................4-7
4.4.3 User Throughput With Heavy Network Traffic .....................................................4-8
4.4.4 User Throughput With Full Network Traffic .........................................................4-9
4.4.5 Conclusions And Comments................................................................................4-10
4.5 Optional Design Features........................................................................................................4-11
4.5.1 The SCRAMNet ASIC Interrupt System .............................................................4-11
4.5.2 The SCRAMNet ASIC Address Decoder and Its Application to the Rehostable
Adapter .........................................................................................................................4-13
5. REHOSTABLE INTERFACING...............................................................................................................5-1
5.1 Overview...................................................................................................................................5-1
5.2 Basic Rehostable VME Interface..............................................................................................5-1
5.3 Supported Features ...................................................................................................................5-1
5.3.1 Write Posting..........................................................................................................5-1
5.3.2 Quasi-dual Vector Interrupts..................................................................................5-1
5.3.3 8–, 16–, And 32–bit Transactions ..........................................................................5-1
5.4 Unsupported Features ...............................................................................................................5-1
5.5 System Architecture..................................................................................................................5-2
5.5.1 Buffer Blocks.........................................................................................................5-2
5.5.2 Data Un-justifier Block..........................................................................................5-2
5.5.3 Controller Interface Block......................................................................................5-3
5.5.4 Rehostable Adapter Block......................................................................................5-3
5.5.5 Media Card (“MAC”) Interface Block...................................................................5-4

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5.6 Controller..................................................................................................................................5-4
5.6.1 Address Decode .....................................................................................................5-4
5.6.2 Transaction Size and Position Encode ...................................................................5-5
5.6.3 Transaction Identification ......................................................................................5-6
5.6.4 Transaction Controller ...........................................................................................5-8
5.6.5 Interrupt Vector Register......................................................................................5-11
5.6.6 Interrupt Control Engine......................................................................................5-11
5.7 Memory Decoder....................................................................................................................5-12
5.7.1 Using The CSR decoder.......................................................................................5-12
5.7.2 Using the On-board Rehostable Adapter Memory Decoder.................................5-12
5.8 Memory Subsystems...............................................................................................................5-12
6. SERIAL LEDS SUPPORT CIRCUITRY...................................................................................................6-1
6.1 Overview...................................................................................................................................6-1
6.2 Interface....................................................................................................................................6-1
6.3 Serial Protocol...........................................................................................................................6-2
6.4 User Designs.............................................................................................................................6-5
6.5 Simple Receiver Design............................................................................................................6-6
6.6 Full Serial Port Design..............................................................................................................6-7
6.7 Cables .....................................................................................................................................6-13
APPENDICES
APPENDIX A – CSR Description.................................................................................................................A-1
APPENDIX B – VHDL Source Code ...........................................................................................................B-1
APPENDIX C – Specifications .....................................................................................................................C-1
APPENDIX D – Schematics..........................................................................................................................D-1
APPENDIX E – Hardware Assembly............................................................................................................E-1
APPENDIX F – Bill of Materials.................................................................................................................. F-1
GLOSSARY................................................................................................................................GLOSSARY-1
INDEX................................................................................................................................................. INDEX-1

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FIGURES
Figure 2-1 Rehostable Adapter......................................................................................................................2-1
Figure 3-1 CS-Bus and CS Mode Timing......................................................................................................3-6
Figure 4-1 HREQ and HREQ_PEND Handshake..........................................................................................4-5
Figure 4-2 Standard Interrupt Logic............................................................................................................4-12
Figure 4-3 Ultra-simple Interrupt Logic......................................................................................................4-13
Figure 4-4 Switch 1 .....................................................................................................................................4-14
Figure 5-1 Block Diagram 1..........................................................................................................................5-2
Figure 5-2 Block Diagram 2..........................................................................................................................5-3
Figure 6-1 Serial Protocol..............................................................................................................................6-3
Figure 6-2 Remote Device Serial Receiver....................................................................................................6-5
TABLES
Table 3-1 ACR Bus Definitions.....................................................................................................................3-4
Table 3-2 Control Status Bus Definition........................................................................................................3-5
Table 3-3 CSR_ME Bus Output Codes.........................................................................................................3-7
Table 3-4 MCI Bus Codes...........................................................................................................................3-10
Table 3-5 ~MWE Bus Lines and Byte-lanes ...............................................................................................3-11
Table 3-6 Transaction Types .......................................................................................................................3-14
Table 3-7 TSP Lines....................................................................................................................................3-14
Table 3-8 Rehostable Adapter Signal Capacitance......................................................................................3-15
Table 4-1 TS1/TS2 Values.............................................................................................................................4-3
Table 4-2 TSP Codes.....................................................................................................................................4-3
Table 4-3 HA Address Connections vs. Memory Size...................................................................................4-4
Table 4-4 Big-Endian 32-bit Formatting .......................................................................................................4-5
Table 4-5 MD Bus Bits Definition During Switch READ...........................................................................4-15
Table 4-6 CSR_ME[1:0] Line Definitions...................................................................................................4-15
Table 5-1 Data Un-justifier Transformations.................................................................................................5-2
Table 5-2 Memory Address Modifiers...........................................................................................................5-4
Table 5-3 VME Transactions and TSPx Codes .............................................................................................5-5
Table 5-4 CSR_I_O_Locations and Switch Settings...................................................................................5-12
Table 6-1 Count_modes.................................................................................................................................6-4

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Copyright 2000 1-1 SCRAMNet SC150 REHOSTABLE REFERENCE
1. INTRODUCTION
1.1 How to Use This Manual
1.1.1 Purpose
The purpose of this document is to aid the engineer integrating the SCRAMNet SC150
Rehostable Adapter to a specific design. This will be accomplished by defining the signal
interface, defining the interface requirements, and by showing an implementation
example. Information is also provided on memory subsystems and hardware assembly. A
section on LEDS Support Circuitry is also included.
.
NOTE: SCRAMNet SC150 (previously SCRAMNet+) is referred to in this manual as
“SCRAMNet.”
1.1.2 Scope
This document is intended for SCRAMNet network system engineers. To use this manual
effectively you need an understanding of the SCRAMNet network hardware.
1.1.3 Style Conventions
The following conventions are used in this document:
· TheCc symbol indicates that you must press the Ckey whileyou
simultaneously press another key (in this case, c).
· Names of files, parameters and commands are in bold type; for example,
sysconfigtab file.
· Names of called routines are followed by open and closed parentheses and are
printed in italics; for example, dma_read().
· Directory path names are in italics; for example, mkdir /usr/SCRAMNet.
· VHDL is boxed, Courier, 9 pt font.
· Hexadecimal values within paragraph text are written with the word hex
italicized and one point smaller than the context font following the value; for
example, 03FF hex.Hexadecimal values in tables or in code blocks may be
written using abbreviated notation; for example 0x03FF.
· CSR and ACR Register bits and bit ranges are specified by the register
identification followed by the bit or range of bits in brackets [ ]; for example,
CSR6[4], CSR3[15:0], ACR[2]
· In a prompt, square brackets indicate that the enclosed item is the default
response. For example, [y] means the default response is Yes.
1.2 Related Information
· SCRAMNet Network Media User’s Guide
(Document No. D-T-MU-MEDIA)
· SCRAMNet Utilities User Manual
(Document No. C-T-MU-UTIL)

INTRODUCTION
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1.3 Quality Assurance
Systran Corporate policy is to provide our customers with the highest quality products
and services. In addition to the physical product, the company provides documentation,
sales and marketing support, hardware and software technical support, and timely product
delivery. Our quality commitment begins with product concept, and continues after
receipt of the purchased product.
Systran’s Quality System conforms to the ISO 9001 international standard for quality
systems. ISO 9001 is the model for quality assurance in design, development, production,
installation and servicing. The ISO 9001 standard addresses all 20 clauses of the ISO
quality system and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:
· Achieve, maintain and continually improve the quality of our products through
established design, test, and production procedures.
· Improve the quality of our operations to meet the needs of our customers,
suppliers, and other stakeholders.
· Provide our employees with the tools and overall work environment to fulfill,
maintain, and improve product and service quality.
· Ensure our customer and other stakeholders that only the highest quality product
or service will be delivered.
The British Standards Institution (BSI), the world’s largest and most respected
standardization authority, assessed Systran’s Quality System. BSI’s QualityAssurance
division certified we meet or exceed all applicable international standards, and issued
Certificate of Registration, number FM 31468, on May 16, 1995. The scope of Systran’s
registration is: “Design, manufacture and service of high technology hardware and
software computer communications products.” The registration is maintained under BSI
QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage
customers to contact us with questions, suggestions, or comments regarding any of our
products or services. We guarantee professional and quick responses to your questions,
comments, or problems.
1.4 Technical Support
Technical documentation is provided with all of our products. This documentation
describes the technology, its performance characteristics, and includes some typical
applications. It also includes comprehensive support information, designed to answer any
technical questions that might arise concerning the use of this product. We also publish
and distribute technical briefs and application notes that cover a wide assortment of
topics. Although we try to tailor the applications to real scenarios, not all possible
circumstances are covered.
Although we have attempted to make this document comprehensive, you may have
specific problems or issues this document does not satisfactorily cover. Our goal is to
offer a combination of products and services that provide complete, easy-to-use solutions
for your application.
If you have any technical or non-technical questions or comments (including software),
contact us. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight
Time.

INTRODUCTION
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· Phone: [phone] or [phone]
· E-mail: [email protected]
· Fax: [phone]
1.5 Ordering Process
To learn more about Systran products or to place an order, please use the following
contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern
Standard/Daylight Time.
· Phone: [phone] or [phone]
· E-mail: i[email protected]
· World Wide Web address: www.systran.com

INTRODUCTION
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Copyright 2000 2-1 SCRAMNet SC150 REHOSTABLE REFERENCE
2. PRODUCT OVERVIEW
2.1 Overview
Figure 2-1 Rehostable Adapter
2.2 Description
The SCRAMNet Rehostable Adapter is a 3.3" x 4.0" circuit card holding the SCRAMNet
“core” circuitry. The following is required to obtain a working SCRAMNet node:
· +5 V @ 0.7 Amps
· A connection to a Systran Media card (the physical media interface)
· User-provided circuitry to interface the Rehostable Adapter to the users design
The goal of the SCRAMNet Rehostable Adapter is to provide an affordable “core” piece of
a SCRAMNet node for use in embedded applications.
2.3 Specifications
The Rehostable Adapter is the “core” of a SCRAMNet node and therefore provides the
following specifications:
· Connection to any Systran supported physical media
· 16.7 MB/s throughput (MAX)

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· Maximum 2 MB on-card SCRAMNet memory (optional 4 MB or 8 MB memory
using an expansion card)
· Shared memory and Error based interrupt support
· Shared memory and CSR address-hit comparators (requires additional external
circuitry)
· Full SCRAMNet hardware and software compatibility

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3. SIGNAL DEFINITION
3.1 Overview
This section contains a complete pinout description, definition of the Control/Status
Registers (CSRs), and a detailed description of the interface signals.
3.2 Pinout Description
This is a listing of the I/O pin definitions for the RehostableAdapter. All active low
signals have '~' as their first character. The bold, italicized signals must be driven by host-
specific Hardware.
Rehostable Adapter
HREQ.................................................Host Request
R_W....................................................Read / Write
TS1......................................................Transaction Select 1
TS2......................................................Transaction Select 2
INT_PEND........................................Host Interrupt Pending line
HA[31:2]............................................Host Address Port
HD[31:0]............................................Host Data bus
TSP[2:0].............................................Transaction Size and Position
HACK.................................................Host Cycle Acknowledge
A_D_LTCH........................................Address Data Latch (Latch Data signal during a
write)
HREQ_PEND ....................................Host Request Pending (Handshake line showing a
pending host request)
OE_A2B[3:0].....................................Output Enable
CNTRL_STATUS[20,18,17,16, 7]...Control Status bits
CS_MODE.........................................Control Status Mode (1 = Non-Network)
STS1...................................................Status of Transaction Select 1
STS2...................................................Status of Transaction Select 2
Memory Control Port
MA[22:2]............................................Memory Address bus
MD[31:0]............................................Memory Data bus
MBCS.................................................External Memory Board Chip Select
~MWE[3:0]........................................Memory Write Enables
ACR[7:0]............................................ACR bus
MEM_DET ........................................Memory Detect for External RAM
~M_DOE............................................Memory Data Output Enable
~ACR_DOE.......................................ACR Data Output Enable
~ACR_WE.........................................ACR Write Enable
MCI[2:0].............................................Memory Size Configuration Bus
Address Comparator
MEM_HIT..........................................Memory Address Hit

SIGNAL DEFINITION
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CSR_ME[1:0] ....................................CSR Map Code
Misc & Control
~RST_IN............................................Rest Input (External power monitor pin - must be
(implemented by host)
BUSY .................................................EEPROM Read is active - HREQ's will not be
acknowledged
CLK....................................................37.5 MHz clock (26.66 ns) Output
~SW_OE0 ..........................................Switch Read Output Enable
Media Card Interface
LINK_A_B.........................................Redundant link A or B selection
L_INSERT_LED................................Insert Status
L_CD_LED........................................Carrier Detect Status
F_RELAY ..........................................Fiber Optic Relay Sense and Control
L_MECHSW......................................Mechanical Switch Output
S_CLK................................................Serial Output Clock
S_DATA.............................................Bi-directional Serial Data
S_DIR.................................................Serial Data Direction Indicator
Trigger................................................Single multiplexed line containing external trigger
information
EXT_PWR .........................................External power output +5 Vdc @ 500 mA minimum
guaranteed 2 A maximum current limited
~TX0\TX0..........................................Differential 100 K ECL pair containing channel 0
transmit data
~TX1\TX1..........................................Differential 100 K ECL pair containing channel 1
transmit data
~RX0\RX0 .........................................Differential 100 K ECL pair containing channel 0
receive data
~RX1\RX1 .........................................Differential 100 K ECL pair containing channel 1
receive data
Testing
TEST ..................................................(Not used in normal operation) = GND
TEST_WR..........................................(Not used in normal operation) = GND

SIGNAL DEFINITION
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3.3 CSR Registers
The following list describes the internal registers of the Rehostable Adapter.
CSRs specific to the Rehostable Adapter have a description that starts with “Rehostable
Adapter”.
CSR0..................................................General SCRAMNet Control
CSR1..................................................SCRAMNet Errors
CSR2..................................................General SCRAMNet Control
CSR3..................................................Number of Nodes and Tx Node ID (Rx ID and
Transmitted AGE)
CSR4..................................................Interrupt FIFO Address (Lower 16 bits)
CSR5..................................................Interrupt FIFO Address (Upper 7 bits)
CSR6..................................................Not implemented in the Rehostable Adapter design
CSR7..................................................Not implemented in the Rehostable Adapter design
CSR8..................................................Rehostable Adapter ASIC extended control and status
CSR9..................................................Rehostable Adapter Error Interrupt MASK Register
CSR10................................................Rehostable Adapter Shared Memory Address and
ENABLE (LSW), replaces physical switches
CSR11................................................Rehostable Adapter Shared Memory Address
(MSW), replaces physical switches
CSR12................................................Rehostable Adapter Virtual Paging with Enable
CSR13................................................Rehostable Adapter General Purpose Counter/Timer
CSR14................................................Not implemented in the Rehostable Adapter design
CSR15................................................Not implemented in the Rehostable Adapter design
CSR16................................................Not implemented in the Rehostable Adapter design
See Appendix A for a detailed description of each CSR.

SIGNAL DEFINITION
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3.4 Detailed Description of Signals
This subsection provides a more detailed description of the Rehostable Adapter interface
signals. The signals are arranged in alphabetical order. The capacitance loading values for
each of the signals is contained in Table 3-8 Rehostable Adapter Signal Capacitance at
the end of the section.
ACR[7:0]
The ACR bus is a TTL level (asserted HI) set of signals provided from the memory
module during a memory access. These control various functions/features of the
Rehostable Adapter product. Table 3-1 shows the definitions of the use of the ACR bus.
Table 3-1 ACR Bus Definitions
Bit # Function
0 Receive Interrupt Enable
1 Transmit Interrupt Enable
2 External Trigger 1
3 External Trigger 2
4 HIPRO
5 External Trigger 3
(Internal Rehostable Adapter
ASIC 4 K only)
6 Undefined
~ACR_DOE
The ACR Data Output Enable signal is an active low TTL level signal that is sourced
from the Rehostable Adapter ASIC to the memory module. This signal instructs the
memory module to place ACR information onto the MD bus.
~ACR_WE
The ACR Write Enable signal is an active low TTL level signal that is sourced from the
Rehostable Adapter ASIC to the memory module. This signal instructs the memory
module to write the present data on the MD bus to the ACR location specified by the MA
bus.
A_D_LTCH
The A_D_LATCH signal latches several host-specific signals during a host-specific
transaction with the Rehostable Adapter ASIC. These signals are HD[31:0], HA[22:2],
R_W, TS[2:1] and TSP[2:0]. When A_D_LATCH occurs, these signals must be valid so
they may be latched. All latching occurs inside the Rehostable Adapter ASIC except for
latching HD[31:0] into the external pipeline registers.
BUSY
The BUSY signal is an active high TTL level signal sourced from the Rehostable Adapter
ASIC. This signal becomes active whenever reset activities start (that is, when ~RST_IN
goes low). This signal will remain active until reset processing is finished (that is, when
the configuration EEPROM is read).

SIGNAL DEFINITION
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CLK
The Clock signal is an active high TTL level signal sourced from the Rehostable Adapter
ASIC. This clock is used for the entire Rehostable Adapter bus and user interface timing.
It is a 37.5 MHz, 50% duty cycle-clock source. All Rehostable Adapter ASIC
transactions are synchronous to this clock.
CNTRL_STATUS[20,18,17,16,7]
These bus signals are TTL logic level HI sourced from the Rehostable Adapter ASIC. It is
a multiplexed bus that is based on the CS_MODE indicator. When CS_MODE is asserted
(TTL logic level HI), then the signals are defined as “non-network”. When CS-MODE
de-asserts (TTL logic level LOW), the CNTRL_STATUS will be in transition within two
host clocks.
Non-network required (user determined) CNTRL_STATUS signals should be “Flow
Through” latched on the CS_MODE signal. The CNTRL_STATUS bus may be latched in
the network mode with the signal NACK. Figure 3-1 shows the timing relationship
between CS_MODE and the CNTRL_STATUS bus. CS_MODE as shown only goes low
during a network cycle (shown by BGN [Bus Grant Network]). BGN, Label 1, causes
CS_MODE to go low. Only after the CS_MODE is low for at least one host Clock does
the CNTRL_STATUS bus change. Also, note from the timing that the CNTRL_STATUS
bus has setup and hold times defined from the NACK (Network Cycle Acknowledge)
signal; this is indicated by labels 5a and 5b. The rising edge of NACK can be used to
latch the CNTRL_STATUS bus, assuring there will be no setup or hold violations. The
falling edge of NACK causes CS-MODE to rise.
There are two fundamental definitions of each CNTRL_STATUS line. These definitions
correspond to network and non-network transactions occurring on the RehostableAdapter
bus. Table 3-2 defines the CNTRL_STATUS bus in each of the modes.
Table 3-2 Control Status Bus Definition
CNTRL_STATUS NETWORK (CS_MODE = 0) NON-NETWORK (CS_MODE = 1)
20 RX_F_WR (Page 3-12) TRIG3 (Page 3-13)
18 OID (Page 3-11) INT_RXFIFO (Page 3-9)
17 RX_INT (Page 3-12) INT_ERROR (Page 3-8)
16 RX_RETRY (Page 3-12) RD_CSR5 (Page 3-11)
7 Not Used INT_ARMED (Page 3-8)

SIGNAL DEFINITION
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Figure 3-1 CS-Bus and CS Mode Timing