Systran SCRAMNet SC150 Application guide

SCRAMNetÒSC150 Network
Rehostable Adapter
Hardware Reference
Document No. D-T-MR-REHOST##-A-0-A3

FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Systran reserves the right to make changes without notice.
Systran makes no warranty of any kind with regard to this printed material, including, but not limited to,
the implied warranties of merchantability and fitness for a particular purpose.
©Copyright 2000 Systran Corporation. All rights reserved.
SCRAMNetÒis a registered trademark of Systran Corporation. US Patent # 4,928,289.
Ôis a trademark of Systran Corporation.
TRI-STATEÒis a registered trademark of National Semiconductor Corporation.
References to products and/or services of other manufacturers as provided in this document do not constitute
endorsement by Systran Corporation.
Revised: April 18, 2000
Systran Corporation
4126 Linden Avenue
Dayton, OH 45432-3068 USA
[phone]

FCC
This product is intended for use in industrial, laboratory or military environments. This product uses and
emits electromagnetic radiation, which may interfere with other radio and communication devices. The
user may be in violation of FCC regulations if this device is used in other than the intended market
environments.
CE
As a component part of another system, this product has no intrinsic function and is therefore not subject
to the European Union CE EMC directive 89/336/EEC.

Copyright 2000 i SCRAMNet SC150 REHOSTABLE REFERENCE
TABLE OF CONTENTS
1. INTRODUCTION......................................................................................................................................1-1
1.1 How to Use This Manual..........................................................................................................1-1
1.1.1 Purpose...................................................................................................................1-1
1.1.2 Scope......................................................................................................................1-1
1.1.3 Style Conventions..................................................................................................1-1
1.2 Related Information..................................................................................................................1-1
1.3 Quality Assurance.....................................................................................................................1-2
1.4 Technical Support.....................................................................................................................1-2
1.5 Ordering Process.......................................................................................................................1-3
2. PRODUCT OVERVIEW ...........................................................................................................................2-1
2.1 Overview...................................................................................................................................2-1
2.2 Description................................................................................................................................2-1
2.3 Specifications............................................................................................................................2-1
3. SIGNAL DEFINITION..............................................................................................................................3-1
3.1 Overview...................................................................................................................................3-1
3.2 Pinout Description ....................................................................................................................3-1
3.3 CSR Registers...........................................................................................................................3-3
3.4 Detailed Description of Signals ................................................................................................3-4
4. DESIGN GUIDELINES.............................................................................................................................4-1
4.1 Overview...................................................................................................................................4-1
4.2 Software Compatibility.............................................................................................................4-1
4.2.1 Interrupt Vector Register........................................................................................4-1
4.2.2 Interrupt Pending and the SCRAMNet Interrupt system........................................4-1
4.2.3 SCRAMNet Memory and CSR mapping...............................................................4-1
4.3 Design Requirements................................................................................................................4-2
4.3.1 Transaction Definition ...........................................................................................4-2
4.3.2 Transaction Setup Information...............................................................................4-2
4.3.3 Transaction Start: HREQ and HREQ_PEND Handshake ......................................4-5
4.3.4 Transaction End: HACK Considerations................................................................4-6
4.4 Throughput considerations........................................................................................................4-6
4.4.1 User Throughput With No Network Traffic...........................................................4-6
4.4.2 User Throughput With Light Network Traffic.......................................................4-7
4.4.3 User Throughput With Heavy Network Traffic .....................................................4-8
4.4.4 User Throughput With Full Network Traffic .........................................................4-9
4.4.5 Conclusions And Comments................................................................................4-10
4.5 Optional Design Features........................................................................................................4-11
4.5.1 The SCRAMNet ASIC Interrupt System .............................................................4-11
4.5.2 The SCRAMNet ASIC Address Decoder and Its Application to the Rehostable
Adapter .........................................................................................................................4-13
5. REHOSTABLE INTERFACING...............................................................................................................5-1
5.1 Overview...................................................................................................................................5-1
5.2 Basic Rehostable VME Interface..............................................................................................5-1
5.3 Supported Features ...................................................................................................................5-1
5.3.1 Write Posting..........................................................................................................5-1
5.3.2 Quasi-dual Vector Interrupts..................................................................................5-1
5.3.3 8–, 16–, And 32–bit Transactions ..........................................................................5-1
5.4 Unsupported Features ...............................................................................................................5-1
5.5 System Architecture..................................................................................................................5-2
5.5.1 Buffer Blocks.........................................................................................................5-2
5.5.2 Data Un-justifier Block..........................................................................................5-2
5.5.3 Controller Interface Block......................................................................................5-3
5.5.4 Rehostable Adapter Block......................................................................................5-3
5.5.5 Media Card (“MAC”) Interface Block...................................................................5-4

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Copyright 2000 ii SCRAMNet SC150 REHOSTABLE REFERENCE
5.6 Controller..................................................................................................................................5-4
5.6.1 Address Decode .....................................................................................................5-4
5.6.2 Transaction Size and Position Encode ...................................................................5-5
5.6.3 Transaction Identification ......................................................................................5-6
5.6.4 Transaction Controller ...........................................................................................5-8
5.6.5 Interrupt Vector Register......................................................................................5-11
5.6.6 Interrupt Control Engine......................................................................................5-11
5.7 Memory Decoder....................................................................................................................5-12
5.7.1 Using The CSR decoder.......................................................................................5-12
5.7.2 Using the On-board Rehostable Adapter Memory Decoder.................................5-12
5.8 Memory Subsystems...............................................................................................................5-12
6. SERIAL LEDS SUPPORT CIRCUITRY...................................................................................................6-1
6.1 Overview...................................................................................................................................6-1
6.2 Interface....................................................................................................................................6-1
6.3 Serial Protocol...........................................................................................................................6-2
6.4 User Designs.............................................................................................................................6-5
6.5 Simple Receiver Design............................................................................................................6-6
6.6 Full Serial Port Design..............................................................................................................6-7
6.7 Cables .....................................................................................................................................6-13
APPENDICES
APPENDIX A – CSR Description.................................................................................................................A-1
APPENDIX B – VHDL Source Code ...........................................................................................................B-1
APPENDIX C – Specifications .....................................................................................................................C-1
APPENDIX D – Schematics..........................................................................................................................D-1
APPENDIX E – Hardware Assembly............................................................................................................E-1
APPENDIX F – Bill of Materials.................................................................................................................. F-1
GLOSSARY................................................................................................................................GLOSSARY-1
INDEX................................................................................................................................................. INDEX-1

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Copyright 2000 iii SCRAMalyzer User Manual
FIGURES
Figure 2-1 Rehostable Adapter......................................................................................................................2-1
Figure 3-1 CS-Bus and CS Mode Timing......................................................................................................3-6
Figure 4-1 HREQ and HREQ_PEND Handshake..........................................................................................4-5
Figure 4-2 Standard Interrupt Logic............................................................................................................4-12
Figure 4-3 Ultra-simple Interrupt Logic......................................................................................................4-13
Figure 4-4 Switch 1 .....................................................................................................................................4-14
Figure 5-1 Block Diagram 1..........................................................................................................................5-2
Figure 5-2 Block Diagram 2..........................................................................................................................5-3
Figure 6-1 Serial Protocol..............................................................................................................................6-3
Figure 6-2 Remote Device Serial Receiver....................................................................................................6-5
TABLES
Table 3-1 ACR Bus Definitions.....................................................................................................................3-4
Table 3-2 Control Status Bus Definition........................................................................................................3-5
Table 3-3 CSR_ME Bus Output Codes.........................................................................................................3-7
Table 3-4 MCI Bus Codes...........................................................................................................................3-10
Table 3-5 ~MWE Bus Lines and Byte-lanes ...............................................................................................3-11
Table 3-6 Transaction Types .......................................................................................................................3-14
Table 3-7 TSP Lines....................................................................................................................................3-14
Table 3-8 Rehostable Adapter Signal Capacitance......................................................................................3-15
Table 4-1 TS1/TS2 Values.............................................................................................................................4-3
Table 4-2 TSP Codes.....................................................................................................................................4-3
Table 4-3 HA Address Connections vs. Memory Size...................................................................................4-4
Table 4-4 Big-Endian 32-bit Formatting .......................................................................................................4-5
Table 4-5 MD Bus Bits Definition During Switch READ...........................................................................4-15
Table 4-6 CSR_ME[1:0] Line Definitions...................................................................................................4-15
Table 5-1 Data Un-justifier Transformations.................................................................................................5-2
Table 5-2 Memory Address Modifiers...........................................................................................................5-4
Table 5-3 VME Transactions and TSPx Codes .............................................................................................5-5
Table 5-4 CSR_I_O_Locations and Switch Settings...................................................................................5-12
Table 6-1 Count_modes.................................................................................................................................6-4

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Copyright 2000 1-1 SCRAMNet SC150 REHOSTABLE REFERENCE
1. INTRODUCTION
1.1 How to Use This Manual
1.1.1 Purpose
The purpose of this document is to aid the engineer integrating the SCRAMNet SC150
Rehostable Adapter to a specific design. This will be accomplished by defining the signal
interface, defining the interface requirements, and by showing an implementation
example. Information is also provided on memory subsystems and hardware assembly. A
section on LEDS Support Circuitry is also included.
.
NOTE: SCRAMNet SC150 (previously SCRAMNet+) is referred to in this manual as
“SCRAMNet.”
1.1.2 Scope
This document is intended for SCRAMNet network system engineers. To use this manual
effectively you need an understanding of the SCRAMNet network hardware.
1.1.3 Style Conventions
The following conventions are used in this document:
· TheCc symbol indicates that you must press the Ckey whileyou
simultaneously press another key (in this case, c).
· Names of files, parameters and commands are in bold type; for example,
sysconfigtab file.
· Names of called routines are followed by open and closed parentheses and are
printed in italics; for example, dma_read().
· Directory path names are in italics; for example, mkdir /usr/SCRAMNet.
· VHDL is boxed, Courier, 9 pt font.
· Hexadecimal values within paragraph text are written with the word hex
italicized and one point smaller than the context font following the value; for
example, 03FF hex.Hexadecimal values in tables or in code blocks may be
written using abbreviated notation; for example 0x03FF.
· CSR and ACR Register bits and bit ranges are specified by the register
identification followed by the bit or range of bits in brackets [ ]; for example,
CSR6[4], CSR3[15:0], ACR[2]
· In a prompt, square brackets indicate that the enclosed item is the default
response. For example, [y] means the default response is Yes.
1.2 Related Information
· SCRAMNet Network Media User’s Guide
(Document No. D-T-MU-MEDIA)
· SCRAMNet Utilities User Manual
(Document No. C-T-MU-UTIL)

INTRODUCTION
Copyright 2000 1-2 SCRAMNet SC150 REHOSTABLE REFERENCE
1.3 Quality Assurance
Systran Corporate policy is to provide our customers with the highest quality products
and services. In addition to the physical product, the company provides documentation,
sales and marketing support, hardware and software technical support, and timely product
delivery. Our quality commitment begins with product concept, and continues after
receipt of the purchased product.
Systran’s Quality System conforms to the ISO 9001 international standard for quality
systems. ISO 9001 is the model for quality assurance in design, development, production,
installation and servicing. The ISO 9001 standard addresses all 20 clauses of the ISO
quality system and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:
· Achieve, maintain and continually improve the quality of our products through
established design, test, and production procedures.
· Improve the quality of our operations to meet the needs of our customers,
suppliers, and other stakeholders.
· Provide our employees with the tools and overall work environment to fulfill,
maintain, and improve product and service quality.
· Ensure our customer and other stakeholders that only the highest quality product
or service will be delivered.
The British Standards Institution (BSI), the world’s largest and most respected
standardization authority, assessed Systran’s Quality System. BSI’s QualityAssurance
division certified we meet or exceed all applicable international standards, and issued
Certificate of Registration, number FM 31468, on May 16, 1995. The scope of Systran’s
registration is: “Design, manufacture and service of high technology hardware and
software computer communications products.” The registration is maintained under BSI
QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage
customers to contact us with questions, suggestions, or comments regarding any of our
products or services. We guarantee professional and quick responses to your questions,
comments, or problems.
1.4 Technical Support
Technical documentation is provided with all of our products. This documentation
describes the technology, its performance characteristics, and includes some typical
applications. It also includes comprehensive support information, designed to answer any
technical questions that might arise concerning the use of this product. We also publish
and distribute technical briefs and application notes that cover a wide assortment of
topics. Although we try to tailor the applications to real scenarios, not all possible
circumstances are covered.
Although we have attempted to make this document comprehensive, you may have
specific problems or issues this document does not satisfactorily cover. Our goal is to
offer a combination of products and services that provide complete, easy-to-use solutions
for your application.
If you have any technical or non-technical questions or comments (including software),
contact us. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight
Time.