Tadpole SPARCbook 3 series User manual

SP4RCbook™ 3 Series
Technical Reference
Manual
980327-02

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Issue 2.2 (Draft) of February 10, 1997
Part number 980327-02
© 1996, 1997 by Tadpole Technology
Printed in the
UK

Contents
About This Guide ix
Document Summary ..................................................... x
Definitions ........................................................... xi
Logic states ........................................................ xi
Data entities ....................................................... xi
Typographical conventions .............................................. xi
Chapter 1
1.1
Key presses, buttons, and field names ................................... xi
Solaris commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Notes, cautions and warnings ......................................... xii
Architecture Overview
Introduction .................................................... 1-2
1.2 Main Components ............................................... 1-2
1.2.1 Base board .................................................. 1-2
1.2.2 CPU module ................................................ 1-2
1.2.3 Microcontroller module ........................................ 1-3
1.2.4 Main display ................................................ 1-3
1.2.5 Other components ............................................ 1-3
1.3 System Architecture ............................................. 1-4
1.4 Processor ...................................................... 1-5
1.5 Main System Buses .............................................. 1-6
1.5.1 Memory bus ................................................. 1-6
1.5.2 SB us ....................................................... 1-6
1.5.3 Ebus ....................................................... 1-7
1.6 DRAM ........................................................ 1-8
1.7 Slow 1/0 Subsystem ............................................. 1-9
1. 7 .1 Serial Channels .............................................. 1-9
1.7.2 Counter-Timers .............................................. 1-9
1. 7 .3 Interrupt Controller .......................................... 1-10
1.7.4 EBus Interface and Controller .................................. 1-10
1.8 Fast 1/0 Subsystem ............................................. 1-10
1.8.1 SCSI Controller ............................................. 1-10
1.8.2 Ethernet Controller .......................................... 1-11
1.8.3 Parallel Port ................................................ 1-11
1.8.4 FIFOs and DMA Controller ................................... 1-11
1.9 Graphics and Video Subsystem
................................... 1-12
1.9.l Graphics Controller .......................................... 1-12
1.9.2 VRAM
.................................................... 1-12
1.9.3 RAMDAC, Panel Driver and Video Clock Generator ............... 1-12
1.10 MK48T08 RTCRAM ........................................... 1-13
1.11 ISDN and 16-Bit Audio Controller ................................. 1-13
1.12 PCMCIA Controller ............................................ 1-14
iii

1. 13 Modem Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.14 Microcontroller Subsystem 1-15
Chapter 2 The SPARC CPU
2.1 SPARC Architecture Overview .................................... 2-2
2.2 Integer Unit ................................................... 2-3
2.2. l Pipeline .................................................... 2-3
2.2.2 Instruction set overview ....................................... 2-3
2.2.3 Traps and interrupts .......................................... 2-4
2.2.4 Memory protection ........................................... 2-5
2.2.5 IU internal registers .......................................... 2-5
2.2.6 IU control registers ........................................... 2-6
2.3 Floating Point Unit .............................................. 2-7
2.3. l Floating Point Registers ....................................... 2-8
2.4 Cache Controller and Memory Management Unit ...................... 2-8
2.4. l Translation lookaside buffer .................................... 2-9
2.4.2 Address translation .......................................... 2-11
2.5 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.6 Instruction Cache .............................................. 2-14
2. 7 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.8 SBus Controller ............................................... 2-14
2.8.l Programmed I/0 ............................................ 2-15
2.8.2 DVMA ................................................... 2-15
Chapter 3
3.1
Memory Map and Interrupts
Address Map .................................................. 3-2
3.1.1 MACIO and SLAVIO Space (SBus Slot 4) ........................ 3-2
3.1.2 DRAM .................................................... 3-5
3.2 Interrupts ..................................................... 3-5
3.2.1 Interrupt Control ............................................. 3-7
3.3 NCR89C105 SLAVIO Configuration Control ......................... 3-9
3.3.1 SLAVIO Configuration Register ................................ 3-9
3.3.2 Diagnostic Messages ........................................ 3-10
3.3.3 Miscellaneous System Functions ............................... 3-11
Chapter 4
4.1 Serial Interface Serial Channel Assignment ....................................... 4-2
4.1.1 Serial Interface Control ....................................... 4-2
4.2 SCC Registers ................................................. 4-3
4.2.1 Register functions ............................................ 4-3
4.3 Baud Rate Clocks .............................................. 4-10
4.4 Handshakes ................................................... 4-10
iv

Chapter 5
5.1
5.2
SCSI Controller
Connecting SCSI Devices ......................................... 5-2
NCR53C9X SCSI Controller ...................................... 5-2
5.2.1 53C9X register set ............................................ 5-2
5.3 DMA Support .................................................. 5-7
Chapter 6
6.1
5.3.1 DMA Transfers .............................................. 5-7
5.3.2 DMA Registers .............................................. 5-7
5.3.3 SCSI Interrupts .............................................. 5-7
Ethernet Interface
NCR92C990 Overview ........................................... 6-2
6.1.1 Bus Interface ................................................ 6-2
6.1.2 LAN Interface ............................................... 6-2
6.1.3 Descriptor Management ....................................... 6-2
6.2 LAN Controller Registers
......................................... 6-3
6.2.1 Register Indexing ............................................. 6-3
6.2.2 Control and Status Register O ................................... 6-3
6.2.3 Control and Status Register l and 2 .............................. 6-4
6.2.4 Control and Status Register 3
................................... 6-5
6.3 DMA Support for Network Operations ............................... 6-5
Chapter 7
7.1 PCMCIA Interface
TS102 Architecture Overview ..................................... 7-2
7.1.1 SBus interface ............................................... 7-2
7.1.2 PCMCIA interface ............................................ 7-3
7.1.3 Microcontroller interface ....................................... 7-3
7.2 TS102 Memory Mapping ......................................... 7-4
7.2.1 Acceses to PCMCIA Resources ................................. 7-4
7.2.2 Byte Swapping ............................................... 7-5
7.2.3 SLAVIO expansion interface ................................... 7-6
7.3 TS102 Registers ................................................ 7-7
7.3.l Card A and B interrupt registers ................................. 7-8
7.3.2 Card status register ........................................... 7-9
7.3.3 Card Control Register ........................................ 7-11
7.3.4 Microcontroller Interrupt Register .............................. 7-12
7.3.5 Microcontroller data register ................................... 7-12
7.3.6 Microcontroller status register .................................. 7-12
7.4 Microcontroller Registers ........................................ 7-12
Chapter 8 ISDN and 16-bit Audio
8.1 ISDN Overview ................................................. 8-2
8.2 DBRI Overview ................................................ 8-2
8.2.1 TE and NT Ports ............................................. 8-3
8.2.2 CHI Port .................................................... 8-3
V

8.2.3 SBus Interface ............................................... 8-3
8.2.4 DBRI Programming Model .................................... 8-4
8.2.5 DBRI Internal Registers ....................................... 8- 7
8.2.6 DBRI Commands ........................................... 8-11
8.2.7 Data structures ............................................. 8-13
8.3 Audio CODEC ................................................ 8-14
8.3.1 Clocking and Data Synchronization ............................. 8-14
8.3.2 Control Mode .............................................. 8-17
8.3.3 Data Mode ................................................ 8-20
Chapter 9 MODEM
9.1 Internal Modem Overview ........................................ 9-2
9.2 Interface Control ............................................... 9-2
9.3 Modem Registers ............................................... 9-4
9.3. l Interrupt Enable Register ...................................... 9-4
9.3.2 Interrupt Identification Register ................................. 9-4
9.3.3 Line Status Register .......................................... 9-5
9.4 AT Command Set ............................................... 9-5
9 .5 S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6 Class 2 Fax Command Set ....................................... 9-27
Chapter 1O Parallel Interface
10.1 Parallel Port Overview .......................................... 10-2
10.1.1 Parallel Port DMA Operations ................................. 10-2
10.2 Parallel Port Control Registers .................................... 10-3
Chapter 11 Display Interface
vi
11.1 Display Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.1 Architecture ............................................... 11-2
11.1.2 Display Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.3 LCD Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2 Power 9100 User Interface Controller .............................. 11-5
11.2.1 Parameter engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.2.2 Drawing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.2.3 Frame buffer controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.2.4 SVGA unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.2.5 Power 9100 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.2.6 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.2.7 Video Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.2.8 VRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.2.9 Parameter engine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.2.1ODrawing engine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
l 1.2.11RAMDAC register accesses
................................. 11-20
11.3 Direct frame buffer access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20

11.4 RAMDAC ................................................... 11-21
11.4.l RAMDAC host interface
..................................... 11-22
11.4.2 Control register accesses
..................................... 11-22
11.4.3 Color palette accesses
....................................... 11-28
11.4.4 Pixel Formats
.............................................. 11-29
Chapter 12 Microcontroller Subsystem
12.l Microcontroller subsystem overview ............................... 12-2
12.1.l Normal operation
............................................ 12-3
12.1.2 Internal keyboard scanning
.................................... 12-4
12.1.3 External keyboard and mouse
.................................. 12-4
12.1.4 Pointing stick
............................................... 12-4
12.1.5 Real time clock
............................................. 12-4
12.1.6 EEPROM
.................................................. 12-4
12.1.7 LCD status display
.......................................... 12-5
12.2 Command Set
................................................. 12-6
12.2.l Command synchronization
.................................... 12-6
12.2.2 System Information Commands
................................ 12-6
12.2.3 Read/Write/Modify Commands
............................... 12-11
12.2.4 Commands Returning no Status
............................... 12-14
12.2.5 Block Transfer Commands
................................... 12-15
12.2.6 Generic Commands
......................................... 12-16
12.2.7 Generic Commands with Optional Status
........................ 12-17
12.2.8 Administration Commands
................................... 12-18
Appendix A Further Information
Appendix B Connector Information
B.l 1/0 Panel Connectors ............................................ B-2
B.1.1
DCin ...................................................... B-2
B.1.2 Parallel (S3XP, S3GX and S3TX)
................................ B-2
B.1.3 Parallel (S3 and S3LC)
........................................ B-3
B.1.4 Ethernet (S3XP, S3GX and S3TX)
............................... B-3
B.1.5 Ethernet (S3 and S3LC)
........................................ B-4
B.1.6 Video
...................................................... B-4
B.1.7 SCSI (S3XP, S3GX and S3TX)
................................. B-5
B.1.8 SCSI (S3 and S3LC)
.......................................... B-6
B.1.9 Keyboard/Mouse
............................................. B-6
B.1.10 Serial (x2)
.................................................. B-6
B.1.11 ISDN
...................................................... B-7
B.2 Cable Adapter Connectors
........................................ B-8
B.2.1 Parallel Cable Adapter
......................................... B-8
B.3 Removable Hard Drive SCSI Connector
............................. B-9
vii

viii

Note
About This Guide
The SPARCbook 3 Technical Reference Manual is
written for the hardware engineer wishing to carry
out service
or repairs, and at the software engineer
wishing to implement hardware drivers. It is
assumed that you are familiar with the operation
of
SPARCbook 3, as detailed in the SPARCbook 3
User Guide, and that you have an understanding
of
computer hardware.
The SPARCbook 3 Technical Reference Manual covers all
models of SPARCbook 3. Where information for one model
differs to information for another model, this is indicated in the
text.

Document Summary
X
The SPARCbook 3 Technical Reference Manual comprises the following
chapters:
• Chapter 1 , Architecture Overview, discusses the main features of the
SPARCbook 3 and introduces the main hardware devices that provide
control over the SPARCbook
3's operations. The internal architecture
of SPARCbook 3 is described, showing how the major devices are
connected together.
• Chapter
2, Microprocessor, provides an overview of the SPARC
processor.
• Chapter
3, Memory Map and Interrupts, describes the addressing
architecture and the interrupt architecture
of the SPARCbook 3.
• Chapter 4 , Serial Interface, discusses the serial interface of the
SPARCbook 3.
• Chapter 5, SCSI Communications, discusses the SCSI controller.
• Chapter 6, Ethernet Interface, discusses the Ethernet interface
of the
SPARCbook 3.
• Chapter 7,
PCM CIA, discusses the PCMCIA interface implemented in
the SPARCbook
3.
• Chapter 8, ISDN and I6-BitAudio Controller, discusses the ISDN and
16-bit audio controller.
• Chapter 9, Modem, discusses the internal modem on the SPARCbook
3.
• Chapter 10, Parallel Interface, discusses the parallel interface on the
SPARCbook 3.
• Chapter 11, Display Interface, discusses the display interface
implemented in the SPARCbook 3. The discussion is centered on the
Brooktree Bt445 RAMDAC, on which the interface is based.
• Chapter 12, Microcontroller Subsystem, discusses the microcontroller
subsystem. This is used to provide internal control over such things
as
the display brightness, keyboard and mouse scanning and power
management.