TDK mPOL EV1703-3300-A User manual

Page 1 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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EV1703-3300-A
EVALUATION BOARD
USER GUIDE

Page 2 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
7
03
-
33
00
-
A
In roduc ion
This user guide describes the evaluation board provided for the FS1703 µPOL™ product.
The board generates an output voltage (V
OUT
) of 3.3V for loads of 0–3A from an input voltage (PV
IN
) of 5V.
Specifica ions
 Input voltage (PV
IN
) = +5V
 Output voltage (V
OUT
) = +3.3V
 Output load (I
O
) = 0–3A
 Switching frequency (F
SW
) = 5 0 kHz
 Output capacitance (C
O
) = 3x22µF (MLCC)
 In put capacitance (C
IN
) = 2x22µF (MLCC)
 Dimensions (width x length x thickness) = 63 x 4 x 1.5mm
Connec ions
Name Iden ifier Descrip ion
PV
IN
J1 Input voltage (+5V)
GND J2 Ground for input voltage
V
OUT
J Output voltage (+3.3V)
GND J7 Ground for output voltage
V
CC
TP2 Internal supply (V
CC
) – output of an LDO regulator
GND TP3 Ground for internal supply
En TP11 Enable
PG TP12 Power Good
The board is configured for a single input supply. An internal low drop-out regulator generates the internal supply (V
CC
)
from PV
IN
. The Enable (En) input is connected to PV
IN
through a resistor divider, so that no Enable signal is needed.
Opera ion
To use the evaluation board:
1. Connect a well-regulated +5V input supply to PV
IN
(J1) and GND (J2).
2. Connect a load of 0–3A to V
OUT
(J ) and GND (J7).

Page 3 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
7
03
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33
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Descrip ion
The evaluation board consists of a 4-layer PCB made from FR4 glass-reinforced epoxy laminate material. All layers use
2oz copper (equating to a thickness of 0.0694mm). The major power components, including the FS1703, are mounted
on the top side of the board.
Par reference Quan i y Type Descrip ion
FS1703 µPOL 1 – Main IC
C10, C21 2 22µF 0 05, 16V, X5R
C12 1 0.1µF 0402, 16V, X7R
C13 1 6 µF 25V
C14, C15, C16 3 22µF 0 05, 6.3V, X5R
C26 1 1µF 0603, 25V, X5R
J1 1 Red Banana connector
J2, J7 2 Black Banana connector
J 1 Green Banana connector
J10, J11 2 – 3-pin header
R1 1 2.7Ω 10%, 1/ W, 0 05 case size
R3, R7 2 49.9kΩ 10%, 1/ W, 0 05 case size
R2, R4, R9 3 0Ω 0 05 case size
C2 , C29 2 0Ω (Note 1) 0402 case size
R6 1 24.9kΩ 10%, 1/ W, 0 05 case size
VIN, PG, EN, VCC, SW_NC15, VOUT, PVIN, GNDs 10 – Test points
Note 1: 0ohm is placed on capacitor footprint to ground NC pin.
Figure 1 shows the layout of the board and Figure 2 shows a schematic of the electrical circuit.

Page 4 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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Figure 1 Board layout

Page 5 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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Figure 2 Schematic

Page 6 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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33
00
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A
Typical performance
Figure 3 to Figure 14 show typical operating waveforms for the evaluation board, while Figure 15 shows a
thermal image of the board in operation. In all cases, the board is operating at room temperature with no
airflow; PV
IN
is 5V, V
OUT
is 3.3V and I
O
is 0–3A.
Figure 3 Startup with no load (Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)

Page 7 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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Figure 4 Startup with 3A load (Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)
Figure 5 Shutdown with VCC UVL at 3A load (Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)

Page 8 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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33
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Figure 6 Soft turn off at 3A (Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)
Figure 7 Startup into pre-bias (Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)

Page 9 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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33
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Figure 8 ver-current protection and auto-recover to 3A
(Ch1: PV
IN
, Ch2: V
UT
, Ch3: PG, Ch5: Enable, Ch8: I
UT
)
Figure 9 Sw and V
UT
ripple at 0A (Ch2: V
UT
Ripple, Ch4: Sw)

Page 10 Rev 1.0, Jun 1, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 201 –20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
EV1
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03
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Figure 10 Sw and V
UT
ripple at 3A (Ch2: V
UT
Ripple, Ch4: Sw)
Figure 11 Transient response 0A to 1.5A (Ch2: V
UT
rIpple, Ch3: I
UT
), peak-peak deviation = 89mV