Terasic HSMC-NET User manual

HSMC-NET
Terasic HSMC-NET Daughter Board
User Manual

I
CONTENTS
Chapter 1 Introduction...............................................................................................................2
1.1 Features..........................................................................................................................................2
1.2 About the KIT.................................................................................................................................3
1.3 Assemble the HSMC-NET Board....................................................................................................4
1.4 Getting Help...................................................................................................................................5
Chapter 2 Architecture ..............................................................................................................6
2.1 Layout and Componets ...................................................................................................................6
2.2 Block Diagram ...............................................................................................................................7
Chapter 3 Board Components....................................................................................................9
3.1 The HSMC-NET Connector............................................................................................................9
3.2 I2C Serial EEPROM.....................................................................................................................15
Chapter 4 Demonstrations....................................................................................................... 16
4.1 Introduction..................................................................................................................................16
4.2 How the Demonstration is built.....................................................................................................17
4.3 System Requirements ...................................................................................................................25
4.4 Setup the Demonstration...............................................................................................................25
4.5 Demo Operation ...........................................................................................................................26
4.6 Overview......................................................................................................................................28
4.7 Nios Program................................................................................................................................29
Chapter 5 Appendix ................................................................................................................ 31
5.1 Revision History...........................................................................................................................31
5.2 Always Visit HSMC-NET Webpage for New Main board..............................................................31

2
Chapter 1
Introduction
The Terasic HSMC-NET is a Gigabit Ethernet transceiver with a High Speed Mezzanine Connector
(HSMC) interface. It offers network transfers of up to 1 Gbps with the host board using a HSMC
connector. Also, it provides a fully integrated Ethernet solution enabling fast implementation design,
shortening development times, and allows you to focus on the core functions of the system design.
Lastly, the HSMC-NET can be connected any HSMC/HSTC interfaces.
1
1. .1 1 F Fe ea at tu ur re es s
Figure 1-1shows the photo of the HSMC-NET board. The important features are listed below:
One HSMC connector for interface conversion, which is fully compatible with Cyclone III
Starter Kit and DE3 host boards
Duel-Port Integrated 10/100/1000 Gigabit Ethernet transceiver Supports GMII/MII/RGMII/TBI
MAC interfaces for direct connection to a MAC/Switch port
Dynamically configurable to support 10Mbps, 100Mbps (Fast Ethernet) or 1000Mbps (Gigabit
Ethernet) operation
Uses standard Cat 5 UTP (unshielded twisted pair) cabling
Requires a 25-MHz reference clock driven from a dedicated oscillator
Complete Reference Designs

3
Figure 1-1 The HSMC-NET board
1
1. .2 2 A Ab bo ou ut t t th he e K KI IT T
This section describes the package content
HSMC-NET board x 1
System CD-ROM x 1
The CD contains technical documents of the HSMC-NET, and one reference design along with the
source code.
Figure 1-2 HSMC-NET Package

4
1
1. .3 3 A As ss se em mb bl le e t th he e H HS SM MC C- -N NE ET T B Bo oa ar rd d
This section describes how to connect the HSMC-NET daughter board to a main board, and using
DE3 as an example shown in Figure 1-4.
The HSMC-NET daughter board connects to the main boards through the HSMC interface. For the
DE3, the HSMC-NET can be connected to any DE3‟s four HSTC connectors using a THCB-HFF
adapter card (Figure 1-3) which can be found in the DE3 package.
Figure 1-3 THCB-HFF adapter card
Figure 1-4 The DE3 board connected to the HSMC-NET daughter board

5
Note. Do not attempt to connect/remove the HSMC-NET daughter board to/from the main the main board
when the poweris on, or else the hardware could be damaged.
1
1. .4 4 G Ge et tt ti in ng g H He el lp p
Here are some places to get help if you encounter any problem:
Email to [e-mail]
Taiwan & China: [phone]
Korea : [phone]
Japan: [phone]

6
Chapter 2
Architecture
This Chapter covers the architecture of the HSMC-NET board including its PCB and block
diagram.
2
2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
The picture of the HSMC-NET board is shown in Figure 2-1 and Figure 2-2. It depicts the layout
of the board and indicates the location of the connectors and key components.
Figure 2-1 The HSMC-NET PCB and component diagram

7
Figure 2-2 The HSMC-NET Back side –HSMC connector view
The following components are provided on the HSMC-NET board :
Ethernet Transceiver (J2/J3)
25MHz Oscillator (Y1/Y2)
HSMC expansion connector (J1)
Marvell 88E1111 Ethernet Device (U2/U3)
Voltage Regulator (REG1/REG2)
I2C EEPORM (U1)
LED/Configuration
2
2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m
Figure 2-3 shows the block diagram of the HSMC-NET board

8
Figure 2-3 The block diagram of the HSMC-NET board

9
`
Chapter 3
Board Components
This section illustrates the detailed information of the components, connector interfaces, and the pin
mapping tables of the HSMC-NET board
3
3. .1 1 T Th he e H HS SM MC C- -N NE ET T C Co on nn ne ec ct to or r
This section describes pin definition of the HSMC-NET interface onboard
All the control and data signals of the Ethernet transmitter and receiver are connected to the HSMC
connector, so users can fully control the HSMC daughter board through the HSMC interface. Power
is derived from 3.3V and 12V of the HSMC connector.

10

11

12
Figure 3-1 The pin-outs on the HSMC connector
The Table 3-1 below lists the HSMC signal direction and description.
Note. The power pins are not shown in the Table 3-1

13
Table 3-1 The pin assignments for the HSMC connector (J1)
Signal Name
HSMC Pin
Direction
Description
Number
NET1_S_RX_p
42
Input
SGMII receive data positive (Ethernet 1)
NET1_S_RX_n
44
Input
SGMII receive data negative (Ethernet 1)
NET1_RX_CRS
47
Input
Carrier Sense pin (Ethernet 1)
NET1_S_TX_p
48
Output
SGMII transmit data postive (Ethernet 1)
NET1_RX_D7
49
Input
Receive code group bit 7 (Ethernet 1)
NET1_S_TX_n
50
Output
SGMII transmit data negative (Ethernet 1)
NET1_RX_D1
53
input
Receive code group bit 1 (Ethernet 1)
NET1_RX_D5
55
input
Receive code group bit 5 (Ethernet 1)
NET1_RX_D2
56
input
Receive code group bit 2 (Ethernet 1)
NET1_RX_D6
59
input
Receive code group bit 6 (Ethernet 1)
NET1_RX_D0
60
input
Receive code group bit 0 (Ethernet 1)
NET1_RX_D3
61
input
Receive code group bit 3 (Ethernet 1)
NET1_RX_D4
62
Input
Receive code group bit 4 (Ethernet 1)
NET1_RX_COL
65
input
GMII and MII Collision pin (Ethernet 1)
NET1_RX_DV
66
input
Receive data valid pin (Ethernet 1)
NET1_LED_LINK1000
67
input
Parallel LED output for link indicator
(Ethernet 1)
NET1_RX_CLK
68
input
Receive Clock provides a clock reference
(Ethernet 1)
NET1_TX_D1
71
output
Transmit code group bit 1 (Ethernet 1)
NET1_TX_CLK
72
input
Provides a clock reference (Ethernet 1)
NET1_TX_D5
73
output
Transmit code group bit 5 (Ethernet 1)
NET1_RX_ER
74
input
Receive Error pin (Ethernet 1)
NET1_TX_ER
77
output
Transmit Error Pin (Ethernet 1)
NET1_TX_D6
78
output
Transmit code group bit 6 (Ethernet 1)
NET1_TX_EN
79
output
Transmit Enable (Ethernet 1)
NET1_TX_D7
80
output
Transmit code group bit 7 (Ethernet 1)
NET1_TX_D0
83
output
Transmit code group bit 0 (Ethernet 1)
NET1_RESETn
84
output
Hardware reset active low (Ethernet 1)
NET1_TX_D4
85
output
Transmit code group bit 4 (Ethernet 1)
NET1_MDC
86
output
Management data clock reference
(Ethernet 1)
NET1_MDIO
89
inout
Management data pin (Ethernet 1)
NET1_TX_D2
90
output
Transmit code group bit 2 (Ethernet 1)
NET1_INTn
91
output
Polarity pin (Ethernet 1)
NET1_TX_D3
92
output
Transmit code group bit 3 (Ethernet 1)
NET1_GTX_CLK
95
output
Transmit Clock (Ethernet 1)

14
NET0_S_CLKp
96
input
SGMII 625 MHz positive receive clock
(Ethernet 0)
NET0_GTX_CLK
97
output
Transmit Clock (Ethernet 0)
NET0_S_CLKn
98
input
SGMII 625 MHz negative receive clock
(Ethernet 0)
NET0_RX_D2
101
input
Receive code group bit 2 (Ethernet 0)
NET0_LED_LINK1000
102
input
Parallel LED output for link indicator
(Ethernet 0)
NET0_RX_D0
103
input
Receive code group bit 0 (Ethernet 0)
NET0_RX_CRS
104
input
Carrier Sense pin (Ethernet 0)
NET0_RX_DV
107
input
Receive data valid pin (Ethernet 0)
NET0_RX_D7
108
input
Receive code group bit 7 (Ethernet 0)
NET0_TX_D5
109
output
Transmit code group bit 5 (Ethernet 0)
NET0_RX_D4
110
input
Receive code group bit 4 (Ethernet 0)
NET0_TX_D7
113
output
Transmit code group bit 7 (Ethernet 0)
NET0_RX_COL
114
input
GMII and MII Collision pin (Ethernet 0)
NET0_RX_ER
115
input
Receive Error pin (Ethernet 0)
NET0_RX_D6
116
input
Receive code group bit 6 (Ethernet 0)
NET0_TX_ER
119
output
Transmit Error Pin (Ethernet 0)
NET0_RX_D5
120
input
Receive code group bit 5 (Ethernet 0)
NET0_TX_EN
121
output
Transmit Enable (Ethernet 0)
NET0_RX_D3
122
input
Receive code group bit 3 (Ethernet 0)
NET0_TX_D0
125
output
Transmit code group bit 0 (Ethernet 0)
NET0_RX_D1
126
input
Receive code group bit 1 (Ethernet 0)
NET0_TX_D4
127
output
Transmit code group bit 4 (Ethernet 0)
NET0_RX_CLK
128
input
Receive Clock provides a clock reference
(Ethernet 0)
NET0_TX_D6
131
output
Transmit code group bit 6 (Ethernet 0)
NET0_TX_CLK
132
input
Provides a clock reference (Ethernet 0)
NET0_MDIO
133
inout
Management data pin (Ethernet 0)
NET0_TX_D1
134
output
Transmit code group bit 1 (Ethernet 0)
NET0_MDC
137
output
Management data clock reference
(Ethernet 0)
NET0_TX_D2
138
output
Transmit code group bit 2 (Ethernet 0)
NET0_INTn
139
output
Polarity pin (Ethernet 0)
NET0_TX_D3
140
output
Transmit code group bit 3 (Ethernet 0)
NET0_RESETn
146
output
Hardware reset active low (Ethernet 0)
NET0_S_RX_p
149
input
SGMII receive data positive (Ethernet 0)
NET0_S_RX_n
151
input
SGMII receive data negative (Ethernet 0)
NET0_S_TX_p
155
output
SGMII transmit data postive (Ethernet 0)
NET1_S_CLKp
156
input
SGMII 625 MHz positive receive clock

15
(Ethernet 1)
NET0_S_TX_n
157
output
SGMII transmit data negative (Ethernet 0)
NET1_S_CLKn
158
input
SGMII 625 MHz negative receive clock
(Ethernet 1)
3
3. .2 2 I I2 2C C S Se er ri ia al l E EE EP PR RO OM M
This section describes the I2C Serial EEPROM on the HSMC-NET board
The HSMC-NET board provides an EEPROM (U1) which is configured by the I2C interface. The
size of the EEPROM is 2K-bit which can store MAC information or user‟s data. The Default I2C
slave address is „0xA0‟. The detailed pin description between the HSMC connector and EEPROM
is shown below in Figure 3-2.
Figure 3-2 The block diagram of the EEPROM and HSMC connector
Table 3-2 The pin assignments of the EEPROM (U1)
Table 3.2 The pin assignments of the EEPROM
(U1)
EEPROM Pin
EEPROM Signal
HSMC Pin
HSMC Signal Name
Number
Name
Number
5
HSMC_SDA
33
HSMC_SDA
6
HSMC_SCL
34
HSMC_SCL

16
Chapter 4
Demonstrations
This chapter illustrates how to build a simple socket server created in Nios II
4
4. .1 1 I In nt tr ro od du uc ct ti io on n
This section describes the functionality of the demonstration briefly.
In this demonstration, we use DE3 as the host board connected to the HSMC-NET daughter board.
However, the HSMC-NET and Cyclone III FPGA Starter Kit Demo is also available in the
HSMC-NET CD-ROM.
We will illustrate how to create a simple socket server generated in Nios II using the Ethernet
daughter board with the DE3 host board. As indicated in the block diagram in Figure 4-1, the Nios
II processor is used to communicate with the Client via 88E1111 Ethernet Device.

17
Figure 4-1 Block diagram of demonstration
As Part of the Nios II, NicheStack TCP/IP Network Stack is a software suite of networking
protocols designed to provide an optimal solution for designing network-connected embedded
devices with the Nios II processor. A telnet client application is used to communicate with the
simple socket server issuing commands over a TCP/IP socket to the Ethernet-connected NicheStack
TCP/IP Stack running Nios II on the DE3 host board with a simple socket server. The Simple
Socket Server continues to listen for commands on a TCP/IP port and operates the DE3 LEDs
according to the commands from the telnet client.
NicheStack TCP/IP stack uses the MicroC/OS-II RTOS multithreaded environment to provide
immediate access to a stack for Ethernet connectivity for the Nios II processor. The Nios II
processor system contains an Ethernet interface, or media access control (MAC).
4
4. .2 2 H Ho ow w t th he e D De em mo on ns st tr ra at ti io on n i is s b bu ui il lt t
The section describes the steps using Quartus II, Nios II, and SOPC builder in generating the
demonstration.
The demonstration is setup using the DE3 System builder (v1.4.2) by configuring the DE3 I/O
components and also building a connection between DE3 and HSMC-NET. In DE3 configuration
we enabled the IO HSTC connector Group C to connect to the HSMC-NET shown in Figure 4-2.
Also, we want to enable the IO Group B connector to use the DDR2 SO-DIMM, in addition
enabling LED, Seg7 and Button which are used in the demonstration.

18
Figure 4-2 System Builder DE3 Configuration
Next we want to add the Ethernet board to our system builder and establish a connection with the
DE3 board shown in Figure 4-3. The I/O standard voltage for the HSMC-NET daughter board is
2.5V. Once the connection is established between DE3 board and HSMC-NET board, the DE3
System builder will change the I/O standard of the connector to fit with the daughter board
automatically. The I/O standard of the HSTCC male connector has been changed from 3.3-V
LVTTL to 2.5V. Also, the DDR2_SODIMM component is added in the board list by building a
connection with the DE3 board.

19
Figure 4-3 Note: A2.5V standard voltage must be used for the HSMC-NET daughter board)
The following step we use the SOPC builder to create our SOPC. The SOPC includes the CPU
processor, On-Chip memory, DDR2 controller, JTAG UART, system ID, timer, Triple-Speed
Ethernet, Scatter-Gather DMA controller and peripherals which are linked together contained in the
Nios II hardware system that are used when building a project.
In the Triple-Speed Ethernet IP Core configuration, the interface is set to GMII interface as well as
using the internal FIFO shown in Figure 4-4.