TES 1381 User manual

Taylor Electronics Services www.tayloredge.com C 2009
Specifications: 1381/1383 Clock Timer Controller Rev 2010/05/16
Fig 1: 1383 Horizontal timer module
The TES 1381/1383 timer controller modules provide a simple way to extend the operating
life for battery powered nixie clocks based on the SmartNixie family while providing an entertaining
hands free display capability. A very low power micro-processor on these modules supports three
modes of operation:
1. Pressing an enable button immediately powers a connected clock to display the time.
2. The processor counts time to operate the clock at various specific intervals.
3. The connected clock can be set to display continuously.
When a connected clock is powered on, the timer module acts as an I2C slave on the clock
communication bus to which the clock master, the 10s of hours module, updates along with the
other display modules the current time. When the timer module prepares to power down the clock,
it uses the last updated time information to compute the delay until the next display interval. The
timer counts down this delay using a very low power oscillator... current consumption of the entire
timer module in this "Waiting" mode is less than 50uA at 9V input.
Since the maximum time between wakeups is no more than one hour (The maximum interval
in the automatic display mode), the accuracy of the timer clock only has to be trimmed close enough
so as to not loose more than 1/2 second per hour.
A SmartNixie RTC is used to count the real-time displayed on the clock and so it is trimmed
for long term accuracy. The RTC has its own battery to maintain the correct time which is charged
when ever the clock is turned on... So long as the time is displayed periodically, the RTC battery
will remain charged indefinitely since this battery charges much-much faster than it discharges.
Introduction

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Specifications: 1381/1383 Clock Timer Controller
Interval Select Switch
0
Setting
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Display Behavior
On when button pressed
Interval 45 seconds
1 minute
90 seconds
2
3
5
4
minutes
minutes
minutes
minutes
6 minutes
10 minutes
12 minutes
15 minutes
20 minutes
30 minutes
60 minutes
Always on
1381: Vertical
timer module 1383: Horizontal timer module
Interval Duration Interval Duration
Table 1: Interval switch settings
Fig 3: Module switch locations
Fig 2: Application schematic
1381/1383 module
Battery
3 to 12V
(12V= Abs-Max)
9VIN
/ENABLE
GND
9VOUT
VDDOUT
SDA
GND
SCL SmartNixie
Clock
HVPS
SDA
SCL
GND
VDD HVIN
330uF
16V
IN
EN HVOUT GND
VDD
A1
A0 (1PPS)
3.94V, 90mA*
N/C
*See Fig 4 for
VDD curve
Iout @ 9VOUT 3A Max,
1A nominal

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Specifications: 1381/1383 Clock Timer Controller
Fig 4: VDD regulator transfer function
Vdropout = 0.5V
(Max at 90mA load)
"9VIN"
1
2
4
6
8
9VIN / VDD - Volts
10
12
14
16
"VDD"
3.94V
Nominal
12V
Abs-Max
Clock Vdd
Min = 2.5V
The regulator in the timer module has a dropout of 200mV
with no external load and 500mV max when an external load of
90mA (Maximum allowed) is connected and is specified as the
sum of the current from both the static VDD and switched
VDDOUT terminals.
Do not apply more than 1uF of external capacitance to the
VDDOUT pin without matching that amount x10 at the VDD pin
to prevent the VDDOUT load capacitance from browning out
the VDD rail when VDDOUT is switched on.
The regulator power limit is approximately 0.6W at 25C
derated to 0.0W at 125C and ultimately determines the
maximum allowable load current at any particular input
voltage or ambient temperature.
Fig 5: Interval timing diagram (Interval Setting "C" example)
9VOUT
VDDOUT
250mS
Wake
Duration-Seconds
12:20
Duration-Seconds
250mS
Duration-Seconds Duration-Seconds
12:40
Interval = 20 minutes
(See Table 1)
The following applies for interval selections from 1 to E (1 to 14): The hour is split into even units based on the
selected interval switch setting and the display will be turned on such that the center of the "Duration" period will be
exactly aligned. If for instance a duration of 5 and an interval of C is selected, the display will turn on 5 seconds before
12:20 and remain on until 5 seconds after 12:20. The display will turn on again just before 12:40, just before 1:00 and
so on. Pressing the enable button (On the user PWB) displays the current time immediately and turns the display off as
soon as the button is released. Manual display of the time will not alter the next programmed display period, i.e. the
display will come on automatically in the example below at 12:40 even if the enable button was pressed at 12:31.

Taylor Electronics Services www.tayloredge.com C 2009
Specifications: 1381/1383 Clock Timer Controller
1 3 5 7 9
24 6 8 10 12
11
Switches
A0 (1PPS) /ENABLE
A1
N/C
SCLSDA
Top View
GND VDDSW 9VIN
VDD
GND
9VOUT
Fig 6: 1381 Vertical timer module parts placement
Fig 7: 1381 Connector signal names

Taylor Electronics Services www.tayloredge.com C 2009
Specifications: 1381/1383 Clock Timer Controller
A0 (1PPS) A1 /ENABLE SDA SCL GND VDDSW
VDD
9VOUT
9VIN
Fig 8: 1383 Horizontal module parts placement and connector signal names

Taylor Electronics Services www.tayloredge.com C 2009
Specifications: 1381/1383 Clock Timer Controller
Fig 9: 1381 Vertical module schematic (References except for the connector are the same for both versions)
2008
DRAWN CHECKED ENGINEER PROJENGINEER APPROVED QA
APPROVALS DATE
SIZE
B
SCALE
NONE
SHEET
DRAWING NO. REV.FSCMNO.
11
OF
TITLE
SmartNixie Sleep Controller
JTAYLOR
2008/04/20
-
1381.DSN
APPROVED DATEREV DESCRIPTION
REVISION HISTORY
NOTES: UNLESS OTHERWISE SPECIFIED
c
Taylor Electronics
Services
3.94V
9 8 7 6 5 4 3 2 1 10 11 12
P1
GND
VDD
A0/DT A1/CK
ENABLE
N/C
SCL
SDA VDD
GND
GND
VDD
R1 100K
Power
1 2 3 4 5 6
ICSP Connection
+5V GND LVP CLOCK DATA GND +5V VPP
ICSP VDDSW
GND 9VIN
9VOUT
A1
N/C
SDA VDD
9VOUT
GND
A0
ENABLE
GND SCL 9VIN
VDDSW
1 3 5 7 9
1112
10
8 6 4 2
R2 2.2K R3
2.2K
VDDSW
VDD
1
RA5/T1CKI/OSC1/CLKIN
2
RA4/AN3/T1G/OSC2/CLKOUT
3
RA3/MCLR/VPP
4
RC5 5
RC4/ C2OUT 6
RC3/AN7/C12IN3- 7
RC6/AN8/SS 8
RC7/AN9/SDO 9
RB7 10
RB6/SCK/SCL
11
RB5/AN11 12
RB4/AN10/SDI/SDA
13
RC2/AN6/C12IN2- 14 RC1/AN5/C12IN1- 15
RC0/AN4/C2IN+ 16
RA2/AN2/T0CKI/INT/C1OUT 17
RA1/AN1/C12IN0-/VREF/ICSPCLK
18
RA0/AN0/C1IN+/ICSPDAT/ULPWU
19
VSS
20
U1 PIC16F677
GND
Y1 32.768KHz
C2 33PF
C3 33PF
Q1 BSS138
Q2 BSS138
GND
GND
4
651 2
3
Q3 FDC640P
4
651 2
3
Q4 FDC640P
VDD VDDSW
9VSW
9VIN
9VSW 9VIN
VIN
1
BYP 3
VOUT 5
FB 4
GND
2
U2 LT1761ES5-BYP
R4 1M R5 453K
GND
GND
C4 10uF/16V
C5 10uF/16V
GND GND
9VIN
DURATION
INTERVAL
RN1:A
RN1:B
RN1:C
RN1:D
RN2:A
RN2:B
RN2:C
RN2:D
4
0 8
C
2
1
3
65
7
A
B
9
EF
D
C1 2
4
3
2
4
1
1
8
6C2 5
SW1 P36S103(6)
4
0 8
C
2
1
3
65
7
A
B
9
EF
D
C1 2
4
3
2
4
1
1
8
6C2 5
SW2 P36S103(6)
R6 100K
R7 100K
2 4 6 8
10 12
Switches on opposite side

Top View
Taylor Electronics Services www.tayloredge.com C 2009
Specifications: 1381/1383 Clock Timer Controller
Fig 10: 1381 Mechanical outline (Inches)
Fig 11: 1383 Mechanical outline (Inches)
0.000
0.000
0.075 0.175 0.275 0.375 0.675 0.775 0.875 0.950
0.050
0.900
0.950
0.025 Sq pins 10
plcs, use 0.042 dia
PWB holes
Provide clearance on user PWB
from other signals around pins as
indicated, 0.100 dia typical.
Some signals are exposed
on underside, use caution
for placement of unmasked
copper on user PWB.
0.950 0.200
(Nom)
0.062
(Nom)
0.250
(Max)
0.000
-0.100
(Nom)
-0.300
(Nom)
0 0
0.155
0.570
0.000 0.495 0.650
0.800
0.075 0.175 0.275 0.375 0.475 0.575
0.025 Sq pins 10
plcs, use 0.042 dia
PWB holes
0 0
0.715
0.375 0.675
0.000 0.050
-0.050
0.250
(Max)
-0.100
(Max)
0.062
(Nom)
Interval
Interval Duration
Interval Duration