Tews Technologies TAMC900 User manual

The Embedded I/O Company
TAMC900
AMC with 8 high Speed ADCs 105MSps, 14Bit
Version 2.0
User Manual
Issue 2.0.1
April 2010
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TAMC900 User Manual Issue 2.0.1 Page 2 of 71
TAMC900-10R
AMC with 8 high speed ADCs 105 MSps 14 bit,
RoHS compliant. Requires Signal Conditioning
Adapter
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‘Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
©2008 – 2010 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TAMC900 User Manual Issue 2.0.1 Page 3 of 71
Issue Description Date
1.0 Initial Issue April 2008
1.1 Minor changes in chapter 9
Added details to chapter 4.3 May 2008
1.2 Corrections in “Crosspoint Switch Control Register “
Different minor corrections and additions August 2008
1.0.3 New User Manual Issue Notation
Correction of “MMC JTAG Connector Pin Assignment” January 2009
2.0.0 Update to TAMC900 V2.0
Added FPGA code description November 2009
2.0.1 Firmware Upgrade to Version 2 April 2010

TAMC900 User Manual Issue 2.0.1 Page 4 of 71
Table of Contents
1PRODUCT DESCRIPTION .........................................................................................10
2TECHNICAL SPECIFICATION ...................................................................................11
3HANDLING AND OPERATING INSTRUCTIONS.......................................................12
3.1 ESD Protection..............................................................................................................................12
3.2 Thermal Considerations...............................................................................................................12
3.3 AMC Module Insertion & Hot-Swap.............................................................................................13
3.3.1 Insertion..................................................................................................................................13
3.3.2 Extraction................................................................................................................................13
4FUNCTIONAL PROCEDURES...................................................................................14
4.1 Channel Logic ...............................................................................................................................15
4.2 Tracking Buffer..............................................................................................................................16
4.2.1 Operation Modes (OM)...........................................................................................................17
4.3 DMA Engine...................................................................................................................................18
4.4 DMA Descriptors...........................................................................................................................18
4.5 Sample Rate Logic........................................................................................................................20
4.6 Module Behavior...........................................................................................................................20
4.6.1 Power-Up/Reset......................................................................................................................20
4.6.2 Pre-Initialization (Setup) Check..............................................................................................20
4.6.3 Channel Setup........................................................................................................................21
4.7 Channel Logic ...............................................................................................................................21
4.7.1 Channel Reset........................................................................................................................21
4.7.2 Channel Activation..................................................................................................................21
4.7.3 Descriptor Change..................................................................................................................22
4.7.4 Channel Start/Stop..................................................................................................................23
4.8 Restrictions ...................................................................................................................................23
4.8.1 Processing Limit......................................................................................................................23
5ADDRESS MAP..........................................................................................................24
5.1 PCI Express Configuration ..........................................................................................................24
5.2 Register Space..............................................................................................................................26
5.3 DMA Descriptor Space .................................................................................................................27
6REGISTER DESCRIPTION.........................................................................................28
6.1 Module Status and DCM 0/1 Status Register .............................................................................28
6.2 DCM Multiply/Divide 0/1 ...............................................................................................................29
6.3 Global Channel Configuration.....................................................................................................30
6.4 Global Reset and Software Trigger Input...................................................................................31
6.5 Sample Clock Configuration 0/1..................................................................................................32
6.6 Trigger Configuration 0/1.............................................................................................................33
6.7 Channel Configuration 0-7...........................................................................................................34
6.8 Channel DMA (Base) Descriptor Addresses 0-7........................................................................35
6.9 Channel Pre-Trigger Data Size ....................................................................................................35
6.10 Channel Data 0–7..........................................................................................................................36
6.11 General DMA Status......................................................................................................................37
6.12 Channel DMA Status 0-7 ..............................................................................................................38
6.13 Channel DMA Buffer Fill-Level 0-7..............................................................................................39
6.14 Revision Control Register............................................................................................................39

TAMC900 User Manual Issue 2.0.1 Page 5 of 71
7INTERRUPTS..............................................................................................................40
7.1 Interrupt Sources..........................................................................................................................40
7.2 Interrupt Handling.........................................................................................................................40
8FPGA...........................................................................................................................41
8.1 Configuration.................................................................................................................................41
8.2 MMC Interface................................................................................................................................41
8.3 AMC Interface................................................................................................................................42
8.4 RAM Interface................................................................................................................................43
8.5 ADC Interface ................................................................................................................................43
9ADCS ..........................................................................................................................44
9.1 AC / DC Characteristics................................................................................................................44
9.1.1 Min / Max Sample Rate ..........................................................................................................44
9.1.2 Input Voltage Range...............................................................................................................44
9.1.3 Input Frequency Range..........................................................................................................44
9.2 Operational Modes........................................................................................................................44
9.2.1 Data Format............................................................................................................................44
9.2.2 Clock Duty Cycle Stabilizer.....................................................................................................45
9.3 Shielding........................................................................................................................................46
10 MEMORY ....................................................................................................................47
11 CLOCK DISTRIBUTION .............................................................................................48
12 LVDS LINK..................................................................................................................50
13 ON BOARD CPLD ......................................................................................................51
13.1 Interface to FPGA..........................................................................................................................51
13.2 CPLD Register Description..........................................................................................................52
13.2.1 ADC x Control Register (Address 0x00 to 0x07)....................................................................53
13.2.2 SiCA Input Register 1 (Address 0x08)....................................................................................53
13.2.3 SiCA Input Register 2 (Address 0x09)....................................................................................54
13.2.4 SiCA Output Register 1 (Address 0x0A) ................................................................................54
13.2.5 SiCA Output Register 2 (Address 0x0B) ................................................................................54
13.2.6 SiCA Output Enable Register 1 (Address 0x0C)....................................................................55
13.2.7 SiCA Output Enable Register 2 (Address 0x0D)....................................................................55
13.2.8 Crosspoint Switch Control Register (Address 0x10) ..............................................................56
13.2.9 Clock Mux Control Register (Address 0x11) ..........................................................................57
13.2.10 Jitter Attenuator Control Register (Address 0x12)..................................................................58
13.2.11 General Board Control Register (Address 0x18)....................................................................59
14 SIGNAL CONDITIONING ADAPTER (SICA) .............................................................60
14.1 Connector and Standoff Positions..............................................................................................60
14.2 Mating Connector..........................................................................................................................61
14.3 Board and Component Height.....................................................................................................61
15 MODULE MANAGEMENT CONTROLLER (MMC) ....................................................62
15.1 Indicators.......................................................................................................................................62
15.1.1 Front Panel LEDs....................................................................................................................62
15.2 Temperature and Voltage Sensors..............................................................................................63
15.3 Connectivity...................................................................................................................................63
15.4 Interfaces to Payload....................................................................................................................64

TAMC900 User Manual Issue 2.0.1 Page 6 of 71
16 ON BOARD INDICATORS..........................................................................................65
16.1 DONE LED......................................................................................................................................65
16.2 Power Good LEDs.........................................................................................................................65
17 PIN ASSIGNMENT......................................................................................................66
17.1 Overview ........................................................................................................................................66
17.2 I/O Connector ................................................................................................................................67
17.3 MMC JTAG Connector (Factory Use Only).................................................................................69
17.4 Payload JTAG Connector.............................................................................................................69
17.5 AMC Connector.............................................................................................................................69

TAMC900 User Manual Issue 2.0.1 Page 7 of 71
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................11
TABLE 3-1 : AMC MODULE INSERTION.......................................................................................................13
TABLE 3-2 : AMC MODULE EXTRACTION....................................................................................................13
TABLE 4-1: ADC CHANNEL GROUP ASSIGNMENT....................................................................................14
TABLE 4-2 : ADC DATA FORMAT WITH SIGN EXTENSION .......................................................................15
TABLE 4-3 : DMA DESCRIPTOR STRUCTURE............................................................................................19
TABLE 5-1 : TAMC900 PCI DEVICE INFORMATION....................................................................................24
TABLE 5-2 : TAMC900 LOCAL SPACE CONFIGURATION..........................................................................24
TABLE 5-3 : TLP TYPE SUMMARY ...............................................................................................................25
TABLE 5-4 : REGISTER MAP.........................................................................................................................27
TABLE 5-5 : DMA DESCRIPTOR SPACE......................................................................................................27
TABLE 6-1 : MODULE STATUS REGISTER (ADDRESS 0X0) .....................................................................28
TABLE 6-2 : DCM MULTIPLY/DIVIDE REGISTER (ADDRESS 0X4+ 0X4*DCM NUMBER)........................29
TABLE 6-3 : GLOBAL CHANNEL CONFIGURATION REGISTER (ADDRESS 0XC) ...................................30
TABLE 6-4 : GLOBAL RESET AND SOFTWARE TRIGGER INPUT REGISTER (ADDRESS 0X10)...........31
TABLE 6-5 : SAMPLE CLOCK CONFIGURATION REGISTER.....................................................................32
TABLE 6-6 : TRIGGER CONFIGURATION REGISTER (ADDRESS 0X1C+ 0X4*CHANNEL GROUP).......33
TABLE 6-7 : CHANNEL CONFIGURATION REGISTER (ADDRESS 0X24+ 0X4*CHANNEL).....................34
TABLE 6-8 : CHANNEL DMA (BASE) DESCRIPTOR ADDRESS REGISTER..............................................35
TABLE 6-9 : CHANNEL PRE-TRIGGER DATA REGISTER (ADDRESS 0X64+ 0X4*CHANNEL)................35
TABLE 6-10: CHANNEL DATA REGISTER (ADDRESS 0X84+ 0X4*CHANNEL).........................................36
TABLE 6-11: GLOBAL DMA STATUS REGISTER (ADDRESS 0XA4)..........................................................37
TABLE 6-12: CHANNEL DMA STATUS REGISTER (ADDRESS 0XA8+ 0X4*CHANNEL)...........................38
TABLE 6-13: CHANNEL DMA BUFFER FILL-LEVEL REGISTER (ADDRESS 0XC8+ 0X4*CHANNEL)......39
TABLE 6-14: REVISION CONTROL REGISTER (ADDRESS 0XE8).............................................................39
TABLE 7-1 : INTERRUPT SOURCES ............................................................................................................40
TABLE 7-2 : INTERRUPT HANDLING............................................................................................................40
TABLE 8-1 : FPGA SIGNALS CONNECTED TO THE MMC..........................................................................41
TABLE 8-2 : AMC FABRIC INTERFACE CONNECTIONS TO THE FPGA...................................................42
TABLE 8-3 : AMC FCLKA CONNECTION TO THE FPGA.............................................................................43
TABLE 9-1 : ADC OUTPUT DATA FORMAT..................................................................................................45
TABLE 11-1: FPGA LOCAL CLOCK (LCLK_250) INPUTS............................................................................49
TABLE 11-2: FPGA CLOCK OUTPUTS .........................................................................................................49
TABLE 11-3: ADC FEEDBACK CLOCKS.......................................................................................................49
TABLE 12-1: LVDS LINK PIN ASSIGNMENT.................................................................................................50
TABLE 13-1: CPLD REGISTER OVERVIEW .................................................................................................52
TABLE 13-2: ADC X CONTROL REGISTER (ADDRESS 0X00 TO 0X07)....................................................53
TABLE 13-3: SICA INPUT REGISTER 1 (ADDRESS 0X08)..........................................................................53
TABLE 13-4: SICA INPUT REGISTER 2 (ADDRESS 0X09)..........................................................................54
TABLE 13-5: SICA OUTPUT REGISTER 1 (ADDRESS 0X0A) .....................................................................54
TABLE 13-6: SICA OUTPUT REGISTER 2 (ADDRESS 0X0B) .....................................................................54

TAMC900 User Manual Issue 2.0.1 Page 8 of 71
TABLE 13-7: SICA OUTPUT ENABLE REGISTER 1 (ADDRESS 0X0C)......................................................55
TABLE 13-8: SICA OUTPUT ENABLE REGISTER 2 (ADDRESS 0X0D)......................................................55
TABLE 13-9: CROSSPOINT SWITCH CONTROL REGISTER (ADDRESS 0X10).......................................56
TABLE 13-10: CLOCK MUX CONTROL REGISTER (ADDRESS 0X11)........................................................57
TABLE 13-11: JITTER ATTENUATOR CONTROL REGISTER (ADDRESS 0X12)........................................58
TABLE 13-12: GENERAL BOARD CONTROL REGISTER (ADDRESS 0X18)..............................................59
TABLE 14-1: I/O MATING CONNECTORS ....................................................................................................61
TABLE 15-1: FRONT PANEL LEDS...............................................................................................................62
TABLE 17-1: PIN ASSIGNMENT I/O CONNECTOR......................................................................................68
TABLE 17-2: PIN ASSIGNMENT MMC JTAG CONNECTOR (FACTORY USE ONLY)................................69
TABLE 17-3: PIN ASSIGNMENT PAYLOAD JTAG CONNECTOR ...............................................................69
TABLE 17-4: PIN ASSIGNMENT AMC CONNECTOR...................................................................................71

TAMC900 User Manual Issue 2.0.1 Page 9 of 71
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM TAMC900 WITH SIGNAL CONDITIONING ADAPTER............................10
FIGURE 4-1: TAMC900 FPGA SYSTEM STRUCTURE ................................................................................14
FIGURE 9-1 : SHIELDING COVER DIMENSIONS ........................................................................................46
FIGURE 10-1: QDR-II SRAM INTERFACE.....................................................................................................47
FIGURE 11-1: CLOCK DISTRIBUTION BLOCK DIAGRAM...........................................................................48
FIGURE 13-1: TIMING OF FPGA-CPLD INTERFACE...................................................................................51
FIGURE 14-1: TAMC900 CONNECTOR AND STANDOFF POSITIONS.......................................................60
FIGURE 14-2: MAXIMUM COMPONENT HEIGHT FOR THE SICA..............................................................61
FIGURE 15-1: TEMPERATURE SENSOR LOCATIONS...............................................................................63
FIGURE 16-1: ON BOARD INDICATORS......................................................................................................65
FIGURE 17-1: CONNECTOR OVERVIEW.....................................................................................................66
FIGURE 17-2: I/O CONNECTOR PIN POSITIONS........................................................................................66

TAMC900 User Manual Issue 2.0.1 Page 10 of 71
1 Product Description
The TAMC900 is a high speed, high performance analog to digital converter AdvancedMC. In addition to the
eight high speed ADCs, it provides excessive preprocessing power by a Virtex-5 FPGA and high speed on
board memory for e.g. full bandwidth snapshots.
The up to x8 PCIe link of the TAMC900 is used to transmit the ADC data to the CPU.
To adapt the TAMC900 to different customer requirements, the TAMC900 is equipped with a Signal
Conditioning Adapter (SiCA) which holds the connector for the analog inputs, the connectors for the clock
and trigger inputs, and the analog signal conditioning.
The TAMC900 provides three clock inputs and three trigger inputs. The three external clock inputs and the
PCIe reference clock are routed to a flexible clocking scheme that allows independent clocking of the ADCs
in two groups. The trigger inputs are routed to the FPGA.
Eight LTC2254 ADCs provide up to 105 MSps and 14 bit resolution each. The minimum sample rate is 1
Msps.
4 MByte high speed on board SRAM enables snapshots of all ADCs at full speed and full resolution for 2ms.
According to AMC.0, the TAMC900 provides an IPMI compliant Module Management Controller (MMC) with
temperature monitoring and hot-swap support.
For First-Time-Buyers the engineering documentation TAMC900-ED is recommended. The engineering
documentation includes TAMC900-DOC, schematics and data sheets of TAMC900.
FPGA
Virtex 5 LX30T
HS-Switch
LEDs
8x
Diff.
Analog
Input
Config.
Flash
1 x Clock
Signal Conditioning Adapter
(SiCA)
3x
Trigger
3x
Clock
88
3
3
4
3
3
to MMC
har-link
x8 PCIe
(or User def.)
Trigger
ADC Data
C
lock
2MByte
SRAM
Clock
2MByte
SRAM
Clock
Distribution
4 x ADC
14 Bit
105 MHz
4 x ADC
14 Bit
105 MHz
4
ADC Data
Clock
Infiniband
Connector
har-link
Power
Supply
MMC
(IPMI)
Signal Cond
Connector AMC - SiCA
Figure 1-1 : Block Diagram TAMC900 with Signal Conditioning Adapter

TAMC900 User Manual Issue 2.0.1 Page 11 of 71
2 Technical Specification
AMC Interface
Mechanical Interface Advanced Mezzanine Card (AMC) confirming to
PICMG® AMC.0 R2.0, Single, Mid Size Module
Electrical Interface Virtex-5 FPGA connected to AMC Port 4-11
PICMG® AMC.1 R1.0 Type 4 (x4 PCI Express), or other interfaces
defined by customer
IPMI
IPMI Version 1.5
Front Panel LEDs Blue Hot Swap LED
Red Fail LED (LED1)
Green User LED (LED2)
On Board Devices
Target Chip Xilinx Virtex-5 with integrated PCI-Express Endpoint Block and two
integrated Gigabit Ethernet MACs
RAM 2 x 2 MByte QDR-II SRAM
ADC 8 x LTC2254 (105 MSps, 14 bit)
I/O Interface
Number of Analog Channels 8 differential
Analog Input Gain depends on Signal Conditioning Adapter used
Analog Input Voltage Range depends on Signal Conditioning Adapter
ADC analog input Voltage (differential) = 2VP-P
ADC input common mode Voltage = 1V to 1.9V
ADC INL/DNL Error ±1 / ±0.5 LSB (typical)
Number of Clock Inputs 3 differential (LVDS)
Number of Trigger Inputs 3 differential (LVDS)
I/O Connector 120 pin Connector to Signal conditioning adapter that holds the I/O
Connectors for the analog inputs, clocks and trigger signals
Physical Data
Power Requirements 2A typical, 4A max. @ +12V DC (Payload Power)
50 mA typical @ +3.3V DC (Management Power)
The exact Power requirement of the TAMC900 depends on
Signal Cond. Adapter used and FPGA utilization.
Temperature Range Operating
Storage 0 °C to +55 °C 0 °C to +70 °C
MTBF 391000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the component
suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F
Notice 2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight 100 g
Table 2-1 : Technical Specification

TAMC900 User Manual Issue 2.0.1 Page 12 of 71
3 Handling and Operating Instructions
Do not exceed the maximum input voltages of the TAMC900 I/Os.
The TAMC900 will be damaged if higher voltage levels are applied.
3.1ESD Protection
The TAMC900 is sensitive to static electricity.
Packing, unpacking and all other handling of the TAMC900 has to be
done in an ESD/EOS protected area.
3.2Thermal Considerations
The TAMC900 requires forced air cooling during operation.
Without forced air cooling, damage to the device will occur.

TAMC900 User Manual Issue 2.0.1 Page 13 of 71
3.3AMC Module Insertion & Hot-Swap
3.3.1 Insertion
Handle Blue LED Description
Open (Full extracted) OFF Insert Module into slot
Open (Full extracted) ON Module is ready to attempt activation
Closed (Pushed all way in) Long Blink Hot-Swap Negotiation
Closed (Pushed all way in) OFF Module is ready & powered
Table 3-1 : AMC Module Insertion
When the blue LED does not go off but returns to the “ON” state, the module FRU information is invalid or
the carrier cannot provide the necessary power.
3.3.2 Extraction
Handle Blue LED Description
Pulled out 1/2 OFF Request Hot-Swap
Pulled out 1/2 Short Blink Hot-Swap Negotiation
Pulled out 1/2 ON Module is ready to be extracted
Open (Full extracted) ON Extract Module from slot
Table 3-2 : AMC Module Extraction

TAMC900 User Manual Issue 2.0.1 Page 14 of 71
4 Functional Procedures
The following diagram illustrates the structure of the ADC data acquisition system implemented on the
TAMC900. The structure is abstract in order to show the different functional units and the data flow. All
physical connections are termed in a bold style. The remaining ones are internal connections.
The functional units are described in the subsequent chapters.
Data
Steering
ADC
Synchronisation
FIFO
Sign Extension
QDR-II
Memory Data Steering
Operation
Modes
Registers
Channel FIFO
DMA Engine (x8)
Tracking Buffer (x2)
Channel Logic (x2)
DCMs
AMC PCI Express
Connection
ADC
Inputs
Control
Logic Clock
Distribution
Sample Rate Logic
Trigger
Inputs
Sampling
Clocks
DMA
Logic
PCI Express
Endpoint
Transmit Buffer
Figure 4-1: TAMC900 FPGA System Structure
The physical clocking structure of the TAMC900 results in two different (ADC) channel groups. The module
contains eight separate 14 bit ADC channels that are structured in the way: two times four. The ADC-to-
channel group assignment is shown in the subsequent table.
Channel Group Corresponding ADC(s)
0 0-3
1 4-7
Table 4-1: ADC Channel Group Assignment
Each group has restrictions concerning a common sampling clock and a common trigger configuration.

TAMC900 User Manual Issue 2.0.1 Page 15 of 71
4.1Channel Logic
The channel logic is implemented for every channel group. It realizes the data synchronization between the
internal processing clock and the ADC sample clock domain. This is necessary because these clocks can
have an arbitrary ratio to each other. Only the limits of the ADCs have to be considered.
The ADCs have an operating frequency of 1 MHz up to 105 MHz.
Besides this the sign extension is performed in this unit. This has been implemented to simplify the data
processing out of the target memory by mapping the ADC values into legal data types. The sign-extension
method is described below.
•In 2-th complement the ADC sign bit (13) is mapped onto the additional bits 14 and 15.
•In binary offset format the ADC sign bit (13) is mapped onto bit 15 and the bits 13 and 14 are set to
zero.
AIN+ - AIN-
(2V Range) OF Data (Offset Bin.) Data (2’s Compl.)
>+1.000000V 1 0x9FFF 0x1FFF
+0.999878V 0 0x9FFF 0x1FFF
+0.999756V 0 0x9FFE 0x1FFE
... ... ... ...
+0.000122V 0 0x8001 0x0001
0.000000V 0 0x8000 0x0000
-0.000122V 0 0x1FFF 0xFFFF
-0.000244V 0 0x1FFE 0xFFFE
... ... ... ...
-0.999878V 0 0x0001 0xE001
-1.000000V 0 0x0000 0xE000
<-1.000000V 1 0x0000 0xE000
Table 4-2 : ADC Data Format with Sign Extension

TAMC900 User Manual Issue 2.0.1 Page 16 of 71
4.2Tracking Buffer
The tracking buffer is the central unit of the module. It is used to realize the different operation modes by
using the on-board QDR-II memories. The modes are described in the following chapters.
Note that an operation mode is set for entire channel group and cannot be done for every
channel in a different way.
The use of the QDR-II memory in the data path has another reason. In case of PCI Express transmission
gaps the memory can buffer the data so that the data integrity is still held. Based on the internal organization
structure there are 256k words for a single channel.
At a sample frequency of 105 MHz a period of approximate 2.4 m sec can be buffered before the loss of data
occurs.
The restriction on channel groups has impacts on the buffer technique. The throttle mode is shared by the
concatenated channels. It is used to stop providing new data to the DMA Engines if one engine signalizes
that its dedicated channel FIFO is running full.
One stalled channel may cause that all channels of the group get into error state due to buffer
overflow.

TAMC900 User Manual Issue 2.0.1 Page 17 of 71
4.2.1 Operation Modes (OM)
One operation mode is provided by the firmware (compare chapter “Trigger Configuration 0/1”) which allows
selecting which acquired ADC data should be transmitted via DMA. The different settings are explained
afterwards.
There is no absolute sample count that defines the end of transmission. This is performed until a descriptor
signalizes the end of the link list.
Due to the initially mentioned restriction the channels of a group are started together and a
channel of the group can be restarted first if all other channels of the group are in idle.
The Post Trigger Data Gathering is the standard case. The ADC data obtained after a trigger impulse is used
for data transmission. Since the mode does not make use of previous data samples there are no restrictions
concerning the number of transmitted samples. The content of register “Channel Pre-Trigger Data Size” must
be zero (see below).
The Pre Trigger Data Gathering is the opposite case. If a trigger event has been detected, the data that has
been monitored before its occurrence will be transmitted. For this, the content of the QDR-II memory is used.
Consequently, the number of samples cannot exceed the QDR-II memory depth. The value of register
“Channel Pre-Trigger Data Size” defines the transmission size. Moreover the linked list must match the
requested sample count (see below).
The Around Trigger Data Gathering is a mixture of the previous two modes. It is used to obtain the data
before and after the trigger event. Thus it makes also use of the QDR-II memory. Hence it is subdued the
size limitation as the Pre-Trigger. The implementation is done in accordance to the above two methods. The
value of register “Channel Pre-Trigger Data Size” defines the demanded tracked samples as starting point.
Afterwards transmission is performed until the linked list has been finished by a descriptor.
Pre- and Around Trigger Data Gathering require some time between trigger events to monitor
ADC channel data. This time depends on the adjusted sample rate. If the inter trigger event
period is too short, it is possible that the transmitted sample data is invalid.
There are three external (physical) trigger sources that can be used. These are described in chapter “Trigger
Configuration 0/1”. For adaptation purposes the interpretation of a trigger input signal change (edge) can be
defined.
Currently only edge-evaluated trigger have been implemented. Level trigger are not
considered.
Besides the external trigger inputs a software trigger input can be selected. This make use of an additionally
register (see chapter “Global Reset and Software Trigger Input”) to initiate processing by writing at a certain
bit position.
All trigger inputs are handled in the same manner. There is no difference.
Additionally the Post Trigger Data gathering can be used in conjunction with the software trigger to realize a
free-running operation mode if necessary.

TAMC900 User Manual Issue 2.0.1 Page 18 of 71
4.3DMA Engine
Generating PCI Express Transaction-Layer-Packets (TLPs) from the channel data and transmitting these via
the PCI Express Interface is the purpose of a DMA Engine. Every engine has an internal buffer structure
build of a first-level FIFO and a second-level transmit buffer. The FIFO is used for collecting the channel
specific data samples besides the QDR-II FIFO. The buffer is storage for the PCI Express TLPs used during
burst writes and in case of a packet retry. The TLPs have a static defined packet size (see below).
Due to flexibility considerations a concept of DMA descriptors has been implemented. These descriptors built
a Linked List (LL) which allows defining regions (windows) in host memory for placing channel ADC data.
Moreover the LL contains additional processing information respectively settings (see chapter “DMA
Descriptors”).
After channel activation or channel reset a DMA Engine uses its DMA (base) descriptor. This is set in the
channel specific DMA (Base) Descriptor Address register.
If a channel is enabled, writing into the channels DMA (Base) Descriptor register will initiate the
reload of the descriptor.
Starting at the obtained base address data packets are transmitted consecutively. The DMA memory is filled
in blocks. If the defined length (sample count) of a window has been achieved, the subsequent descriptor will
be loaded. Hence it will be switched to the next list element respectively memory address range. The data
acquisition and its transmission are performed until the last descriptor of the chain has been processed.
To reduce PCI Express traffic, interrupts will only be generated if additional steering flags demand this.
After the last descriptor has been processed, its successor list element is loaded. Thus the last
element must point to the first if the list should be used again.
If a DMA channel is stopped before its linked list could have been processed completely, it is not clear up to
which address the data inside the window is valid. Such a case can be handled by controlling the fill-level
counter. This monitors the current position inside a window. The information can be obtained through the
DMA Buffer Fill-Level register. There is one dedicated register for every channel.
The channels are processed in a rotating mechanism that considers possible interrupted PCI Express
transactions. The channels are selected for transmission in a consecutive manner, starting with channel
zero. After the last channel has been processed, the first is taken again. If the current selected channel has
no packet prepared e.g. since it is disabled or is offline caused by a transmission error, the subsequent
channel is selected.
The engine does not make any restriction to the DMA window size. Odd and even sizes are legal. If a
window has a remaining size less than the static packet size (32 DWORDS), a packet is generated that fills
the remaining gap of the window.
Interrupt events have to be acknowledged in the corresponding Channel DMA Status register after
occurrence. For additional information about interrupts refer chapter “Interrupts”.
4.4DMA Descriptors
The DMA descriptors are used to define target memory regions (windows) that are used to store the sampled
data of a channel inside the host memory. For this a descriptor contains on the one hand flags required for
its processing and on the other hand information to build a Linked List (LL).

TAMC900 User Manual Issue 2.0.1 Page 19 of 71
A DMA descriptor consists of three instructions words where every word comprises 32 bit. These have to be
arranged in a consecutive manner in the module’s dedicated memory (see chapter “DMA Descriptor Space”).
Placing the descriptors into embedded Block RAM (inside the FPGA) will reduce the PCI Express traffic and
hence accelerate the internal processing. Moreover it simplifies the access onto the descriptor instruction
words.
An embedded Block RAM in Virtex-5 is 36 kb large and thus can contain up to 42 logical DMA regions for
one physical ADC if all eight channels are used parallel. One single channel alone can have up to 341
different regions. The firmware occupies two memory blocks thus having twice the mentioned depth. The
number of address bit is defined in accordance to that.
The structure of this block is shown below.
Bits
31:28 27:24 23 22 21 20 19:11 10:0
0xC Reserved LF Reserved HI CBA Reserved
Subsequent Linked List
Pointer (resident in on-board
block RAM)
Pointer (Address) to DMA Memory Region inside the Host Memory
Length of the DMA Memory Region inside the Host Memory in Samples (16 bit words)
Table 4-3 : DMA Descriptor Structure
Providing steering information for every descriptor separately allows process-steering during runtime and
offers a different handling of the descriptors. Notice that changing the descriptors after channel activation is
not recommended. The flags are described afterwards.
The identifier 0xC marks the first instruction word of a set. It is used to detect if a descriptor is provided at the
currently accessed memory address that can be used by a DMA Engine.
If the identifier is not set, the internal structure will not use the descriptor.
The Last identifier Flag (LF) marks the last descriptor of the linked list. This information is used to execute
post-DMA-sequence tasks e.g. stop data acquisition and transmission.
The information that a certain descriptor has been processed can be sent via an interrupt to the host
respective a software driver during processing by setting the Host Interrupt (HI) flag.
Processing all linked list DMA buffers in a cyclic manner, if required, is possible by setting the Continue at
Base Address (CBA) descriptor flag. If the bit is set, the DMA (base) descriptor start address (compare
chapter “Channel DMA (Base) Descriptor Addresses 0-7” is taken next regardless of a defined subsequent
descriptor in the current descriptor.
The Subsequent Linked List Pointer is an address inside the module’s descriptor address range (see above).
Due to the 36 kbit Block RAM size the address length is 10 bit.
Setting the Linked List Pointer to 0x0 selects the first DMA descriptor memory address.

TAMC900 User Manual Issue 2.0.1 Page 20 of 71
Besides this steering information the descriptor stores the information about the pointer (address) to the
DMA memory region inside the host memory and the information about the length of this memory region.
Be aware that the length is defined in samples. Hence the number of required bytes is twice as
large as the defined length.
4.5Sample Rate Logic
The sample rate logic allows defining two different clocks that can be used as sample rate for the different
ADC channel groups. There are two Digital Clock Managers (DCMs) that generate a clock based on a
multiply-divide ratio. The internal control logic employs clock multiplexers for switching the clocks to a certain
group. The multiplexers are glitch-free so that switching can be performed at every time.
Switching during runtime (processing) is not recommend.
In accordance with that, both groups can be set into a common clock mode (sourced from DCM0 or DCM1)
or an independent clock mode.
4.6Module Behavior
4.6.1 Power-Up/Reset
The module has reset-conditions after it has been activated. For this the PCI Express Endpoint’s dedicated
reset signal is used. This means
•all registers have their reset value
•DCMs have reset settings
•trigger signals are reset
•the QDR memories invalidate their data
•all DMA Engines lose their information
•DMA processing select the base Descriptors as defined through the register map
•interrupts are de-asserted
•CPLD has been reset
4.6.2 Pre-Initialization (Setup) Check
Before any operation on the TAMC900 can be performed it has to be checked that
•the GSTAT bit inside the Module Status and DCM 0/1 Status register indicates that the module is
operational,
•all (unused) channels are disabled.