Tews Technologies TAMC900 User manual

The Embedded I/O Company
TAMC900
AMC with 8 high Speed ADCs 105MSps, 14Bit
Version 2.0
User Manual
Issue 2.0.1
April 2010
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TAMC900 User Manual Issue 2.0.1 Page 2 of 71
TAMC900-10R
AMC with 8 high speed ADCs 105 MSps 14 bit,
RoHS compliant. Requires Signal Conditioning
Adapter
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‘Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
©2008 – 2010 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TAMC900 User Manual Issue 2.0.1 Page 3 of 71
Issue Description Date
1.0 Initial Issue April 2008
1.1 Minor changes in chapter 9
Added details to chapter 4.3 May 2008
1.2 Corrections in “Crosspoint Switch Control Register “
Different minor corrections and additions August 2008
1.0.3 New User Manual Issue Notation
Correction of “MMC JTAG Connector Pin Assignment” January 2009
2.0.0 Update to TAMC900 V2.0
Added FPGA code description November 2009
2.0.1 Firmware Upgrade to Version 2 April 2010

TAMC900 User Manual Issue 2.0.1 Page 4 of 71
Table of Contents
1PRODUCT DESCRIPTION .........................................................................................10
2TECHNICAL SPECIFICATION ...................................................................................11
3HANDLING AND OPERATING INSTRUCTIONS.......................................................12
3.1 ESD Protection..............................................................................................................................12
3.2 Thermal Considerations...............................................................................................................12
3.3 AMC Module Insertion & Hot-Swap.............................................................................................13
3.3.1 Insertion..................................................................................................................................13
3.3.2 Extraction................................................................................................................................13
4FUNCTIONAL PROCEDURES...................................................................................14
4.1 Channel Logic ...............................................................................................................................15
4.2 Tracking Buffer..............................................................................................................................16
4.2.1 Operation Modes (OM)...........................................................................................................17
4.3 DMA Engine...................................................................................................................................18
4.4 DMA Descriptors...........................................................................................................................18
4.5 Sample Rate Logic........................................................................................................................20
4.6 Module Behavior...........................................................................................................................20
4.6.1 Power-Up/Reset......................................................................................................................20
4.6.2 Pre-Initialization (Setup) Check..............................................................................................20
4.6.3 Channel Setup........................................................................................................................21
4.7 Channel Logic ...............................................................................................................................21
4.7.1 Channel Reset........................................................................................................................21
4.7.2 Channel Activation..................................................................................................................21
4.7.3 Descriptor Change..................................................................................................................22
4.7.4 Channel Start/Stop..................................................................................................................23
4.8 Restrictions ...................................................................................................................................23
4.8.1 Processing Limit......................................................................................................................23
5ADDRESS MAP..........................................................................................................24
5.1 PCI Express Configuration ..........................................................................................................24
5.2 Register Space..............................................................................................................................26
5.3 DMA Descriptor Space .................................................................................................................27
6REGISTER DESCRIPTION.........................................................................................28
6.1 Module Status and DCM 0/1 Status Register .............................................................................28
6.2 DCM Multiply/Divide 0/1 ...............................................................................................................29
6.3 Global Channel Configuration.....................................................................................................30
6.4 Global Reset and Software Trigger Input...................................................................................31
6.5 Sample Clock Configuration 0/1..................................................................................................32
6.6 Trigger Configuration 0/1.............................................................................................................33
6.7 Channel Configuration 0-7...........................................................................................................34
6.8 Channel DMA (Base) Descriptor Addresses 0-7........................................................................35
6.9 Channel Pre-Trigger Data Size ....................................................................................................35
6.10 Channel Data 0–7..........................................................................................................................36
6.11 General DMA Status......................................................................................................................37
6.12 Channel DMA Status 0-7 ..............................................................................................................38
6.13 Channel DMA Buffer Fill-Level 0-7..............................................................................................39
6.14 Revision Control Register............................................................................................................39

TAMC900 User Manual Issue 2.0.1 Page 5 of 71
7INTERRUPTS..............................................................................................................40
7.1 Interrupt Sources..........................................................................................................................40
7.2 Interrupt Handling.........................................................................................................................40
8FPGA...........................................................................................................................41
8.1 Configuration.................................................................................................................................41
8.2 MMC Interface................................................................................................................................41
8.3 AMC Interface................................................................................................................................42
8.4 RAM Interface................................................................................................................................43
8.5 ADC Interface ................................................................................................................................43
9ADCS ..........................................................................................................................44
9.1 AC / DC Characteristics................................................................................................................44
9.1.1 Min / Max Sample Rate ..........................................................................................................44
9.1.2 Input Voltage Range...............................................................................................................44
9.1.3 Input Frequency Range..........................................................................................................44
9.2 Operational Modes........................................................................................................................44
9.2.1 Data Format............................................................................................................................44
9.2.2 Clock Duty Cycle Stabilizer.....................................................................................................45
9.3 Shielding........................................................................................................................................46
10 MEMORY ....................................................................................................................47
11 CLOCK DISTRIBUTION .............................................................................................48
12 LVDS LINK..................................................................................................................50
13 ON BOARD CPLD ......................................................................................................51
13.1 Interface to FPGA..........................................................................................................................51
13.2 CPLD Register Description..........................................................................................................52
13.2.1 ADC x Control Register (Address 0x00 to 0x07)....................................................................53
13.2.2 SiCA Input Register 1 (Address 0x08)....................................................................................53
13.2.3 SiCA Input Register 2 (Address 0x09)....................................................................................54
13.2.4 SiCA Output Register 1 (Address 0x0A) ................................................................................54
13.2.5 SiCA Output Register 2 (Address 0x0B) ................................................................................54
13.2.6 SiCA Output Enable Register 1 (Address 0x0C)....................................................................55
13.2.7 SiCA Output Enable Register 2 (Address 0x0D)....................................................................55
13.2.8 Crosspoint Switch Control Register (Address 0x10) ..............................................................56
13.2.9 Clock Mux Control Register (Address 0x11) ..........................................................................57
13.2.10 Jitter Attenuator Control Register (Address 0x12)..................................................................58
13.2.11 General Board Control Register (Address 0x18)....................................................................59
14 SIGNAL CONDITIONING ADAPTER (SICA) .............................................................60
14.1 Connector and Standoff Positions..............................................................................................60
14.2 Mating Connector..........................................................................................................................61
14.3 Board and Component Height.....................................................................................................61
15 MODULE MANAGEMENT CONTROLLER (MMC) ....................................................62
15.1 Indicators.......................................................................................................................................62
15.1.1 Front Panel LEDs....................................................................................................................62
15.2 Temperature and Voltage Sensors..............................................................................................63
15.3 Connectivity...................................................................................................................................63
15.4 Interfaces to Payload....................................................................................................................64

TAMC900 User Manual Issue 2.0.1 Page 6 of 71
16 ON BOARD INDICATORS..........................................................................................65
16.1 DONE LED......................................................................................................................................65
16.2 Power Good LEDs.........................................................................................................................65
17 PIN ASSIGNMENT......................................................................................................66
17.1 Overview ........................................................................................................................................66
17.2 I/O Connector ................................................................................................................................67
17.3 MMC JTAG Connector (Factory Use Only).................................................................................69
17.4 Payload JTAG Connector.............................................................................................................69
17.5 AMC Connector.............................................................................................................................69

TAMC900 User Manual Issue 2.0.1 Page 7 of 71
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................11
TABLE 3-1 : AMC MODULE INSERTION.......................................................................................................13
TABLE 3-2 : AMC MODULE EXTRACTION....................................................................................................13
TABLE 4-1: ADC CHANNEL GROUP ASSIGNMENT....................................................................................14
TABLE 4-2 : ADC DATA FORMAT WITH SIGN EXTENSION .......................................................................15
TABLE 4-3 : DMA DESCRIPTOR STRUCTURE............................................................................................19
TABLE 5-1 : TAMC900 PCI DEVICE INFORMATION....................................................................................24
TABLE 5-2 : TAMC900 LOCAL SPACE CONFIGURATION..........................................................................24
TABLE 5-3 : TLP TYPE SUMMARY ...............................................................................................................25
TABLE 5-4 : REGISTER MAP.........................................................................................................................27
TABLE 5-5 : DMA DESCRIPTOR SPACE......................................................................................................27
TABLE 6-1 : MODULE STATUS REGISTER (ADDRESS 0X0) .....................................................................28
TABLE 6-2 : DCM MULTIPLY/DIVIDE REGISTER (ADDRESS 0X4+ 0X4*DCM NUMBER)........................29
TABLE 6-3 : GLOBAL CHANNEL CONFIGURATION REGISTER (ADDRESS 0XC) ...................................30
TABLE 6-4 : GLOBAL RESET AND SOFTWARE TRIGGER INPUT REGISTER (ADDRESS 0X10)...........31
TABLE 6-5 : SAMPLE CLOCK CONFIGURATION REGISTER.....................................................................32
TABLE 6-6 : TRIGGER CONFIGURATION REGISTER (ADDRESS 0X1C+ 0X4*CHANNEL GROUP).......33
TABLE 6-7 : CHANNEL CONFIGURATION REGISTER (ADDRESS 0X24+ 0X4*CHANNEL).....................34
TABLE 6-8 : CHANNEL DMA (BASE) DESCRIPTOR ADDRESS REGISTER..............................................35
TABLE 6-9 : CHANNEL PRE-TRIGGER DATA REGISTER (ADDRESS 0X64+ 0X4*CHANNEL)................35
TABLE 6-10: CHANNEL DATA REGISTER (ADDRESS 0X84+ 0X4*CHANNEL).........................................36
TABLE 6-11: GLOBAL DMA STATUS REGISTER (ADDRESS 0XA4)..........................................................37
TABLE 6-12: CHANNEL DMA STATUS REGISTER (ADDRESS 0XA8+ 0X4*CHANNEL)...........................38
TABLE 6-13: CHANNEL DMA BUFFER FILL-LEVEL REGISTER (ADDRESS 0XC8+ 0X4*CHANNEL)......39
TABLE 6-14: REVISION CONTROL REGISTER (ADDRESS 0XE8).............................................................39
TABLE 7-1 : INTERRUPT SOURCES ............................................................................................................40
TABLE 7-2 : INTERRUPT HANDLING............................................................................................................40
TABLE 8-1 : FPGA SIGNALS CONNECTED TO THE MMC..........................................................................41
TABLE 8-2 : AMC FABRIC INTERFACE CONNECTIONS TO THE FPGA...................................................42
TABLE 8-3 : AMC FCLKA CONNECTION TO THE FPGA.............................................................................43
TABLE 9-1 : ADC OUTPUT DATA FORMAT..................................................................................................45
TABLE 11-1: FPGA LOCAL CLOCK (LCLK_250) INPUTS............................................................................49
TABLE 11-2: FPGA CLOCK OUTPUTS .........................................................................................................49
TABLE 11-3: ADC FEEDBACK CLOCKS.......................................................................................................49
TABLE 12-1: LVDS LINK PIN ASSIGNMENT.................................................................................................50
TABLE 13-1: CPLD REGISTER OVERVIEW .................................................................................................52
TABLE 13-2: ADC X CONTROL REGISTER (ADDRESS 0X00 TO 0X07)....................................................53
TABLE 13-3: SICA INPUT REGISTER 1 (ADDRESS 0X08)..........................................................................53
TABLE 13-4: SICA INPUT REGISTER 2 (ADDRESS 0X09)..........................................................................54
TABLE 13-5: SICA OUTPUT REGISTER 1 (ADDRESS 0X0A) .....................................................................54
TABLE 13-6: SICA OUTPUT REGISTER 2 (ADDRESS 0X0B) .....................................................................54

TAMC900 User Manual Issue 2.0.1 Page 8 of 71
TABLE 13-7: SICA OUTPUT ENABLE REGISTER 1 (ADDRESS 0X0C)......................................................55
TABLE 13-8: SICA OUTPUT ENABLE REGISTER 2 (ADDRESS 0X0D)......................................................55
TABLE 13-9: CROSSPOINT SWITCH CONTROL REGISTER (ADDRESS 0X10).......................................56
TABLE 13-10: CLOCK MUX CONTROL REGISTER (ADDRESS 0X11)........................................................57
TABLE 13-11: JITTER ATTENUATOR CONTROL REGISTER (ADDRESS 0X12)........................................58
TABLE 13-12: GENERAL BOARD CONTROL REGISTER (ADDRESS 0X18)..............................................59
TABLE 14-1: I/O MATING CONNECTORS ....................................................................................................61
TABLE 15-1: FRONT PANEL LEDS...............................................................................................................62
TABLE 17-1: PIN ASSIGNMENT I/O CONNECTOR......................................................................................68
TABLE 17-2: PIN ASSIGNMENT MMC JTAG CONNECTOR (FACTORY USE ONLY)................................69
TABLE 17-3: PIN ASSIGNMENT PAYLOAD JTAG CONNECTOR ...............................................................69
TABLE 17-4: PIN ASSIGNMENT AMC CONNECTOR...................................................................................71

TAMC900 User Manual Issue 2.0.1 Page 9 of 71
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM TAMC900 WITH SIGNAL CONDITIONING ADAPTER............................10
FIGURE 4-1: TAMC900 FPGA SYSTEM STRUCTURE ................................................................................14
FIGURE 9-1 : SHIELDING COVER DIMENSIONS ........................................................................................46
FIGURE 10-1: QDR-II SRAM INTERFACE.....................................................................................................47
FIGURE 11-1: CLOCK DISTRIBUTION BLOCK DIAGRAM...........................................................................48
FIGURE 13-1: TIMING OF FPGA-CPLD INTERFACE...................................................................................51
FIGURE 14-1: TAMC900 CONNECTOR AND STANDOFF POSITIONS.......................................................60
FIGURE 14-2: MAXIMUM COMPONENT HEIGHT FOR THE SICA..............................................................61
FIGURE 15-1: TEMPERATURE SENSOR LOCATIONS...............................................................................63
FIGURE 16-1: ON BOARD INDICATORS......................................................................................................65
FIGURE 17-1: CONNECTOR OVERVIEW.....................................................................................................66
FIGURE 17-2: I/O CONNECTOR PIN POSITIONS........................................................................................66

TAMC900 User Manual Issue 2.0.1 Page 10 of 71
1 Product Description
The TAMC900 is a high speed, high performance analog to digital converter AdvancedMC. In addition to the
eight high speed ADCs, it provides excessive preprocessing power by a Virtex-5 FPGA and high speed on
board memory for e.g. full bandwidth snapshots.
The up to x8 PCIe link of the TAMC900 is used to transmit the ADC data to the CPU.
To adapt the TAMC900 to different customer requirements, the TAMC900 is equipped with a Signal
Conditioning Adapter (SiCA) which holds the connector for the analog inputs, the connectors for the clock
and trigger inputs, and the analog signal conditioning.
The TAMC900 provides three clock inputs and three trigger inputs. The three external clock inputs and the
PCIe reference clock are routed to a flexible clocking scheme that allows independent clocking of the ADCs
in two groups. The trigger inputs are routed to the FPGA.
Eight LTC2254 ADCs provide up to 105 MSps and 14 bit resolution each. The minimum sample rate is 1
Msps.
4 MByte high speed on board SRAM enables snapshots of all ADCs at full speed and full resolution for 2ms.
According to AMC.0, the TAMC900 provides an IPMI compliant Module Management Controller (MMC) with
temperature monitoring and hot-swap support.
For First-Time-Buyers the engineering documentation TAMC900-ED is recommended. The engineering
documentation includes TAMC900-DOC, schematics and data sheets of TAMC900.
FPGA
Virtex 5 LX30T
HS-Switch
LEDs
8x
Diff.
Analog
Input
Config.
Flash
1 x Clock
Signal Conditioning Adapter
(SiCA)
3x
Trigger
3x
Clock
88
3
3
4
3
3
to MMC
har-link
x8 PCIe
(or User def.)
Trigger
ADC Data
C
lock
2MByte
SRAM
Clock
2MByte
SRAM
Clock
Distribution
4 x ADC
14 Bit
105 MHz
4 x ADC
14 Bit
105 MHz
4
ADC Data
Clock
Infiniband
Connector
har-link
Power
Supply
MMC
(IPMI)
Signal Cond
Connector AMC - SiCA
Figure 1-1 : Block Diagram TAMC900 with Signal Conditioning Adapter