Texas Instruments AM62x SK EVM User manual

User’s Guide
AM62x SK EVM User's Guide
ABSTRACT
This technical User’s Guide describes the hardware architecture of the AM62x SKEVM, a low cost Starter
Kit built around the AM62x SoC. The AM62x processor comprises of a Quad-Core 64-bit Arm®-Cortex® A53
microprocessor, Single-core Arm Cortex-R5F MCU and an Arm Cortex-M4F MCU.
The SKEVM allows the user to experience great dual display feature through HDMI (over DPI) and LVDS, as
well as industrial communication solutions using serial, Ethernet, USB and other interfaces.
The SKEVM can be used for your display application(for example a HMI or control panel) with either a
HDMI display or an external LVDS panel, up to 2K resolution. It's high performance (up to) Quad-A53 ARM
cores at 1.4GHz, with rich industrial interfaces, offer control and communication capabilities for a wide ranges
of applications, such as PLC, automation control and monitor/supervisor systems. In addition, SKEVM can
communicate with other processors or systems, and act as a communication gateway. The embedded emulation
logic allows for emulation and debugging using standard development tools such as Code Composer Studio™
from TI.
Note
This evaluation board is a pre-production release and has several known issues that should not be
copied into a production system. E1 EVM Shown in product photos.
Table of Contents
1 EVM Revisions and Assembly Variants................................................................................................................................4
2 System Description................................................................................................................................................................ 5
2.1 Key Features......................................................................................................................................................................6
2.2 Functional Block Diagram (SK-AM62)............................................................................................................................... 8
2.3 Functional Block Diagram (SK-AM62-P1)..........................................................................................................................9
2.4 AM62x SKEVM Interface Mapping...................................................................................................................................11
2.5 Power ON/OFF Procedures............................................................................................................................................. 11
2.6 Peripheral and Major Component Description................................................................................................................. 13
3 Known Issues and Modifications........................................................................................................................................ 64
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3.1 Issue 1 - HDMI/DSS Incorrect Colors on E1.................................................................................................................... 64
3.2 Issue 2 - J9 and J10 Header Alignment on E1.................................................................................................................64
3.3 Issue 3 - USB Boot descoped on E1................................................................................................................................65
3.4 Issue 4 - OLDI Connector Orientation and Pinout............................................................................................................65
3.5 Issue 5 - Bluetooth descoped on E2 EVMs......................................................................................................................65
3.6 Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes...................................................................................... 65
3.7 Issue 7 - TEST_POWERDOWN changes........................................................................................................................66
3.8 Issue 8 - MMC1_SDCD spurious interrupts..................................................................................................................... 66
3.9 Issue 9 - PD Controller I2C2 IRQ Not Pinned Out........................................................................................................... 66
3.10 Issue 10 - INA Current Monitor Adress Changes...........................................................................................................66
3.11 Issue 11 - Test Automation I2C Buffer Changes.............................................................................................................66
Regulatory Compliance...........................................................................................................................................................68
Revision History.......................................................................................................................................................................68
List of Figures
Figure 2-1. SK-AM62 Top View....................................................................................................................................................5
Figure 2-2. SK-AM62 Back View................................................................................................................................................. 6
Figure 2-3. Functional Block Diagram of the AM62x SKEVM Board........................................................................................... 9
Figure 2-4. Functional Block Diagram of the AM62x SKEVM Board with TPS65219 PMIC......................................................10
Figure 2-5. SD Bootmode Switch Setting Example (E2, E3)..................................................................................................... 12
Figure 2-6. SD Bootmode Switch Setting Example (E1)........................................................................................................... 13
Figure 2-7. Clock Architecture of AM62x SKEVM..................................................................................................................... 14
Figure 2-8. SoC WKUP Domain................................................................................................................................................ 14
Figure 2-9. Bootmode Switch Configuration for SD Boot (E2, E3)............................................................................................ 50
Figure 2-10. Bootmode Switch Configuration for SD Boot (E1).................................................................................................51
Figure 3-1. PRU Connector Missalignment on E1 Boards........................................................................................................ 65
Figure 3-2. Schematic of I2C Buffer Section..............................................................................................................................67
Figure 3-3. Location on AM62x SK E3 (Bottom Side)............................................................................................................... 67
List of Tables
Table 1-1. SK EVM PCB design revisions, and asssembly variants............................................................................................4
Table 2-1. Interface Mapping .....................................................................................................................................................11
Table 2-2. Power Test Points..................................................................................................................................................... 13
Table 2-3. Clock Table............................................................................................................................................................... 15
Table 2-4. Display Connector Pinout (As used by display and the E3 EVM).............................................................................16
Table 2-5. Display Connector Pinout (E1/E2)............................................................................................................................ 17
Table 2-6. CSI Camera Connector J19 Pin-out......................................................................................................................... 18
Table 2-7. JTAG Connector (J17) Pin-out.................................................................................................................................. 21
Table 2-8. Test Automation Connector (J23) Pin-out................................................................................................................. 23
Table 2-9. UART Port Interface..................................................................................................................................................24
Table 2-10. IO Expander Signal Detail.......................................................................................................................................36
Table 2-11. GPIO Mapping.........................................................................................................................................................38
Table 2-12. Type-C port Power roles......................................................................................................................................... 40
Table 2-13. Recommended External Power Supply.................................................................................................................. 40
Table 2-14. SoC Power Supply..................................................................................................................................................48
Table 2-15. INA I2C Device Address (E1)................................................................................................................................. 48
Table 2-16. INA I2C Device Address (E2)................................................................................................................................. 49
Table 2-17. BOOT-MODE Pin Mapping..................................................................................................................................... 51
Table 2-18. PLL Reference Clock Selection BOOTMODE [2:0]................................................................................................ 51
Table 2-19. Boot Device Selection BOOT-MODE [6:3]..............................................................................................................52
Table 2-20. Backup Boot Mode Selection BOOT-MODE [12:10]...............................................................................................52
Table 2-21. Primary Boot Media Configuration BOOT-MODE [9:7]........................................................................................... 52
Table 2-22. Backup Boot Media Configuration BOOT-MODE [13]............................................................................................ 53
Table 2-23. User test LEDs .......................................................................................................................................................53
Table 2-24. PRU Header (J10) Pin-out...................................................................................................................................... 54
Table 2-25. 40 Pin User Expansion Connector..........................................................................................................................55
Table 2-26. Pin MCU Connector (J9).........................................................................................................................................57
Table 2-27. EVM Push Buttons..................................................................................................................................................59
Table 2-28. I2C Mapping Table (SK-AM62 E3 and SK-AM62-P1 Variants)...............................................................................60
Table 2-29. I2C Mapping Table (SK-AM62 E2)..........................................................................................................................62
Table 3-1. AM62x SK EVM Known Issues and Modifications....................................................................................................64
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Trademarks
Sitara™ is a trademark of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
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1 EVM Revisions and Assembly Variants
The various AM62x SK EVM PCB design revisions, and asssembly variants are listed in the table below. Specific
PCB revision is indicated in silkscreen on the PCB. Specific assembly variant is indicated with additional sticker
label.
Table 1-1. SK EVM PCB design revisions, and asssembly variants
OPN PCB Revison Assembly Variant
Revision and Assembly Variant
Description
SK-AM62 PROC114E1 N/A (single variant produced) First prototype, early release revision of
the AM62x SK EVM. Implements the
Sitara™ AM62x MPU with a discrete
power solution
SK-AM62 PROC114E2 N/A Second prototype, early release revision
of the AM62x SK EVM. Implements a
number of changes and bug fixes focused
on enabling 24 bit RGB output via HDMI.
SK-AM62 PROC114E3 N/A Third prototype, early release revision
of the AM62x SK EVM. Implements a
number of changes around LVDS and
multimedia peripherals.
SK-AM62-P1 PROC142E1 N/A First prototype, early release version of
the AM62x SK EVM. implementing the
TPS65219 PMIC.
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2 System Description
Figure 2-1. SK-AM62 Top View
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Figure 2-2. SK-AM62 Back View
2.1 Key Features
The AM62x SKEVM is a high performance, standalone development platform that enables users to evaluate and
develop industrial applications for the Texas Instrument’s AM62x System-on-Chip (SoC).
The following sections discuss the SKEVM’s key features.
2.1.1 Thermal Compliance
There is elevated heat on the processor, use caution particularly at elevated ambient temperatures! Although the
processor is not a burn hazard, caution should be used when handling the EVM due to increased heat in the
area of the SoC.
Caution Caution Hot surface.
Contact may cause burns.
Do not touch!
2.1.2 Processor
• AM62x SoC, 13 mm x 13 mm, 0.5 mm pitch, 423‐pin VCA FBGA
2.1.3 Power Supply
• Two USB Type-C ports (5V‐15V input range)
• Optimized Power Solution with Discrete Regulators and LDOs for the Processor and Peripherals
2.1.4 Memory
• 2GB DDR4 supporting data rate up to 1600MT/s.
• Micro SD Card slot with UHS-1 support
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• 512Mbit Octal SPI Flash memory
• 512 Kbit Inter-Integrated Circuit (I2C) board ID EEPROM
• 16GB eMMC Flash
2.1.5 JTAG/Emulator
• XDS110 On-Board Emulator
• Supports 20-pin JTAG connection from external emulator
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2.1.6 Supported Interfaces and Peripherals
• 1x USB2.0 Type C Interface, support DFP and UFP roles
• 1x USB2.0 Host Interface, Type A
• 1x HDMI Interface
• Audio Line in and Mic + Headphone out
• Wilink WL1837 Module with support for Wi-Fi and Bluetooth
• 2x Gigabit Ethernet ports supporting 10/100/1000 Mbps data rate on two RJ45 connectors.
• Quad port UART to USB circuit over microB USB connector
• Industrial Ethernet LEDs
• INA devices for current monitoring
• 2x Temperature Sensors near SoC and DDR4 for thermal monitoring
2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
• CSI Camera Header
• LVDS Display connector
• User Expansion connector
• PRU Header
• MCU Header
2.2 Functional Block Diagram (SK-AM62)
Figure 2-3 shows the functional block diagram of the AM62x SKEVM Board.
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Figure 2-3. Functional Block Diagram of the AM62x SKEVM Board
2.3 Functional Block Diagram (SK-AM62-P1)
Figure 2-3 shows the functional block diagram of the AM62x SKEVM Board with TPS65219 PMIC.
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Figure 2-4. Functional Block Diagram of the AM62x SKEVM Board with TPS65219 PMIC
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2.4 AM62x SKEVM Interface Mapping
Table 2-1 is provided below.
Table 2-1. Interface Mapping
Interface Name Port on SoC Device Part Number
Memory – DDR4 DDR0 MT40A1G16KD-062E:E
Memory – OSPI OSPI0 S28HS512TGABHM010
Memory – Micro SD Socket MMC1 MEM2051-00-195-00-A
Memory – eMMC MMC0 MTFC16GAPALBH-IT
Memory – Board ID EEPROM SoC_I2C0 AT24C512C-MAHM-T
Ethernet 1 – RGMII SoC_RGMII1 DP83867IRRGZ
Ethernet 2 – RGMII SoC_RGMII2 DP83867IRRGZ
LED Driver – 8 Communication LEDs WKUP_I2C0 TPIC2810D
PRU Header – 2x10 HDR PR0_PRU0_GPO and SoC_I2C0 PREC010DAAN-RC
User Expansion Connector – 2x20 HDR SPI0, SPI2, UART5, SoC_I2C0, SoC_I2C2
and GPIOs PEC20DAAN
MCU Header – 2x14 HDR MCU_UART0, MCU_MCAN0, MCU_SPI0,
MCU_I2C0 and MCU GPIOs PREC014DAAN-RC
USB – 2.0 Type C USB0 TUSB4020BIPHP + AU-Y1008-2
USB – 2.0 Type A USB1 -
LVDS Display Connector OLDI0 FFC2A32-40-T
CSI Interface CSI0 1-1734248-5
HDMI VOUT0 SiI9022ACNU + TPD12S016PWR +
10029449-001RLF
Audio Codec McASP2 and SoC_I2C1 TLV320AIC3106IRGZT + SJ-43514-SMT
GPIO Port Expander SoC_I2C1 TCA6424ARGJR
UART Terminal (UART-to-USB) SoC_UART [1:0], WKUP_UART0 and
MCU_UART0 FT4232HL + 629105150521
Test Automation Header SoC_I2C1 FH12A-40S-0.5SH
Temperature Sensors SoC_I2C1 TMP100NA/3K
Current Monitors SoC_I2C1 INA231AIYFDR
Connectivity – Wilink Module MMC2, McASP2 and SoC_UART2 WL1837MODGIMOCT
2.5 Power ON/OFF Procedures
Power to the EVM is provided through an external power supply providing PD voltage and current to the either of
the two USB Type-C Ports.
2.5.1 Power-On Procedure
1. Place the SKEVM boot switch selectors (SW1, SW2) into selected boot mode. Example boot-modes for SD
card and no-boot are shown below.
2. Connect your boot media (if applicable).
3. Attach the PD capable USB Type-C cable to the SKEVM Type-C (J11 or J13) Connector.
4. Connect the other end of the Type-C cable to the source, either AC Power Adapter, or Type C source device
(such as a Laptop computer).
5. Visually inspect that either LD10 or LD12 LED are illuminated.
6. XDS110 JTAG and UART debug console output are routed to micro-USB ports J16 and J15, respectively.
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Figure 2-5. SD Bootmode Switch Setting Example (E2, E3)
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Figure 2-6. SD Bootmode Switch Setting Example (E1)
2.5.2 Power-Off Procedure
1. Disconnect AC power from AC/DC converter.
2. Remove the USB Type-C cable from the SKEVM.
2.5.3 Power Test Points
Test points for each power output on the board is mentioned in Table 2-2.
Table 2-2. Power Test Points
Sl # Power Supply Test Point Voltage
1 VBUS_TYPEC1 C398.1 5V-15V
2 VBUS_TYPEC2 C415 5V-15V
3 VMAIN TP95 5V-15V
4 VCC_5V0 TP70 5V
5 VCC_3V3_SYS TP51 3.3V
6 VDD_2V5 TP42 2.5V
7 VPP_1V8 TP31 1.8V
8 VDD_1V0 TP33 1.0V
9 VDD_1V1 TP44 1.1V
10 VDD_1V2 TP10 1.2V
11 VDDA1V8 TP36 1.8V
12 VCC_1V8 TP41 1.8V
13 VDDSHV_SDIO TP29 1.8V/3.3V
14 VCC1V2_DDR TP40 1.2V
15 VCC_CORE TP45 0.85V
16 VDD_CORE TP46 0.85V
17 VCC_0V85 TP39 0.85V
18 VDDR_CORE TP38 0.85V
19 DDR_VREFCA TP43 0.6V
20 VCC3V3_TA TP87 3.3V
21 VCC3V3_XDS TP77 3.3V
22 VCC_3V3_FT4232 C482.1 3.3V
2.6 Peripheral and Major Component Description
The following sections provide an overview of the different interfaces and circuits on the AM62x SK EVM.
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2.6.1 Clocking
Figure 2-7 shows the clock architecture of AM62x SKEVM.
Figure 2-7. Clock Architecture of AM62x SKEVM
A clock generator of part number LMK1C1103PWR is used to drive the 25 MHz clock to the SoC and two
Ethernet PHYs. LMK1C1103PWR is a 1:4 LVCMOS clock buffer, which takes the 25 MHz crystal/LVCMOS
reference input and provides three 25 MHz LVCMOS clock outputs. The source for the clock buffer shall be
either the CLKOUT0 pin from the SoC or a 25 MHz oscillator, the selection is made using a set of resistors. By
default, an oscillator is used as input to the clock buffer on the AM62x SKEVM. Output Y2 and Y3 of the clock
buffer are used as reference clock inputs] for two Gigabit Ethernet PHYs.
There is one external crystal attached to the AM62x SoC to provide clock to the WKUP domain of the SoC
(32.768 KHz).
Figure 2-8. SoC WKUP Domain
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2.6.1.1 Peripheral Ref Clock
Clock inputs required for peripherals such as XDS110, USB HUB, FT4232, HDMI Transmitter and Audio Codec
are generated locally using separate crystals or oscillators. Crystals or Oscillators used to provide the reference
clocks to the EVM peripherals are shown in the table bellow.
Table 2-3. Clock Table
Peripheral Mfr. Part No. Description Frequency
XDS110 emulator ECS-.327-9-34QCS-TR CRY 32.768 KHz 9pF SMD 32.768 KHz
FT4232 Bridge ECS-120-18-30B-AGN-TR CRY 12.000 MHz 18pF SMD 12.000 MHz
Audio Codec KC2520Z12.2880C1KX00 OSC 12.288 MHz CMOS SMD 12.288 MHz
USB HUB (E1 Only) ECS-240-20-30B-AGL-TR CRY 24.000 MHz 20pF SMD 24.000 MHz
HDMI Transmitter KC2520Z12.2880C1KX00 OSC 12.288 MHz CMOS SMD 12.288 MHz
The clock required by the HDMI Transmitter can be provided by either the on board oscillator or the SoC’s
AUDIO_EXT_REFCLK1, which can be selected through a resistor mux. SoC’s EXT_REFCLK1 is used to
provide clock to the User Expansion Connector on the SKEVM. The 32 KHz clock to the Wilink module is
provided by WKUP_CLKOUT0 of AM62x SoC through a voltage translational buffer.
2.6.2 Reset
The Reset Architecture of AM62x SKEVM is shown below.
The SoC has the following resets:
• RESETSTATz is the Main domain warm reset status output
• PORz_OUT is the Main domain power ON reset status output
• RESET_REQz is the Main domain warm reset input
• MCU_PORz is the MCU domain power ON/ Cold Reset input
• MCU_RESETz is the MCU domain warm reset input
• MCU_RESETSTATz is the MCU domain warm reset status output
Upon Power on Reset, all peripheral devices connected to the main domain get reset by RESETSTATz.
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2.6.3 OLDI Display Interface
The OLDI0 Display interface of the AM62x SoC is connected to a 40 pin LVDS display connector (J21) Mfr
Part# FFC2A32-40-T from GCT. The OLDI Interface supports dual channel 8 bit LVDS output.The pinout and
connector orientation is common between E1 and E2 boards but differs from the future 'final' E3 boards.
Adapters are available to update the E1/E2 wiring to E3. Do not attempt to connect a display designed for E3
EVMs to the E1/E2 EVM without this adapter.
The Pin-out details of the Display connector are given in Table 2-5.
Table 2-4. Display Connector Pinout (As used by display and the E3 EVM)
Pin no. Signal Pin no. Signal
1 VCC_3V3_SYS(EEPROM_VDD) 21 CH1_LVDS_A2P
2 SoC_I2C0_SCL 22 GND
3 SoC_I2C0_SDA 23 CH1_LVDS_A3N
4 NC 24 CH1_LVDS_A3P
5 NC 25 GND
6 GND 26 CH1_LVDS_A0N
7 GND 27 CH2_LVDS_A0P
8 OLDI_RESETn 28 GND
9 TS_INT# 29 CH2_LVDS_A1N
10 GND 30 CH2_LVDS_A1P
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Table 2-4. Display Connector Pinout (As used by display and the E3 EVM) (continued)
Pin no. Signal Pin no. Signal
11 CH1_LVDS_A0N 31 GND
12 CH1_LVDS_A0P 32 CH2_LVDS_CLKN
13 GND 33 CH2_LVDS_CLKP
14 CH1_LVDS_A1N 34 GND
15 CH1_LVDS_A1P 35 CH2_LVDS_A2N
16 GND 36 CH2_LVDS_A2P
17 CH1_LVDS_CLKN 37 GND
18 CH1_LVDS_CLKP 38 CH2_LVDS_A3N
19 GND 39 CH2_LVDS_A3P
20 CH1_LVDS_A2N 40 GND
Table 2-5. Display Connector Pinout (E1/E2)
Pin no. Signal Pin no. Signal
40 VCC_3V3_SYS(EEPROM_VDD) 20 CH1_LVDS_A2P
39 GND 19 GND
38 SoC_I2C0_SCL 18 GND
37 SoC_I2C0_SDA 17 CH1_LVDS_A3N
36 NC 16 CH2_LVDS_A0N
35 NC 15 CH1_LVDS_A3P
34 NC 14 CH2_LVDS_A0P
33 TS_INT 13 GND
32 TS_RST 12 GND
31 GND 11 CH2_LVDS_A1N
30 GND 10 CH2_LVDS_CLKN
29 CH1_LVDS_A0N 9 CH2_LVDS_A1P
28 CH1_LVDS_A1N 8 CH2_LVDS_CLKP
27 CH1_LVDS_A0P 7 GND
26 CH1_LVDS_A1P 6 GND
25 GND 5 CH2_LVDS_A2N
24 GND 4 CH2_LVDS_A3N
23 CH1_LVDS_CLKN 3 CH2_LVDS_A2P
22 CH1_LVDS_A2N 2 CH2_LVDS_A3P
21 CH1_LVDS_CLKP 1 GND
2.6.4 CSI Interface
The CSI-2 interface from the AM62x SoC is terminated to a 15 pin Camera FPC connector 1-1734248-5
compatible with the RPi Camera Modules. These modules support 2 Lane CSI RX signals. While the SoC
supports 4 CSI RX Lanes, only two are pinned out on the SKEVM
The CSI connector pin-out is compatible with the RPi camera connector. The Table 2-6 contains 15 pin CSI
Connector pin-out. SoC I2C1 signals are also connected to the CSI Header. IO Expander GPIO signals are
connected to the camera GPIO’s.
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Table 2-6. CSI Camera Connector J19 Pin-out
Pin No Pin Description
1 Ground
2 CSI0_RXN0
3 CSI0_RXP0
4 Ground
5 CSI0_RXN1
6 CSI0_RXP1
7 Ground
8 CSI0_RXCLKN
9 CSI0_RXCLKP
10 Ground
11 CSI_GPIO1
12 CSI_GPIO2
13 SoC_I2C1_SCL
14 SoC_I2C1_SDA
15 VCC_3V3_SYS
2.6.5 Audio Codec Interface
AM62x SKEVM has TI‘s Low-Power TLV320AIC3106 Stereo Audio Codec to interface with AM62x via McASP.
TLV320AIC3106 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple
inputs and outputs programmable in single ended or fully differential configurations. The record path of the
TLV320AIC3106 contains integrated microphone bias, digitally controlled stereo microphone preamplifier and
automatic gain control (AGC) with mix/Mux capability among the multiple analog inputs. The stereo audio DAC
supports sampling rates from 8 kHz to 96 kHz.
1x Standard 3.5 mm TRRS Audio Jack connector Mfr. Part# SJ-43514 shall be provided for MIC and Headphone
output. Audio Codec’s Line inputs are terminated to Testpoints.
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SELECT pin shall be held LOW to select I2C as control interface. Codec can be configured over I2C interface,
where I2C address can be set by driving pins MFP0 and MFP1 pin either high or low. Both these pins are set
to high, so the Device address is set to 0x1B. Unused inputs and outputs of the Audio Codec are connected to
ground.
The Controller Clock input, MCLK to the Audio Codec is provided through a 12.288MHz Oscillator. Audio serial
data bus bit clock BCLK of \the codec is driven by the AM62x SoC through a buffer. Audio serial data bus input
and output DIN, DOUT are connected to SoC’s MCASP2_AXR2 and MCASP2_AXR3 through buffers. An AND
output of RESETSTATz and a GPIO sourced via IO expander are used to reset the Audio codec.
The TLV320AIC3106 is powred by an analog supply of 3.3 V, a digital core supply of 1.8 V, and a digital I/O
supply 3.3 V.
2.6.6 HDMI Display Interface
The DSS (Display Sub system) interface from AM62x SoC is used on the SKEVM to provide a HDMI
Interface through a standard Type-A Connector. The SKEVM features a SiI9022A HDMI Transmitter from Lattice
semiconductors to convert the 24bit Parallel RGB DSS output stream as well as a McASP to a HDMI-compliant
digital audio and video signal.
The Data mapping format used is RGB888. The data bus width is 24-bits.
SoC_I2C1 is connected to the HDMI Transmitter to access the compatible mode registers, the TPI registers,
and the CPI registers. In order to use the SiI9022A, the SoC needs to setup the device. This is done via the
I2C interface between the SoC and the SiI9022A. Audio Data is sent from SoC to HDMI transmitter through the
McASP1 instance. HDMI_I2C Bus accesses the EDID and HDCP data on an attached sink device.
TMDS Differential data pairs along with the differential clock signals from the transmitter are connected to the
HDMI connector through HDMI ESD device Mfr Part# TPD12S016PWR which also acts as a load switch to limit
current supplied to the HDMI connector from board 5 V supply.
The HDMI Framer is powered using 3.3 V Board IO Supply and 1.2 V by a dedicated LDO Mfr Part#
TLV75512PDQNR.
www.ti.com System Description
SPRUJ40A – MAY 2022 – REVISED FEBRUARY 2023
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AM62x SK EVM User's Guide 19
Copyright © 2023 Texas Instruments Incorporated

Note
Please see the Known Issues section of this document. The SK-AM62 E1 board was intended to
feature 16bit YUV 422 video output but was wired incorrectly. E2 and newer variants of SK-AM62 as
well as all variants of SK-AM62-P1 feature the full 24 bit Parallel RGB888 Interface.
2.6.7 JTAG Interface
AM62x SKEVM board include XDS110 class on board emulation. The connection for the emulator uses an USB
2.0 micro-B connector and the circuit acts as a Bus powered USB device. The VBUS power from the connector
will be used to power the emulation circuit such that connection to the emulator is not lost when the power to
the SKEVM is removed. Voltage translation buffers are used to isolate the XDS110 circuit from the rest of the
SKEVM.
Optionally, JTAG Interface on SKEVM is also provided through 20 Pin Standard JTAG cTI Header J17. This
allows the user to connect an external JTAG Emulator Cable. Voltage translation buffers are used to isolate the
JTAG signals from cTI header from the rest of the SKEVM. The output from the voltage translators from XDS110
Section and cTI Header Section are muxed and connected to AM62x JTAG Interface. If a connection to the cTI
20 Pin JTAG connector is sensed using a presence detect circuit, the mux will be set to route the 20 pin signals
from the cTI connector to the AM62x SoC in place of the on-board emulation circuit.
System Description www.ti.com
20 AM62x SK EVM User's Guide SPRUJ40A – MAY 2022 – REVISED FEBRUARY 2023
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Copyright © 2023 Texas Instruments Incorporated