Texas Instruments DAC 1401 Series User manual

EVM User's Guide: DAC81401EVM
DAC81401 Evaluation Module
Description
The 16-bit DAC81401 and 12-bit DAC61401
(DACx1401) are a pin-compatible family of single-
channel, buffered, high-voltage-output digital to-
analog converters (DACs) with an integrated 2.5-
V internal reference. These devices are specified
monotonic and provide exceptional linearity of less
than 1 LSB.
Get Started
1. Order the EVM.
2. Configure EVM jumpers.
3. Install DAC814xxEVM GUI from ti.com.
4. Connect USB and external power supplies.
5. Launch DAC814xxEVM GUI.
Features
• Configurable circuit to evaluate DAC
• Onboard VDD and IOVDD (1.8-V or 3.3-V) support
• High-voltage 4× gain stage is available to support
up to an 80-V output
• Output protection circuit on gain output stage
• Trigger output is available for synchronous
measurement
• FT4232 used to easily write to DAC using
DAC814xxEVM GUI
• External SPI connections available
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1 Evaluation Module Overview
1.1 Introduction
The DACx1401 devices offer bipolar output voltages of ±20 V, ±10 V, ±5 V, and full-scale unipolar output
voltages of 40 V, 10 V and 5 V. The DAC output range is programmable.
This user's guide describes the characteristics, operation, and recommended use cases of the DAC81401EVM.
This document provides examples and instructions on how to use the DAC81401EVM board and included
software. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous
with the DAC81401EVM. This document also includes a schematic, reference printed circuit board (PCB)
layouts, and a complete bill of materials (BOM).
1.2 Kit Contents
Table 1-1 details the contents of the EVM kit. Contact the TI Product Information Center at [phone] if any
component is missing. Download the latest versions of the related software on the TI website, www.ti.com.
Table 1-1. DAC81401EVM Kit Contents
Item Quantity
DAC81401EVM 1
USB-A to Micro-USB Cable 1
1.3 Specification
Figure 1-1 shows the block diagram of the DAC81401EVM board. By default, the DAC81401EVM connects to a
local machine USB port through a USB-A to Micro-USB cable.
USB
Micro
FTDI
Controller
Level
Shifter DAC81401
High Voltage
Gain(=4)
Stage
LDOs
High Voltage Output
DAC81401 Output
Optional Blocks
Trigger
Digital
Headers
DAC81401 Power Suplies
Supply
Selection
External HV
Supply
Figure 1-1. DAC81401EVM Functional Block Diagram
The USB provides the 5 V default DVDD supply to the DAC81401. Voltage regulators generates 3.3 V and 1.8
V from USB 5 V supply. These 3.3 V and 1.8 V supplies are used to power the FTDI controller, level shifter and
IOVDD of DAC81401. IOVDD can be 3.3-V or 1.8-V depending on the jumper J5 setting. DVDD and IOVDD
device supply inputs for the DAC81401 can be externally supplied through J7 and J6 banana jacks respectively,
with proper settings of jumpers J1 and J5. DAC81401 AVDD and AVSS (can be GND through jumper J2) needs
external power supply connection through J3 and J4 banana jacks respectively.
Optional High voltage gain stage needs separate power supply through J13 and J15 banana jacks. This high
voltage stage provides 4 times gained DAC81401 output voltage, up to 0-80 V or ± 40-V. Attenuated output
voltage by 4, is used on the VSENSEP to close the loop properly on DAC81401 side.
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1.4 Device Information
The documents in Table 1-2 provide information regarding Texas Instruments integrated circuits used in the
assembly of the DAC81401EVM. This user's guide is available from the TI web site under literature number
SLAU905. Any letter appended to the literature number corresponds to the document revision that is current at
the time of the writing of this document. Newer revisions are available from the TI web site at www.ti.com, or call
the Texas Instruments Literature Response Center at [phone] or the Product Information Center at (972)
644-5580. When ordering, identify the document by both title and literature number.
Table 1-2. Related Device Documentation
Document Literature Number
DAC81401 product data sheet SLAU905
OPA593 product data sheet SBOS659
OPA189 product data sheet OPA189
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2 Software
2.1 GUI Installation
This section provides the procedure for EVM software installation.
The EVM software is compatible with the Windows® 10 operating system. Before installing the software, make
sure that the DAC80401EVM is not connected to the local machine.
Download the latest version of the EVM graphical user interface (GUI) installer from the Order and start
development subsection of the DAC81401EVM tool folder on TI.com. Run the GUI installer to install the
DAC81401EVM GUI software on your local machine.
When the DAC804xxEVM GUI is launched, an installation dialog window opens and prompts the user to select
an installation directory. If left unchanged, Figure 2-1 shows that the software location defaults to C:\Program
Files (x86)\Texas Instruments\DAC814xxEVM.
Figure 2-1. Software Installation Path
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The EVM software also installs the Future Technology Devices International Limited (FTDI) USB drivers using
a separate executable file. Figure 2-2 shows the FTDI USB drivers installation window that is automatically
launched after the DAC814xxEVM software installation is complete.
Figure 2-2. FTDI USB Drivers
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2.2 Software Description
To launch the software, locate the DAC814xxEVM folder in the Start Menu, and select the DAC814xxEVM icon
as shown in Figure 2-3.
Figure 2-3. DAC814xxEVM Software Installation in Start Menu
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Figure 2-4 shows that if the onboard FTDI controller is connected correctly, then the status bar at the bottom of
the screen displays CONNECTED. If the controller is not properly connected or not connected at all, then the
status displays DEMO. If the graphical user interface (GUI) does not display the CONNECTED status while the
EVM is connected, then unplug and reconnect the EVM and relaunch the GUI software.
Figure 2-4. DAC814xxEVM GUI Connection Detection
DAC81401 High Level page provides quick access to basic DAC81401 functionality as shown in Figure 2-5.
Figure 2-5. DAC81401EVM High Level Page
The DAC81401 Registers page, shown in Figure 2-6, allows the user to access low-level communication directly
with the DAC81401 registers. Selecting a register on the Register Map list shows a description of the values in
that register, as well as information on the register address, default value, size, and current value. Values are
read from and written to the registers by writing to the Value or bit field of the GUI.
The Register Map page also provides the FTDI GPIO controls for DAC81401EVM. For example, OPE_EN, TRIG
and FAULT pins, under the FTDI section.
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Figure 2-6. DAC81401EVM Registers Page
To store the values of the register map locally, select Save Configuration under the File menu option. The stored
configuration files can be recalled and loaded by selecting Open Configuration as shown in Figure 2-7.
Figure 2-7. DAC81401EVM Save/Open Configuration
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3 Hardware
3.1 Power Requirements
The USB connection at J12 provides 5 V to the EVM. This connection is necessary if using the DAC814xxEVM
GUI, as the communication is done through the USB port and the FT4232 is powered by one of the LDOs on
the board. On board supplies for DVDD (5-V USB supply through J1) and IOVDD ( LDO generated 1.8-V or
3.3-V through J5) are also available. DVDD and IOVDD power supply of DAC81401 can be provided externally
through J5 and J7 respectively. AVDD and AVSS power supply of DAC81401 need to connected externally
through J3 and J4 respectively. AVSS can be connected to GND through J2. Optional EXT HV POS (V+) and
EXT HV NEG (V-) supplies are needed for OPA593 (U2, U5) while using the high-voltage gain stage.
• AVDD : 0 to 41.5 V (default + 15 V)
• AVSS : 0 to -21.5 V (default - 15 V)
• DVDD : 4.5 V to 5.5 V (default + 5 V)
• IOVDD : 1.7 V to 5.5 V (default + 3.3 V)
• (AVDD - AVSS) must not be greater than 43 V
• EXT HV POS (V+) - EXT HV NEG : ± 4 V to ±42.5 V or 8 V to 85 V (default ± 25 V)
Table 3-1 summarizes the external power connections.
Table 3-1. DAC81401EVM Power Supply Inputs
Terminal Name Function
J3 AVDD Positive supply voltage for the DAC81401 output buffers
J4 AVSS Negative supply voltage for DAC81401 output buffers
J5 DVDD Digital and analog supply voltage for the DAC81401
J7 IOVDD IO supply voltage for setting the digital I/O operating voltage for the DAC81401
J9 GND Ground connection
J13 EXT HV POS Optional positive supply for high voltage gain stage operational amplifier
J14 GND Ground connection
J15 EXT HV NEG Optional negative supply for high voltage gain stage operational amplifier
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3.2 Jumper Information
The jumpers must be connected properly to operate the DAC81401EVM for it's intended operation. Table 3-2
provides the details of the configurable jumper settings on the EVM. Figure 3-1 and Figure 3-2 shows the default
jumper connections on the board with High-voltage gain stage enabled and High-voltage gain stage disabled
respectively.
Table 3-2. DAC81401EVM Jumper Summary
Header Name Function
J1 DVDD=USB5V Short 1-2 – DVDD = 5 V supplied through USB power (default)
Open – DVDD supplied through J6
J2 AVSS SEL Short 1-2 – AVSS supplied through J3
Short 2-3 – AVSS connected to board GND (default)
Open – AVSS supply pin is floating (not recommended)
J5 IOVDD SEL Short 1-2 – IOVDD = 1.8V supplied through LDO (U12) output
Short 2-3 – IOVDD = 3.3V supplied through LDO (U11) output (default)
Open – IOVDD = 1.8V supplied through J7
J17 VOUT-GND SEL Short 1-2 – OPA593 +IN (U2)connected to DAC81401 output
Short 2-3 – OPA593 +IN (U2) connected to GND (default)
Open – OPA593 +IN (U2) pin is floating (not recommended)
J18 DAC CHANNEL TP Short 1-2 – OPA593 OUT (U2) connected to OPA593 +IN (U5) pin
Short 3-4 – DAC81401 VSENSEN pin connected to GND
Open(1-2 and 3-4) – High voltage gain stage is not connected to DAC81401
(default)
J19 PULL-UP Short 1-2 – pulled down to GND and OPA593 (U2,U5) is in power down mode
Open – OPA_EN = 1 bit : OPA593 (U2,U5) is in active mode and OPA_EN bit = 0:
OPA593 (U2,U5) is in active mode (default)
J21 VSENSEN Short 1-2 – VSENSEN of high voltage gain stage is connected to DAC81401
VSENSEN pin
Open – VSENSEN of high voltage gain stage is open (default)
J24 VSENSEP Short 1-2 – VSENSEP of high voltage gain stage is connected to DAC81401
VSENSEP pin
Open – VSENSEP of high voltage gain stage is open (default)
J22 LEVEL SHIFT ENABLE Short 1-2 – Digital buffers (U8,U10) enabled
Open – Digital buffers (U8,U10) disabled
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