Texas Instruments DAC 1401 Series User manual

EVM User's Guide: DAC81401EVM
DAC81401 Evaluation Module
Description
The 16-bit DAC81401 and 12-bit DAC61401
(DACx1401) are a pin-compatible family of single-
channel, buffered, high-voltage-output digital to-
analog converters (DACs) with an integrated 2.5-
V internal reference. These devices are specified
monotonic and provide exceptional linearity of less
than 1 LSB.
Get Started
1. Order the EVM.
2. Configure EVM jumpers.
3. Install DAC814xxEVM GUI from ti.com.
4. Connect USB and external power supplies.
5. Launch DAC814xxEVM GUI.
Features
• Configurable circuit to evaluate DAC
• Onboard VDD and IOVDD (1.8-V or 3.3-V) support
• High-voltage 4× gain stage is available to support
up to an 80-V output
• Output protection circuit on gain output stage
• Trigger output is available for synchronous
measurement
• FT4232 used to easily write to DAC using
DAC814xxEVM GUI
• External SPI connections available
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1 Evaluation Module Overview
1.1 Introduction
The DACx1401 devices offer bipolar output voltages of ±20 V, ±10 V, ±5 V, and full-scale unipolar output
voltages of 40 V, 10 V and 5 V. The DAC output range is programmable.
This user's guide describes the characteristics, operation, and recommended use cases of the DAC81401EVM.
This document provides examples and instructions on how to use the DAC81401EVM board and included
software. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous
with the DAC81401EVM. This document also includes a schematic, reference printed circuit board (PCB)
layouts, and a complete bill of materials (BOM).
1.2 Kit Contents
Table 1-1 details the contents of the EVM kit. Contact the TI Product Information Center at [phone] if any
component is missing. Download the latest versions of the related software on the TI website, www.ti.com.
Table 1-1. DAC81401EVM Kit Contents
Item Quantity
DAC81401EVM 1
USB-A to Micro-USB Cable 1
1.3 Specification
Figure 1-1 shows the block diagram of the DAC81401EVM board. By default, the DAC81401EVM connects to a
local machine USB port through a USB-A to Micro-USB cable.
USB
Micro
FTDI
Controller
Level
Shifter DAC81401
High Voltage
Gain(=4)
Stage
LDOs
High Voltage Output
DAC81401 Output
Optional Blocks
Trigger
Digital
Headers
DAC81401 Power Suplies
Supply
Selection
External HV
Supply
Figure 1-1. DAC81401EVM Functional Block Diagram
The USB provides the 5 V default DVDD supply to the DAC81401. Voltage regulators generates 3.3 V and 1.8
V from USB 5 V supply. These 3.3 V and 1.8 V supplies are used to power the FTDI controller, level shifter and
IOVDD of DAC81401. IOVDD can be 3.3-V or 1.8-V depending on the jumper J5 setting. DVDD and IOVDD
device supply inputs for the DAC81401 can be externally supplied through J7 and J6 banana jacks respectively,
with proper settings of jumpers J1 and J5. DAC81401 AVDD and AVSS (can be GND through jumper J2) needs
external power supply connection through J3 and J4 banana jacks respectively.
Optional High voltage gain stage needs separate power supply through J13 and J15 banana jacks. This high
voltage stage provides 4 times gained DAC81401 output voltage, up to 0-80 V or ± 40-V. Attenuated output
voltage by 4, is used on the VSENSEP to close the loop properly on DAC81401 side.
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1.4 Device Information
The documents in Table 1-2 provide information regarding Texas Instruments integrated circuits used in the
assembly of the DAC81401EVM. This user's guide is available from the TI web site under literature number
SLAU905. Any letter appended to the literature number corresponds to the document revision that is current at
the time of the writing of this document. Newer revisions are available from the TI web site at www.ti.com, or call
the Texas Instruments Literature Response Center at [phone] or the Product Information Center at (972)
644-5580. When ordering, identify the document by both title and literature number.
Table 1-2. Related Device Documentation
Document Literature Number
DAC81401 product data sheet SLAU905
OPA593 product data sheet SBOS659
OPA189 product data sheet OPA189
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2 Software
2.1 GUI Installation
This section provides the procedure for EVM software installation.
The EVM software is compatible with the Windows® 10 operating system. Before installing the software, make
sure that the DAC80401EVM is not connected to the local machine.
Download the latest version of the EVM graphical user interface (GUI) installer from the Order and start
development subsection of the DAC81401EVM tool folder on TI.com. Run the GUI installer to install the
DAC81401EVM GUI software on your local machine.
When the DAC804xxEVM GUI is launched, an installation dialog window opens and prompts the user to select
an installation directory. If left unchanged, Figure 2-1 shows that the software location defaults to C:\Program
Files (x86)\Texas Instruments\DAC814xxEVM.
Figure 2-1. Software Installation Path
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The EVM software also installs the Future Technology Devices International Limited (FTDI) USB drivers using
a separate executable file. Figure 2-2 shows the FTDI USB drivers installation window that is automatically
launched after the DAC814xxEVM software installation is complete.
Figure 2-2. FTDI USB Drivers
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2.2 Software Description
To launch the software, locate the DAC814xxEVM folder in the Start Menu, and select the DAC814xxEVM icon
as shown in Figure 2-3.
Figure 2-3. DAC814xxEVM Software Installation in Start Menu
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Figure 2-4 shows that if the onboard FTDI controller is connected correctly, then the status bar at the bottom of
the screen displays CONNECTED. If the controller is not properly connected or not connected at all, then the
status displays DEMO. If the graphical user interface (GUI) does not display the CONNECTED status while the
EVM is connected, then unplug and reconnect the EVM and relaunch the GUI software.
Figure 2-4. DAC814xxEVM GUI Connection Detection
DAC81401 High Level page provides quick access to basic DAC81401 functionality as shown in Figure 2-5.
Figure 2-5. DAC81401EVM High Level Page
The DAC81401 Registers page, shown in Figure 2-6, allows the user to access low-level communication directly
with the DAC81401 registers. Selecting a register on the Register Map list shows a description of the values in
that register, as well as information on the register address, default value, size, and current value. Values are
read from and written to the registers by writing to the Value or bit field of the GUI.
The Register Map page also provides the FTDI GPIO controls for DAC81401EVM. For example, OPE_EN, TRIG
and FAULT pins, under the FTDI section.
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Figure 2-6. DAC81401EVM Registers Page
To store the values of the register map locally, select Save Configuration under the File menu option. The stored
configuration files can be recalled and loaded by selecting Open Configuration as shown in Figure 2-7.
Figure 2-7. DAC81401EVM Save/Open Configuration
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3 Hardware
3.1 Power Requirements
The USB connection at J12 provides 5 V to the EVM. This connection is necessary if using the DAC814xxEVM
GUI, as the communication is done through the USB port and the FT4232 is powered by one of the LDOs on
the board. On board supplies for DVDD (5-V USB supply through J1) and IOVDD ( LDO generated 1.8-V or
3.3-V through J5) are also available. DVDD and IOVDD power supply of DAC81401 can be provided externally
through J5 and J7 respectively. AVDD and AVSS power supply of DAC81401 need to connected externally
through J3 and J4 respectively. AVSS can be connected to GND through J2. Optional EXT HV POS (V+) and
EXT HV NEG (V-) supplies are needed for OPA593 (U2, U5) while using the high-voltage gain stage.
• AVDD : 0 to 41.5 V (default + 15 V)
• AVSS : 0 to -21.5 V (default - 15 V)
• DVDD : 4.5 V to 5.5 V (default + 5 V)
• IOVDD : 1.7 V to 5.5 V (default + 3.3 V)
• (AVDD - AVSS) must not be greater than 43 V
• EXT HV POS (V+) - EXT HV NEG : ± 4 V to ±42.5 V or 8 V to 85 V (default ± 25 V)
Table 3-1 summarizes the external power connections.
Table 3-1. DAC81401EVM Power Supply Inputs
Terminal Name Function
J3 AVDD Positive supply voltage for the DAC81401 output buffers
J4 AVSS Negative supply voltage for DAC81401 output buffers
J5 DVDD Digital and analog supply voltage for the DAC81401
J7 IOVDD IO supply voltage for setting the digital I/O operating voltage for the DAC81401
J9 GND Ground connection
J13 EXT HV POS Optional positive supply for high voltage gain stage operational amplifier
J14 GND Ground connection
J15 EXT HV NEG Optional negative supply for high voltage gain stage operational amplifier
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3.2 Jumper Information
The jumpers must be connected properly to operate the DAC81401EVM for it's intended operation. Table 3-2
provides the details of the configurable jumper settings on the EVM. Figure 3-1 and Figure 3-2 shows the default
jumper connections on the board with High-voltage gain stage enabled and High-voltage gain stage disabled
respectively.
Table 3-2. DAC81401EVM Jumper Summary
Header Name Function
J1 DVDD=USB5V Short 1-2 – DVDD = 5 V supplied through USB power (default)
Open – DVDD supplied through J6
J2 AVSS SEL Short 1-2 – AVSS supplied through J3
Short 2-3 – AVSS connected to board GND (default)
Open – AVSS supply pin is floating (not recommended)
J5 IOVDD SEL Short 1-2 – IOVDD = 1.8V supplied through LDO (U12) output
Short 2-3 – IOVDD = 3.3V supplied through LDO (U11) output (default)
Open – IOVDD = 1.8V supplied through J7
J17 VOUT-GND SEL Short 1-2 – OPA593 +IN (U2)connected to DAC81401 output
Short 2-3 – OPA593 +IN (U2) connected to GND (default)
Open – OPA593 +IN (U2) pin is floating (not recommended)
J18 DAC CHANNEL TP Short 1-2 – OPA593 OUT (U2) connected to OPA593 +IN (U5) pin
Short 3-4 – DAC81401 VSENSEN pin connected to GND
Open(1-2 and 3-4) – High voltage gain stage is not connected to DAC81401
(default)
J19 PULL-UP Short 1-2 – pulled down to GND and OPA593 (U2,U5) is in power down mode
Open – OPA_EN = 1 bit : OPA593 (U2,U5) is in active mode and OPA_EN bit = 0:
OPA593 (U2,U5) is in active mode (default)
J21 VSENSEN Short 1-2 – VSENSEN of high voltage gain stage is connected to DAC81401
VSENSEN pin
Open – VSENSEN of high voltage gain stage is open (default)
J24 VSENSEP Short 1-2 – VSENSEP of high voltage gain stage is connected to DAC81401
VSENSEP pin
Open – VSENSEP of high voltage gain stage is open (default)
J22 LEVEL SHIFT ENABLE Short 1-2 – Digital buffers (U8,U10) enabled
Open – Digital buffers (U8,U10) disabled
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Figure 3-1. Default Header Settings with High Voltage Gain Stage Enabled
Figure 3-2. Default Header Settings with High Voltage Gain Stage Disabled
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3.3 Setup
After the power and jumper configurations are set up per Figure 3-1 or Figure 3-2 , and the DAC814xxEVM
GUI is fully installed, connect the USB cable from the DAC81401EVM USB port to the local machine. Figure 3-3
displays the system hardware setup.
USB/Digital
Control DAC81401 High Voltage Gain (=4) Stage
DAC81401 Power
Supplies
External HV
Supply
High Voltage Output
DAC81401 Output
DAC814xxEVM
GUI
Optional blocks
Figure 3-3. DAC81401EVM Hardware Setup
Once all the connection is done, power up the DAC81401EVM hardware as described in the power requirement
section 3-1.
For basic DAC81401 device check, use one of the following sequences in the DAC814xxEVM GUI:
•From DAC81401 Register page
– Write 0x0A24 to the SPI_CONFIG (0x03) register to power up the device
– Write 0x0000 to the GEN_CONFIG (0x04) register to power up the internal reference
– Write 0x0000 to the DAC_PWDWN (0x09) register to power up the DAC output
– Write 0x7FFF to the DAC (0x10) register to configure the DAC_OUT to 2.5-V on DAC_OUT (TP4) or 10 V
on TP18 (pin-1) while high voltage gain stage is active
•From DAC81401 High Level page
– Device Power Down: select Active mode to power up the device
– Reference Power-Down: select Activate internal ref to power up the internal reference
– DAC Channel Power-Down: select Activate channel to power up the DAC output
– DAC_DATA: write 0x7FFF to get 2.5-V on DAC_OUT (TP4) or 10 V on TP18 (pin-1) while high voltage
gain stage is active
The default voltage range for the DAC81401 is 0 V to 5 V. Configure the voltage range by modifying the "DAC
Voltage Range" control on DAC814xxEVM GUI High Level page, or by writing to the "DAC_RANGE" register in
the Low Level page as shown in section 2-2.
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3.4 Header Information
The EVM provides access to the DAC81401 digital pins through header J12. Table 3-3 lists the J12 pin
definitions.
Table 3-3. DAC81401EVM Header J12 Pin Definitions
Pin Number Signal Description
1FAULT DAC81401 FAULT output
3SYNC DAC81401 chip-select input
5SDO DAC81401 serial data output
7 SDI DAC81401 serial data input
9 SCLK Serial-clock input
2,4,6,8,10 GND Ground
The pins on J12 can be used to externally control the DAC81401 with SPI commands if the FTDI controller is
disconnected from the DAC, by opening the J22 jumper.
3.5 Test Points
The DAC81401EVM has a variety of test points available for measuring and debugging purposes. Table 3-4
explains the purpose of each test point.
Table 3-4. DAC81401EVM Test Points
Test Point Net Description
TP4 DAC_VOUT DAC81401 output
TP6 VREF DAC81401 reference voltage
TP7 AVDD DAC8140 1 AVDD
TP8 AVSS DAC81401 AVSS
TP9 DVDD DAC81401 DVDD
TP10 IOVDD DAC81401 IOVDD
TP12,TP13,TP14,TP16,TP16 GND Ground connection
TP17 Current flag (U2) Current flag output of OPA593 (U2)
TP18 Thermal flag (U2) Thermal flag output of OPA593 (U2)
TP19 DAC_OUT
= 4×
High voltage gain BY 4× output for DAC81401 DAC_OUT
TP20 DAC VSENSEP HV Attenuated by 4X output for DAC81401 VSENSEP
TP21 3P3V 3.3-V LDO output
TP22 1P8V 1.8-V LDO output
TP23 TRIG FTDI trigger pin
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4 Hardware Design Files
4.1 Schematics
Figure 4-1 through Figure 4-4 shows the DAC81401EVM schematic. Components not populated on the
DAC81401EVM board are marked with red cross and "DNI*" text.
SDO
SDI
SCLK
SYNC
FAULT
OPA_EN
FTDI
DC260E1_FTDI.SchDoc
SCLK
SYNC
FAULT
SDI
SDO
DAC_OUT
DAC_VSENSEP
DAC_VSENSEN
DAC
DC260E1_DAC.SchDoc
Hardware
DC260E1_Hardware.SchDoc
OPA_EN
DAC_OUT
DAC_VSENSEP
DAC_VSENSEN
Gain = 4x
DC260E1_DAC_VOUT_gain_4x.SchDoc
DAC OUT HV
Figure 4-1. DAC81401EVM Schematic : Top Level Blocks
GND
AVSS
GND
GND
GND
GND
IOVDD
DVDD
AVDD
VREF
IOVDD
1P8V
IOVDD
3P3V
USB_VBUSDVDD
GND
GND
SCLK
SYNC
FAULT
SDI
SDO
GND
GND
GND
AVDD
DVDD
IOVDD
GND
DAC_VOUT
DAC_VOUT
DAC_VOUT DAC_OUT
DAC_VSENSEP
DAC_VSENSEN
AVDD
5
DVDD
20
IOVDD
17
FAULT
12
SYNC
16
CCOMP 7
SCLK
14
SDIN
15
SDO
13
VOUT 9
VREFIO
1
VSENSEN 11
VSENSEP 10
NC 4
NC 6
NC 8
NC 18
AVSS 3
DVSS 19
VREFGND 2
DAC81401PWR
U1
SH-1
1
2
1
2
3
J5IOVDD SEL
4
1
2
3
J10
DAC CHANNEL TP
0.1µF
C9
0.1µF
C2
0.1µF
C4
0.1µF
C6
0.1µF
C10
SH-4SH-5
1
2
3
4
J6 DVDD
J3 AVDD
J4 AVSS
J7 IOVDD
J9 GND
0
R4470pF
C7
Figure 4-2. DAC81401EVM Schematic : DAC81401 Interface
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GND
GND
GND
GND
OPA_EN
GND
GND
EXT_HV+
EXT_HV-
EXT_HV-
High voltage buffer with gain of 4x
0-85V or +/-42.5V
GND
GND
GND
EXT_HV-
IOVDD
GND
GND
DAC_OUT
DAC_VSENSEP
DAC_VSENSEN
EXT_HV+
EXT_HV+
GND
OPA_ENABLE
DAC_VOUT gain = 4x
VSENSEP attenuation = 1/4
GND
GND
OPA_ENABLE
GND
GND
AVDD
AVSS
GND
GND
AVDD
AVSS
GND
VSENSEP_HV
EXT_HV+
EXT_HV-
GND
EXT_HV+
EXT_HV-
GND
VSENSEP_HV
GND
AVSS
AVDD
IOVDD
1
2
3
J17
VOUT-GND SEL
Thermal_Flag 8
Thermal_Pad 13
+IN
4
-IN
3
Current_Flag 7
E/D
12
E/D_Com
1
ISET
11
OUT 9
V+
10
V- 6
NC 2
NC 5
OPA593DNT
U2
0.1µF
C15
0.1µF
C17
J13
EXT HV POS
J15
EXT HV NEG
J14
GND
TP19
DAC OUT = 4X
TP17
CURRENT FLAG
TP18
THERMAL FLAG
Thermal_Flag
8
Thermal_Pad
13
+IN 4
-IN 3
Current_Flag
7
E/D 12
E/D_Com 1
ISET 11
OUT
9
V+ 10
V-
6
NC
2
NC
5
OPA593DNT
U5
0.1µF
C22
10.0k
R8 4
1
2
3
J18
DAC CHANNEL TP
SH-7SH-8
1
2
3
4
J16
DAC CHANNEL TP
0.1µF
C19
TP20
DAC VSENSEP HV
10uF
C12
10uF
C14
1uF
C11
1uF
C13
SH-6
0.1µF
C16
0.1µF
C18
0
R10
0.1µF
C20
0.1µF
C21
10.0
R7
1.00k
R11
1.00k
R15
1
2
J19
PULL-UP
15.0k
R13
4.99k
R12
15.0k
R16
4.99k
R18
Figure 4-3. DAC81401EVM Schematic : High Voltage Gain Stage
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GNDUSB_SHIELD
SDI SDI
SCLK
SDO
GND
OE_ENABLE
GND OE_ENABLE
GND
GND
GND
3P3V 1P8V 3P3V
FAULT
FAULTz
USB_VBUS USB_VBUS
3P3V
3P3V
1P8V
3P3V
GND
USB_VBUS
GND
GND
5V to 3.3V supply generation
GND
GND
GND
GND
GND
GND OE_ENABLE
GND
IOVDD3P3V
3P3V IOVDD
FTDI_FAULT
5V to 1.8V supply generation
GND
FTDI_TRIG
GND
Level shifter enabele
SYNC
SDO
FTDI_OPA_EN
FTDI_OPA_EN OPA_EN
USB Connector Interface
USB to SPI/I2C Conversion
GND
100nF
C28
100nF
C31
1 2
Y1
0
R26
1.00M
R24
10.0
R20
10.0
R19
10.0k
R21
330
R25
12.0k
R22
47.0k
R23
470nF
C27
L1 4.7µF
C25
100nF
C26
4.7µF
C34
4.7µF
C35
100nF
C23
100nF
C24
10.0k
R27
100nF
C29
100nF
C30
100nF
C36
100nF
C37
20pF
C32
20pF
C33
Figure 4-4. DAC81401EVM Schematic : FTDI Controller Interface
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4.2 PCB Layouts
Figure 4-5 through Figure 4-8 show the board layout for the DAC81401EVM.
Figure 4-5. DAC81401EVM PCB Top Layer Layout
Figure 4-6. DAC81401EVM PCB Mid Layer 1 Layout
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Figure 4-7. DAC81401EVM PCB Mid Layer 2 Layout
Figure 4-8. DAC81401EVM PCB Bottom Layer Layout
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4.3 Bill of Materials (BOM)
Table 4-1 lists the DAC81401EVM bill of materials (BOM).
Table 4-1. Bill of Materials for the DAC81401EVM
Designator Qty Value Description Package
Reference Part Number Manufacturer Assembly
Details
C1,C3,C5,C8 4 1 µF CAP, CERM, 1 uF, 50 V, +/-
10%, X5R, 0603
0603 885012206126 Wurth
Elektronik
Installed
C2, C4, C6,
C9, C10
50.1 µF CAP, CERM, 0.1 µF, 50 V,+/-
10%, X7R, AEC-Q200 Grade
1, 0402
0402 885012205086 Wurth
Elektronik
Installed
C7 1 470 pF Cap Ceramic 470 pF 50 V
C0G 1% SMD 0603 125°C
Paper T/R
0603 885012006061 Wurth
Elektronik
Installed
C11,C13 21 µF CAP, CERM, 1 uF, 100 V, +/-
10%, X7S, AEC-Q200 Grade
1, 0805
0805_HV CGA4J3X7S2A105K12
5AB
TDK Installed
C12,C14 210 µF CAP, CERM, 10 uF, 100
V,+/- 20%, X7S, AEC-Q200
Grade 1, 1812
CKG45N_500 CKG45NX7S2A106M5
00JJ
TDK Installed
C15, C16, C17,
C18, C19, C20,
C21, C22
8 0.1 µF CAP, CERM, 0.1 µF, 100
V,+/- 10%, X8L, AEC-Q200
Grade 0, 0603
0603 885012206120 Wurth
Elektronik
Installed
C23, C24, C26,
C28, C29, C30,
C31, C36, C37,
C39, C40, C41,
C42, C43, C44,
C45
16 0.1 µF CAP, CERM, 0.1 µF, 25 V,+/-
10%, X7R, 0402
0402S 885012205085 Wurth
Elektronik
Installed
C25 1 4.7 µF CAP, CERM, 4.7 uF, 10 V,
+/- 20%, X7R, 0603
0603 GRM188Z71A475ME15
D
MuRata Installed
C27 10.47
µF
CAP, CERM, 0.47 uF, 25 V,
+/- 10%, X7R, 0603
0603 885012206075 Wurth
Elektronik
Installed
C32,C33 2 20 pF CAP, CERM, 20 pF, 50 V, +/-
5%, C0G/NP0, 0402
0402 GRM1555C1H200JA01
D
MuRata Installed
C34,C35 24.7 µF CAP, CERM, 4.7 uF, 16 V,+/-
10%, X7R, 0603
0603 GRM188Z71C475KE21
D
MuRata Installed
C38 1 100 pF CAP, CERM, 100 pF, 50 V,
+/- 5%, C0G/NP0, 0402
0402 885012005061 Wurth
Elektronik
Installed
D1 1 Red LED, Red, SMD LTST-
C191_Red
LTST-C191KRKT Lite-On Installed
D2,D3,D5,D6,D
7,D9
6 Diode, Switching, 100 V,
0.15 A, SOD-123
DOS-123 1N4148W-TP Micro
Commercial
Components
Installed
D10,D11 2 1-Channel ESD Protection
Diode for USB Type-C and
Thunderbolt 3, DPY0002A
(X1SON-2)
DPY0002A TPD1E01B04DPYR Texas
Instruments
Installed
FID1, FID2,
FID3
3 Fiducial mark. There is
nothing to buy or mount.
Fiducial10-20 N/A N/A Installed
www.ti.com Hardware Design Files
SLAU905 – AUGUST 2023
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DAC81401 Evaluation Module 19
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Table 4-1. Bill of Materials for the DAC81401EVM (continued)
Designator Qty Value Description Package
Reference Part Number Manufacturer Assembly
Details
H1,H2,H3,H4 4 MACHINE SCREW PAN
PHILLIPS 4-40
NY PMS 440
0025 PH
NY PMS 440 0025 PH B&F Fastener
Supply
Installed
H5,H6,H7,H8 4 HEX STANDOFF #4-40
NYLON 1/2"
Keystone_1902
C
1902C Keystone Installed
J1,J19,J21,J22
,J24
5Header, 2.54 mm, 2×1, Gold,
TH
WURTH_6130
0211121
61300211121 Wurth
Elektronik
Installed
J2,J5,J17 3 Header, 2.54 mm, 3×1, Gold,
TH
WURTH_6130
0311121
61300311121 Wurth
Elektronik
Installed
J3,J4,J6,J7,J13
,J15
6Standard Banana Jack,
insulated, 10 A, red
571-0500 571-0500 DEM
Manufacturing
Installed
J9,J14 2 Standard Banana Jack,
insulated, 10 A, black
571-0100 571-0100 DEM
Manufacturing
Installed
J10,J18 2 Header, 100mil, 4×1, Gold,
TH
TSW-104-07-
G-S
61300411121 Wurth
Elektronik
Installed
J11,J16 2 Terminal Block, 3.5mm Pitch,
4×1, TH
TERM_BLK_E
D555-4DS
ED555/4DS On Shore
Technology Inc.
Installed
J12 1 Header, 100mil, 5×2, Tin, TH CONN_PEC05
DAAN
61301021121 Wurth
Elektronik
Installed
J20 1 Receptacle, USB 2.0, Micro
B, 5 Position, R/A, SMT
Molex_105164
0001
1051640001 Molex Installed
L1 1 600
ohm
Ferrite Bead, 600 ohm @
100 MHz, 1 A, 0603
0603S 782633601 Wurth
Elektronik
Installed
LBL1 1 Thermal Transfer Printable
Labels, 0.650" W x 0.200" H
- 10,000 per roll
Label_650x200 THT-14-423-10 Brady Installed
R1 1 200.0 200 Ohms ±1% 0.125W,
1/8W Chip Resistor 0603
(1608 Metric) Anti-Sulfur,
Moisture Resistant Thin Film
FP-
RNCP0603FT
D200R_0603-
MFG
RNCP0603FTD200R Stackpole
Electronics Inc
Installed
R2,R3,R5,R6,R
8,R21,R27
7 10.0k RES, 10.0 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402S RMCF0402FT10K0 Stackpole
Electronics Inc
Installed
R4,R10,R14,R
28,R29,R30
6 0 RES, 0, 5%, 0.1 W, 0603 0603 RC0603JR-070RL Yageo America Installed
R7 1 10.0 RES, 10.0, 0.05%, 0.1 W,
0603
0603 RNCF0603AKT10R0 Stackpole
Electronics Inc
Installed
R9,R17,R23 3 47.0k RES, 47.0 k, 1%, 0.1 W,
0603
0603 RC0603FR-0747KL Yageo Installed
R11,R15 2 1.00k RES, 1.00 k, 0.1%, 0.1 W,
0603
0603 RT0603BRB071KL Yageo America Installed
R12,R18 2 4.99k RES, 4.99 k, 0.01%, 0.1 W,
0603
0603 RNCF0603TKY4K99 Stackpole
Electronics Inc
Installed
R13,R16 2 15.0k RES, 15.0 k, 0.05%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 ERA-3ARW153V Panasonic Installed
R19,R20 2 10.0 RES, 10.0, 1%, 0.063 W,
0402
0402S RK73H1ETTP10R0F KOA Speer Installed
Hardware Design Files www.ti.com
20 DAC81401 Evaluation Module SLAU905 – AUGUST 2023
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Copyright © 2023 Texas Instruments Incorporated