Texas Instruments LMK1D1208IEVM User manual

User’s Guide
LMK1D1208IEVM User's Guide
ABSTRACT
The LMK1D1208I is a high-performance, low-additive jitter LVDS clock buffer with two universal inputs, 8 LVDS
outputs, and I2C configurability.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1208I.
Throughout this document, the acronym EVM and the phrases evaluation module and evaluation board are
synonymous with the LMK1D1208IEVM.
The LMK1D1208IEVM is equipped with 50-Ω SMA connectors and impedance-controlled, 50-Ω, microstrip
transmission lines for best performance.
Figure 1-1. LMK1D1208I Evaluation Board
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Table of Contents
1 Features...................................................................................................................................................................................3
2 General Description................................................................................................................................................................3
3 Signal Path and Control Circuitry......................................................................................................................................... 3
4 Getting Started........................................................................................................................................................................4
5 Power Supply Connection..................................................................................................................................................... 5
6 Input Clock.............................................................................................................................................................................. 6
6.1 Differential Input................................................................................................................................................................. 6
6.2 Single-Ended Input.............................................................................................................................................................7
7 Output Clock........................................................................................................................................................................... 8
8 Using I2C................................................................................................................................................................................. 9
8.1 I2C Address Selection......................................................................................................................................................11
9 EVM Board Schematic..........................................................................................................................................................12
10 Bill of Materials................................................................................................................................................................... 17
11 REACH Compliance............................................................................................................................................................21
Trademarks
All trademarks are the property of their respective owners.
Table of Contents www.ti.com
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1 Features
• Easy-to-use evaluation board to fan out low-phase noise clocks
• Supports output frequencies of up to 2 GHz
• Simple, fast device configuration and setup
• I2C programmable with TICSPRO GUI available
• Single supply input powered at either 1.8 V, 2.5 V, or 3.3 V
• Differential or single-ended input clocks accepted
• EVM supports 8 differential LVDS outputs.
2 General Description
The LMK1D1208I is an I2C-programmable clock buffer that delivers 8 differential LVDS outputs. This device has
two universal input buffers which support differential or single-ended clock inputs that can be selected through
I2C programming. The device also features on-chip bias generators that can provide LVDS common-mode
voltage for AC-coupled differential clock inputs.
The I2C capabilities of this device can be evaluated by connecting a micro-USB cable to the computer and
interfacing with the TICS Pro software.
This fully assembled and factory-tested evaluation board allows complete validation of device functionalities.
For optimum performance, the board is equipped with SMA connectors and well-controlled, 50-Ω impedance,
microstrip transmission lines.
3 Signal Path and Control Circuitry
The LMK1D1208I supports single-ended inputs up to 250 MHz and differential inputs up to 2 GHz. Each device
provides up to 8 LVDS outputs that operate at the selected input frequency.
For more information, see the LMK1D1208I I2C Configurable Low Additive Jitter LVDS Buffer data sheet
(SNAS828) for details.
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4 Getting Started
The EVM has self-explanatory labeling and offers almost the same naming convention used in the data sheets.
The bold italic text in this document follows the same spelling as the actual labeling on the EVM board. By
default, the EVM can be used with differential inputs and, after board modification, with single-ended inputs.
Figure 4-1. LMK1D1208IEVM Quick Start Guide
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5 Power Supply Connection
Connect the power supply source to the SMA connector, J8 (VDD). Test points, TP3 (VCC) and TP4 (GND),
can be used as an alternative power supply source. The decoupling capacitors and ferrite bead isolate the EVM
power from the power pins of the device.
A supply voltage of 1.71 V to 3.465 V can be used for this EVM.
Figure 5-1. Power Supply Connection Layout
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6 Input Clock
The LMK1D1208I can receive either a differential or single-ended clock as input. The default board configuration
is for an LVDS differential signal at both device inputs. The inputs can be applied through the SMAs: J1, J2
(IN0_P, IN0_N) or J3, J4 (IN1_P, IN1_N). These inputs are AC-coupled to the device. The common-mode
voltage is provided by the device on-chip bias generator (VAC_REF pins), which can be measured at TP1 and
TP2.
Figure 6-1. Input Clock Selection Layout
6.1 Differential Input
By default, the clock inputs are configured as AC-coupled LVDS inputs with VAC_REF connection.
Input Clock www.ti.com
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6.2 Single-Ended Input
Single-ended input must be configured by replacing or removing passive components on the board. Follow Table
6-1 for proper setup of a single-ended input.
Table 6-1. Single-Ended Configurations by Bias Voltage
BIAS VOLTAGE
TO INx_N (V)
INPUT TO INx_P
(V)
INPUT REMOVE
BIASING
RESISTOR
REMOVE
COMMON-MODE
RESISTOR
REPLACE WITH
0-Ω RESISTOR
REPLACE WITH
100-Ω RESISTOR
0.9 1.8 (LVCMOS) IN0_N R5
R6
R12 C3 N/A
IN0_P C4 N/A
0.9 1.8 (LVCMOS) IN1_N R7
R8
R13 C5 N/A
IN1_P C6 N/A
1.25 2.5 (LVCMOS) IN0_N R6 R12 R1
C3, C4
R14
R15
IN0_P
1.25 2.5 (LVCMOS) IN1_N R8 R13 R2
C5, C6
R16
R17
IN1_P
1.65 3.3 (LVCMOS) IN0_N R6 R12 R1
C3, C4
R14
R15
IN0_P
1.65 3.3 (LVCMOS) IN1_N R8 R13 R2
C5, C6
R16
R17
IN1_P
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7 Output Clock
The LMK1D1208I generates up to 8 LVDS outputs. Two outputs (OUT0 and OUT4) are available by default
on the EVM through the following populated SMAs: J12, J13 (OUT0_P, OUT0_N) and J14, J15 (OUT4_P,
OUT4_N).
The LVDS outputs are AC-coupled to their respective SMAs. Each output pair has the 100-Ω termination on the
board already populated.
Figure 7-1. Output Clock EVM Layout
Output Clock www.ti.com
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8 Using I2C
The user can program the LMK1D1208I through the TICSPRO software (available for download on ti.com).
This GUI allows the user to control the input enables, bank enable/mute controls, individual output enable, and
individual output amplitude.
From the TICS Pro toolbar located at the top, click Select Device → Clock Distribution with Divider →
LMK1D1208I to access the profile.
Figure 8-1. Locate the LMK1D1208I Device Profile
Using the same toolbar, click USB communications → Interface → USB2ANY to switch from DemoMode to
I2C.
Figure 8-2. Set to I2C Communication
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TI highly recommends that the user only modifies the registers available in the Main tab. Using the LMK1D1208I
beyond logic states allowed in the GUI should be avoided to ensure performance and prevent device misuse.
Figure 8-3. LMK1D1208I GUI Main Page
Using I2C www.ti.com
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8.1 I2C Address Selection
The LMK1D1208I can be configured among four different I2C addresses by setting the two-level IDX pins.
Jumpers, J9 and J6, are routed to the IDX0 and IDX1 pins and can be connected to VDD or GND. Use Table 8-1
to determine the appropriate jumper layout to select the I2C address.
Table 8-1. I2C Address Assignment
I2C ADDRESS IDX1 IDX0
0x68 GND GND
0x69 GND VDD
0x6A VDD GND
0x6B VDD VDD
Figure 8-4. I2C Address Selection Layout
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9 EVM Board Schematic
Figure 9-1 shows the printed circuit board (PCB) schematic.
LMK1D1208IRHA
NC
1
OUT7_P 2
OUT7_N 3
NC
4
SDA
5SCL
6
NC
7
IN1_P
8
IN1_N
9
VAC_REF1
10
VCC
11
IN0_P
12
IN0_N
13
VAC_REF0
14
IDX0
15
IDX1
16
NC
17
OUT0_P 18
OUT0_N 19 VCC
20
NC
21
OUT1_P 22
OUT1_N 23
OUT2_P 24
OUT2_N 25
NC
26 NC
27
OUT3_P 28
OUT3_N 29
NC
30 NC
31
OUT4_P 32
OUT4_N 33
OUT5_P 34
OUT5_N 35
NC
36 NC
37
OUT6_P 38
OUT6_N 39
VCC
40
ThermalPad 41
U1
CK0 P
CK0 N CK0 P
CK0 N
CK6 N
CK5 P
CK6 P
CK4 N
CK5 N CK5 N
CK6 N
CK5 P
CK6 P
CK4 P
CK4 N
CK4 P
CK3 N CK3 N
CK3 P CK3 P
CK2 N CK2 N
CK2 P CK2 P
CK1 N CK1 N
CK1 P CK1 P
INP1
INN1
INP1
INN1
CK7 P
CK7 N CK7 N
CK7 P
INP0
INN0
INP0
INN0
VAC_REF1/NC
VAC_REF0/NC VAC_REF1/NC
VAC_REF0/NC
SDA
SCL SDA
SCL
IDX0
IDX1
IDX0 IDX1
VCC
GND
Figure 9-1. LMK1D1208IEVM Schematic: Device Sheet
EVM Board Schematic www.ti.com
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GND
1
2 3 4 5
J1
CON-SMA-EDGE-S
GND
1
2 3 4
5
J2
CON-SMA-EDGE-S
49.9
R5
49.9
R6
VAC_REF0/NC
0
R12
GND
1uF
R1
1uF
C7
0.1µF
C3
0.1µF
C4
VCC
49.9
R14
VCC
49.9
R15
GND
1
2
3
4
5
J3
GND
1
2 3 4 5
J4
CON-SMA-EDGE-S
49.9
R7
49.9
R8
VAC_REF1/NC
0
R13
GND
1uF
R2
1uF
C8
0.1µF
C5
0.1µF
C6
VCC
49.9
R16
VCC
49.9
R17
INN0
INP1
INP0
INN1
INP0
INN0
INP1
INN1
Default: AC-coupled LVDS inputs for IN0 and IN1
VAC_REF1/NC
VAC_REF0/NC
0
R19
0
R18
PBC03SAAN
1
2
3
J5
GND
SDA_BACK
SDA1
SCL1
1.00k
R20
VCC
1.00k
R21 VCC
SCL_BACK
SDA1
SCL1
GND
10pF
50V
C9
GND
10pF
50V
C10
1.5k
R9
U2A_3V3
1.5k
R4
100nF
16V
C2
GND
10V
1uF
C1
GND 510
R3
Yellow
1 2
D1
SDA
SCL 0R10
0R11
U2AGPIO0
U2AGPIO1
TP2
TP1
PBC03SAAN
1
2
3
J6
GND
0
R22 IDX1 IDX1
PBC03SAAN
1
2
3
J9
0
R23 IDX0 IDX0
GND
VCC
VCC
CON-SMA-EDGE-S
Default: I2C connection through USB2ANY
Default: 0x6B when floating (internal 650 kΩ pullup on IDX pins)
I2C Address Configuration
IDX1 IDX0
L
H
L
L
L
H
HH
Address
0x68
0x69
0x6A
0x6B
Figure 9-2. LMK1D1208IEVM Schematic: Inputs Sheet
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GND
1
2 3 4 5
J12
CON-SMA-EDGE-S
1
2 3 4 5
J13
CON-SMA-EDGE-S
0.1µF
C13
0.1µF
C14
GND
1
2 3 4 5
J16
CON-SMA-EDGE-S
1
2 3 4 5
J17
CON-SMA-EDGE-S
0.1µF
C17
0.1µF
C18
GND
1
2 3 4 5
J20
CON-SMA-EDGE-S
1
2 3 4 5
J21
CON-SMA-EDGE-S
0.1µF
C21
0.1µF
C22
GND
1
2 3 4 5
J14
CON-SMA-EDGE-S
1
2 3 4 5
J15
CON-SMA-EDGE-S
0.1µF
C15
0.1µF
C16
GND
1
2 3 4 5
J18
CON-SMA-EDGE-S
1
2 3 4 5
J19
CON-SMA-EDGE-S
0.1µF
C19
0.1µF
C20
GND
1
2 3 4 5
J22
CON-SMA-EDGE-S
1
2 3 4 5
J23
CON-SMA-EDGE-S
0.1µF
C23
0.1µF
C24
GND
1
2 3 4 5
J24
1
2 3 4 5
J25
0.1µF
C25
0.1µF
C26
GND
1
2 3 4 5
J26
1
2 3 4 5
J7
0.1µF
C27
0.1µF
C28
CK1 P
CK1 N
CK2 P
CK4 P CK5 P CK6 P
CK2 N
CK4 N CK5 N CK6 N
CK3 P
CK7 P
CK7 N
CK3 N
0
R26
0
R24
0
R27
0
R29
0
R32
0
R30
0
R36
0
R38
0
R45
0
R47
0
R33
0
R35
0
R39
0
R41
0
R42
0
R44
100
R25
100
R31
100
R37
100
R43
100
R46
100
R40
100
R34
100
R28
GND GND GND GND
GNDGNDGNDGND
CK0 P
CK0 N
Default: All outputs terminated with 100 Ω differential
Figure 9-3. LMK1D1208IEVM Schematic: Outputs Sheet
EVM Board Schematic www.ti.com
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GND
VCC
GND
L1
GND
VDD = 1.8V / 2.5V / 3.3V @
300mA (max)
Red
21
D2
100
R48
GND
VCC
1
2
J10
1
2 3 4 5
J8
CON-SMA-EDGE-S
1µF
C29
10µF
10V
C30
10V
0.22uF
C31
10V
0.22uF
C32
10V
0.22uF
C33
10V
0.22uF
C34
10V
0.22uF
C35
10V
0.22uF
C36
10V
0.22uF
C37
TP3
TP4
Figure 9-4. LMK1D1208IEVM Schematic: Power Supply Sheet
www.ti.com EVM Board Schematic
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1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
5 6
HSDC118A_USB
6/21/2021
HSDC118A_USB.SchDoc
Sheet Title:
Size:
Mod. Date:
File:
Sheet: of
B http://www.ti.com
Contact: http://www.ti.com/support
LMK1D1208iEVMProject Title:
Designed for: Public Release
Assembly Variant: LMK1D1208ixx40PINAC
© Texas Instruments 2021
Drawn By:
Engineer:
Aaron Black
Aaron Black
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version controlSVN Rev:
HSDC118Number: Rev: A
TID #: N/A
Orderable: LMK1D1208iEVM
VBUS
D_N
D_P
0.1uF
C45
33R54
33R55
1.2Meg
R57
220pF
C46
GND
1.5k
R56
PUR
VUSB
GNDGND
GND
7.5V
D3
GND
22uF
C47 10uF
C48
LP5900SD-3.3/NOPB
VOUT 1
NC 2
GND 3
VEN
4
NC 5
VIN
6
PAD 7
U4
GND
GND
FB1
3.3V, 150mA REGULATORUSB MINI-B CONNECTOR
33k
R58
0.1uF
C49
GND
VBUS VBUS_FILT U2A_3V3
10uF
C51
1
2
3
4
S1
TPD4E004DRYR
IO1 1
IO2 2
GND
3
IO3
4
IO4
5
VCC 6
U2
220pF
C40
GND
U2AGPIO8
U2AGPIO9
U2AGPIO10
MSP430F5529IPN
P6.4/CB4/A4 1
P6.5/CB5/A5 2
P6.6/CB6/A6 3
P6.7/CB7/A7 4
P7.0/CB8/A12
5
P7.1/CB9/A13
6
P7.2/CB10/A14
7
P7.3/CB11/A15
8
P5.0/A8/VREF+/VEREF+
9
P5.1/A9/VREF-/VEREF-
10
AVCC1
11
P5.4/XIN
12
P5.5/XOUT
13
AVSS1 14
P8.0 15
P8.1 16
P8.2 17
DVCC1
18 DVSS1 19
VCORE
20
P1.0/TA0CLK/ACLK
21
P1.1/TA0.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/TA0.3
25
P1.5/TA0.4
26
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
P2.0/TA1.1 29
P2.1/TA1.2 30
P2.2/TA2CLK/SMCLK 31
P2.3/TA2.0 32
P2.4/TA2.1 33
P2.5/TA2.2 34
P2.6/RTCCLK/DMAE0 35
P2.7/UCB0STE/UCA0CLK 36
P3.0/UCB0SIMO/UCB0SDA
37
P3.1/UCB0SOMI/UCB0SCL
38
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
P3.4/UCA0RXD/UCA0SOMI
41
P3.5/TB0.5
42
P3.6/TB0.6
43
P3.7/TB0OUTH/SVMOUT
44
P4.0/PM_UCB1STE/PM_UCA1CLK 45
P4.1/PM_UCB1SIMO/PM_UCB1SDA 46
P4.2/PM_UCB1SOMI/PM_UCB1SCL 47
P4.3/PM_UCB1CLK/PM_UCA1STE 48
DVSS2 49 DVCC2
50
P4.4/PM_UCA1TXD/PM_UCA1SIMO 51
P4.5/PM_UCA1RXD/PM_UCA1SOMI 52
P4.6/PM_NONE 53
P4.7/PM_NONE 54
P5.6/TB0.0
55
P5.7/TB0.1
56
P7.4/TB0.2
57
P7.5/TB0.3
58
P7.6/TB0.4
59
P7.7/TB0CLK/MCLK
60
VSSU 61
PU.0/DP 62
PUR 63
PU.1/DM 64
VBUS
65
VUSB
66
V18
67
AVSS2 68
P5.2/XT2IN
69
P5.3/XT2OUT
70
TEST/SBWTCK 71
PJ.0/TDO 72
PJ.1/TDI/TCLK 73
PJ.2/TMS 74
PJ.3/TCK 75
RST/NMI/SBWTDIO 76
P6.0/CB0/A0 77
P6.1/CB1/A1 78
P6.2/CB2/A2 79
P6.3/CB3/A3 80
U3
0.1uF
C44
0.1uF
C43
0.1uF
C41
GND GND GND
GND
PUR
0.47uF
C42
VBUS
VUSB
GND
U2AGPIO7
U2A_I2CPU
V18
EXT5V_EN
EXT5V_FAULT
EXT3.3V_EN
EXT3.3V_FAULT
2200pF
C50
GND
33k
R68
U2A_3V3
D_N
D_P
12
Y1
30pF
C39
30pF
C38
GND
0
R50
U2AGPIO12
0R51
1.0kR53
0 R59
VCORE
0 R62
0 R63
0 R64
0 R65
0 R66
0 R67
MSP430 MCU -- "USB2ANY" (U2A) CONTROLLER
U2AADC1
U2AADC0
0.1uF
C12
510
R70
510
R71
0.1uF
C11
U2A_3V3
U2AGPIO1
U2AGPIO2
U2AGPIO0
U2AGPIO4
U2AGPIO3
U2AGPIO5
U2AGPIO6
U2AGPIO11 1.0kR52
0 R60
0 R61
1
2 3
Q1
GND
U2A_3V3
510
R69
Green
12
D4
U2A_SDABRD
U2A_SCLBRD
GND
33k
R49
U2AGPIO1
U2AGPIO0
10118194-0001LF
VBUS 1
D- 2
D+ 3
ID 4
GND 5
67 8
11 10
9
J11 TP5
Figure 9-5. LMK1D1208IEVM Schematic: USB Sheet
EVM Board Schematic www.ti.com
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10 Bill of Materials
Table 10-1. Bill of Materials
Quantity Value Designator Description Package Reference Part Number Manufacturer
1 1uF C1 CAP, CERM, 1 uF, 10 V,
+/- 10%, X5R, 0603
0603 C0603C105K8PACTU Kemet
8 0.1uF C2, C11, C12, C41, C43,
C44, C45, C49
CAP, CERM, 0.1 uF, 16 V,
+/- 5%, X7R, 0603
0603 C0603C104J4RACTU Kemet
20 0.1uF C3, C4, C5, C6, C13,
C14, C15, C16, C17,
C18, C19, C20, C21,
C22, C23, C24, C25,
C26, C27, C28
CAP, CERM, 0.1 µF, 10
V,+/- 10%, X7R, AEC-
Q200 Grade 1, 0402
0402 C0402C104K8RACAUTO Kemet
2 10pF C9, C10 CAP, CERM, 10 pF, 50 V,
+/- 5%, C0G/NP0, 0603
0603 C0603C100J5GACTU Kemet
1 1uF C29 CAP, CERM, 1 µF, 10
V,+/- 5%, X7R, AEC-
Q200 Grade 1, 0603
0603 C0603X105J8RAC7867 Kemet
1 10uF C30 CAP, CERM, 10 µF,
10 V,+/- 5%, X7R, AEC-
Q200 Grade 1, 0805
0805 C0805C106J8RACAUTO Kemet
7 0.22uF C31, C32, C33, C34,
C35, C36, C37
CAP, CERM, 0.22 uF, 10
V, +/- 10%, X7R, 0402
0402 GRM155R71A224KE01D MuRata
2 30pF C38, C39 CAP, CERM, 30 pF, 100
V, +/- 5%, C0G/NP0,
0603
0603 GRM1885C2A300JA01D MuRata
2 220pF C40, C46 CAP, CERM, 220 pF,
50 V, +/- 1%, C0G/NP0,
0603
0603 06035A221FAT2A AVX
1 0.47uF C42 CAP, CERM, 0.47 uF, 10
V, +/- 10%, X7R, 0603
0603 GRM188R71A474KA61D MuRata
1 22uF C47 CAP, CERM, 22 uF, 10 V,
+/- 20%, X5R, 0805
0805 LMK212BJ226MG-T Taiyo Yuden
2 10uF C48, C51 CAP, CERM, 10 uF, 10 V,
+/- 20%, X5R, 0603
0603 C1608X5R1A106M080A
C
TDK
1 2200pF C50 CAP, CERM, 2200 pF, 50
V, +/- 10%, X7R, 0603
0603 C0603C222K5RACTU Kemet
1 Yellow D1 LED, Yellow , SMD 0805 LED LTST-C170KSKT Lite-On
1 D2 SMD RED LED SMD_LED BOS-3528-2RCQ BYD
1 7.5V D3 Diode, Zener, 7.5 V, 550
mW, SMB
SMB 1SMB5922BT3G ON Semiconductor
1 Green D4 LED, Green, SMD 1.6x0.8x0.8mm LTST-C190GKT Lite-On
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SNAU270 – FEBRUARY 2022
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LMK1D1208IEVM User's Guide 17
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Table 10-1. Bill of Materials (continued)
Quantity Value Designator Description Package Reference Part Number Manufacturer
1 60 ohm FB1 Ferrite Bead, 60 ohm @
100 MHz, 3.5 A, 0603
0603 MPZ1608S600ATAH0 TDK
4 H1, H2, H3, H4 Machine Screw, Round,
#4-40 x 1/4, Nylon,
Philips panhead
Screw NY PMS 440 0025 PH B&F Fastener Supply
4 H5, H6, H7, H8 Standoff, Hex, 0.5"L
#4-40 Nylon
Standoff 1902C Keystone
9 J1, J2, J3, J4, J8, J12,
J13, J14, J15
CONN SMA JACK STR
EDGE MNT
CONN_JACK CON-SMA-EDGE-S RF Solutions Ltd.
2 J6, J9 Header, 100mil, 3x1,
Gold, TH
PBC03SAAN PBC03SAAN Sullins Connector
Solutions
1 J10 Header, 100mil, 2x1,
Gold, TH
Header, 2x1, 100mil 5-146261-1 TE Connectivity
1 J11 Receptacle, USB 2.0,
Micro-USB Type B, R/A,
SMT
USB-micro B USB 2.0,
0.65mm, 5 Pos, R/A,
SMT
10118194-0001LF FCI
1 50 ohm L1 Ferrite Bead, 50 ohm @
100 MHz, 12 A, 1206
1206 BLM31SN500SZ1L MuRata
1 50V Q1 MOSFET, N-CH, 50 V,
0.22 A, SOT-23
SOT-23 BSS138 Fairchild Semiconductor
2 1uF R1, R2 CAP, CERM, 1 uF, 6.3
V,+/- 10%, X7R, 0402
0402 GRM155R70J105KA12D MuRata
1 510 R3 RES, 510, 5%, 0.1 W,
0603
0603 RC0603JR-07510RL Yageo
2 1.5k R4, R9 RES, 1.5 k, 5%, 0.1 W,
0603
0603 RC0603JR-071K5L Yageo
4 49.9 R5, R6, R7, R8 RES, 49.9, 1%, 0.1 W,
AEC-Q200 Grade 0, 0402
0402 ERJ-2RKF49R9X Panasonic
4 0 R10, R11, R12, R13 RES, 0, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402 CRCW04020000Z0ED Vishay-Dale
2 0 R22, R23 RES, 0, 5%, 0.1 W, 0603 0603 RC0603JR-070RL Yageo
16 0 R24, R26, R27, R29,
R30, R32, R33, R35,
R36, R38, R39, R41,
R42, R44, R45, R47
RES, 0, 5%, 0.1 W, AEC-
Q200 Grade 0, 0402
0402 ERJ-2GE0R00X Panasonic
8 100 R25, R28, R31, R34,
R37, R40, R43, R46
RES, 100, 0.1%, 0.1 W,
AEC-Q200 Grade 0, 0402
0402 MCS0402MD1000BE100 Vishay/Beyschlag
1 100 R48 RES, 100, 1%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW0603100RFKEA Vishay-Dale
2 33k R49, R58 RES, 33 k, 5%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW060333K0JNEA Vishay-Dale
EVM Board Schematic www.ti.com
18 LMK1D1208IEVM User's Guide SNAU270 – FEBRUARY 2022
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Table 10-1. Bill of Materials (continued)
Quantity Value Designator Description Package Reference Part Number Manufacturer
7 0 R50, R51, R59, R60,
R61, R62, R63
RES, 0, 5%, 0.1 W, AEC-
Q200 Grade 0, 0603
0603 CRCW06030000Z0EA Vishay-Dale
2 1.0k R52, R53 RES, 1.0 k, 5%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW06031K00JNEA Vishay-Dale
2 33 R54, R55 RES, 33, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402 CRCW040233R0JNED Vishay-Dale
1 1.5k R56 RES, 1.5 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402 CRCW04021K50JNED Vishay-Dale
1 1.2Meg R57 RES, 1.2 M, 5%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW06031M20JNEA Vishay-Dale
3 510 R69, R70, R71 RES, 510, 5%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW0603510RJNEA Vishay-Dale
1 S1 Switch, Tactile, SPST-NO,
0.05A, 12V, SMT
SW, SPST 6x6 mm FSM4JSMA TE Connectivity
2 1x2 SH1, SH2 Shunt, 100mil, Gold
plated, Black
Shunt SNT-100-BK-G Samtec
5 TP1, TP2, TP3, TP4, TP5 Test Point, Miniature,
SMT
Test Point, Miniature,
SMT
5019 Keystone
1 U1 LMK1D1208IRHA VQFN40 LMK1D1208IRHA Texas Instruments
1 U2 4-Channel ESD
Protection Array for High-
Speed Data Interfaces,
DRY0006A (USON-6)
DRY0006A TPD4E004DRYR Texas Instruments
1 U3 25 MHz Mixed Signal
Microcontroller with 128
KB Flash, 8192 B SRAM
and 63 GPIOs, -40 to 85
degC, 80-pin QFP (PN),
Green (RoHS & no Sb/Br)
PN0080A MSP430F5529IPN Texas Instruments
1 U4 150-mA Ultra-Low Noise
LDO for RF and
Analog Circuits Requires
No Bypass Capacitor,
NGF0006A (WSON-6)
NGF0006A LP5900SD-3.3/NOPB Texas Instruments
1 Y1 Crystal, 24.000 MHz,
20pF, SMD
Crystal, 11.4x4.3x3.8mm ECS-240-20-5PX-TR ECS Inc.
0 1uF C7, C8 CAP, CERM, 1 uF, 6.3 V,
+/- 20%, X7R, 0402
0402 GRM155R70J105MA12D MuRata
0 FID1, FID2, FID3, FID4,
FID5, FID6
Fiducial mark. There is
nothing to buy or mount.
N/A N/A N/A
0 J5 Header, 100mil, 3x1,
Gold, TH
PBC03SAAN PBC03SAAN Sullins Connector
Solutions
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LMK1D1208IEVM User's Guide 19
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Table 10-1. Bill of Materials (continued)
Quantity Value Designator Description Package Reference Part Number Manufacturer
0 J7, J16, J17, J18, J19,
J20, J21, J22, J23, J24,
J25, J26
CONN SMA JACK STR
EDGE MNT
CONN_JACK CON-SMA-EDGE-S RF Solutions Ltd.
0 49.9 R14, R15, R16, R17 RES, 49.9, 1%, 0.1 W,
AEC-Q200 Grade 0, 0402
0402 ERJ-2RKF49R9X Panasonic
0 0 R18, R19 RES, 0, 5%, 0.1 W, 0603 0603 RC0603JR-070RL Yageo
0 1.00k R20, R21 RES, 1.00 k, 1%, 0.1 W,
0603
0603 ERJ-3EKF1001V Panasonic
0 0 R64, R65, R66, R67 RES, 0, 5%, 0.1 W, AEC-
Q200 Grade 0, 0603
0603 CRCW06030000Z0EA Vishay-Dale
0 33k R68 RES, 33 k, 5%, 0.1 W,
AEC-Q200 Grade 0, 0603
0603 CRCW060333K0JNEA Vishay-Dale
EVM Board Schematic www.ti.com
20 LMK1D1208IEVM User's Guide SNAU270 – FEBRUARY 2022
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Copyright © 2022 Texas Instruments Incorporated