Texas LMK04906B User manual

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LMK04906 Family
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04906 Evaluation Board Operating Instructions
Texas Instruments
June 2012

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Table of Contents
TABLE OF CONTENTS.............................................................................................................................................. 2
GENERAL DESCRIPTION.......................................................................................................................................... 4
EVALUATION BOARD KIT CONTENTS ..................................................................................................................................4
AVAILABLE LMK04906 EVALUATION BOARDS....................................................................................................................4
AVAILABLE LMK04906 FAMILY DEVICES ...........................................................................................................................4
QUICK START ......................................................................................................................................................... 5
DEFAULT CODELOADER MODES FOR EVALUATION BOARDS....................................................................................................6
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04906B ........................................................................... 7
1. START CODELOADER 4APPLICATION..............................................................................................................................7
2. SELECT DEVICE ..........................................................................................................................................................7
3. PROGRAM/LOAD DEVICE.............................................................................................................................................8
4. RESTORING A DEFAULT MODE......................................................................................................................................8
5. VISUAL CONFIRMATION OF FREQUENCY LOCK..................................................................................................................9
6. ENABLE CLOCK OUTPUTS.............................................................................................................................................9
PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11
PLL 1LOOP FILTER ......................................................................................................................................................11
122.88 MHz VCXO PLL........................................................................................................................................11
PLL2 LOOP FILTER .......................................................................................................................................................12
EVALUATION BOARD INPUTS AND OUTPUTS....................................................................................................... 13
RECOMMENDED TEST EQUIPMENT...................................................................................................................... 20
PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 21
OVERVIEW..................................................................................................................................................................21
DUAL LOOP 0-DELAY MODE EXAMPLES ...........................................................................................................................21
Programming Steps............................................................................................................................................21
Details ................................................................................................................................................................21
SINGLE LOOP 0-DELAY MODE EXAMPLES .........................................................................................................................23
Programming Steps............................................................................................................................................23
Details ................................................................................................................................................................23
APPENDIX A: CODELOADER USAGE...................................................................................................................... 25
PORT SETUP TAB .........................................................................................................................................................25
CLOCK OUTPUTS TAB ...................................................................................................................................................26
PLL1 TAB...................................................................................................................................................................28
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency.......................................................................29
PLL2 TAB...................................................................................................................................................................30
BITS/PINS TAB ............................................................................................................................................................31
REGISTERS TAB............................................................................................................................................................36
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS................................................................................. 37
PLL1.........................................................................................................................................................................37
122.88 MHz VCXO Phase Noise..........................................................................................................................37
Clock Output Measurement Technique..............................................................................................................38
Buffered OSCout Phase Noise.............................................................................................................................38
CLOCK OUTPUTS (CLKOUT)...........................................................................................................................................39

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LMK04906B CLKout Phase Noise........................................................................................................................39
LMK04906B OSCout Phase Noise .......................................................................................................................41
APPENDIX C: SCHEMATICS ................................................................................................................................... 42
POWER SUPPLIES.........................................................................................................................................................42
LMK04906B DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS .........................................................................................43
REFERENCE INPUTS (CLKIN0, CLKIN1&CLKIN2), EXTERNAL VCXO (OSCIN)&VCO CIRCUITS................................................44
CLOCK OUTPUTS (OSCOUT0, CLKOUT0TO CLKOUT5) ......................................................................................................45
UWIRE HEADER,LOGIC I/O PORTS AND STATUS LEDS........................................................................................................46
APPENDIX D: BILL OF MATERIALS ........................................................................................................................ 47
APPENDIX E: PCB LAYERS STACKUP..................................................................................................................... 52
APPENDIX F: PCB LAYOUT.................................................................................................................................... 53
LAYER #1 –TOP ..........................................................................................................................................................53
LAYER #2 –RF GROUND PLANE (INVERTED).....................................................................................................................54
LAYER #3 –VCC PLANES ...............................................................................................................................................55
LAYER #4 –GROUND PLANE (INVERTED)..........................................................................................................................56
LAYER #5–VCC PLANES 2............................................................................................................................................57
LAYER #6 –BOTTOM....................................................................................................................................................58
LAYERS #1 AND 6–TOP AND BOTTOM (COMPOSITE).........................................................................................................59
APPENDIX G: PROPERLY CONFIGURING LPT PORT ............................................................................................... 60
LPT DRIVER LOADING...................................................................................................................................................60
CORRECT LPT PORT/ADDRESS .......................................................................................................................................60
CORRECT LPT MODE....................................................................................................................................................61
APPENDIX H: TROUBLESHOOTING INFORMATION ............................................................................................... 62
1) CONFIRM COMMUNICATIONS ...............................................................................................................................62
2) CONFIRM PLL1 OPERATION/LOCKING ....................................................................................................................62
3) CONFIRM PLL2 OPERATION/LOCKING ....................................................................................................................63

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General Description
The LMK04906 Evaluation Board simplifies evaluation of the LMK04906B Low-Noise Clock
Jitter Cleaner with Dual Loop PLLs. Texas Instrument‟s CodeLoader software can be used to
program the internal registers of the LMK04906B device through the MICROWIRETM interface.
The CodeLoader software will run on a Windows 2000 or Windows XP PC and can be
downloaded from http://www.ti.com/codeloader.
Evaluation Board Kit Contents
The evaluation board kit includes:
(1) LMK04906 Evaluation Board from Table 1
(1) CodeLoader uWire cable (LPT uWire)
Available LMK04906 Evaluation Boards
The LMK04906 Evaluation Board supports any of the four devices offered in the LMK04906
Family. All evaluation boards use the same PCB layout and bill-of-materials, except for the
corresponding LMK04906B device affixed to the board. A commercial-quality VCXO is also
mounted to the board to provide a known reference point for evaluating device performance and
functionality.
Table 1: Available Evaluation Board Configurations
Evaluation Board ID
Device
PLL1 VCXO
LMK04906BEVAL
LMK04906B
122.88 MHz Crystek VCXO
Model CVHD-950-122.880
Available LMK04906 FamilyDevices
Table 2: LMK04906B Devices
Device
Reference
Inputs
Buffered/
Divided
OSCin
Outputs
Programmable
LVDS/LVPECL/
LVCMOS
Outputs
VCO Frequency
LMK04906B
3
1
6
2370 to 2600 MHz

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Quick Start
Full evaluation board instructions are downloadable from the LMK04906B device product folder
at www.ti.com.
1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard
LP3878-ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device.
2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88
MHz for default. The reference frequency depends on the device programming.
3. Connect the uWire header to a PC parallel port using the CodeLoader cable. A USB
interface is also available (search for “USB2UWIRE-IFACE” at www.ti.com).
4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at
least once to load all registers. Alternatively click menu “Keyboard Controls” “Load
Device”. CodeLoader can be downloaded from www.ti.com/tool/codeloader/.
5. Measurements may be made on an active output clock port via its SMA connector.
CLKout0
CLKout0*
Laptop or PC
Parallel Port
Connector
5.0 V
(LDO)
1
3
4Program with CodeLoader
Be sure to press ‘Ctrl - L’
CLKin1
Reference clock from
signal generator or other
external source.
122.88 MHz
(Default)
2
Power
Reference
LMK04906
uWire
header
CLKout1
CLKout1*
CLKout2*
CLKout2
CLKout3*
CLKout3
CLKout4
CLKout4*
CLKout5*
CLKout5
OSCout0
OSCout0*
CLKin0
CLKin0*
5.0 V
3.3 V
Factory default is LDO is used.
Customer may reconfigure to
power LMK directly.
OSCin
OSCin*
CLKin2
CLKin2*
Parallel Port Ribbon
Cable
Figure 1: Quick Start Diagram

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Default CodeLoader Modes for Evaluation Boards
CodeLoader saves the state of the selected LMK04906B device when exiting the software. To
ensure a common starting point, the following modes listed in Table 3 may be restored by
clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the
case of the LMK04906B device. Similar default modes are available for each LMK04906B
device in CodeLoader. Choose a mode with CLKin0 or CLKin2 for differential clock signal or
CLKin1 for a single ended signal.
Figure 2: Selecting a Default Mode for the LMK04906 Device
After restoring a default mode, press Ctrl+L to program the device. The default modes also
disable certain outputs, so make sure to enable the output under test to make measurements.
Table 3: Default CodeLoader Modes for LMK04906
Default CodeLoader Mode
Device Mode
CLKin
Frequency
OSCin
Frequency
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO
122.88 MHz
122.88 MHz
122.88 MHz CLKin1, Dual Loop 0-
delay, 122.88 MHz VCXO
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
122.88 MHz
122.88 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
122.88 MHz
20.48 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO
122.88 MHz
122.88 MHz
122.88 MHz CLKin1, Dual Loop 0-
delay, 122.88 MHz VCXO
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
122.88 MHz
122.88 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
122.88 MHz
20.48 MHz
The next section outlines step-by-step procedures for using the evaluation board with the
LMK04906B. For boards with another part number, make sure to select the corresponding part
number under the “Device” menu.

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Example: Using CodeLoader to Program the LMK04906B
The purpose of this section is to walk the user through using CodeLoader 4 to make some
measurements with the LMK04906B device as an example. For more information on
CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located
at http://www.ti.com/tool/codeloader.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start” “Programs” “CodeLoader 4” “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” “Clock
Conditioners” “LMK04906B”
Once started CodeLoader 4 will load the last
used device. To load a new device click
“Select Device” from the menu bar, then
select the subgroup and finally device to
load. For this example, the LMK04906B is
chosen. Selecting the device does cause the
device to be programmed.
Figure 3 –Selecting the LMK04906B device

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3. Program/Load Device
Assuming the Port Setup settings are correct,
press the “Ctrl+L” shortcut or click “Keyboard
Controls” “Load Device” from the menu to
program the device to the current state of the
newly loaded LMK04906 file.
Once the device has been initially loaded,
CodeLoader will automatically program changed
registers so it is not necessary to re-load the device upon subsequent changes in the device
configuration. It is possible to disable this functionality by ensuring there is no checkmark by
the “Options” “AutoReload with Changes.”
Because a default mode will be restored in the next step, this step isn‟t really needed but included
to emphasize the importance of pressing “Ctrl+L”to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on Port Setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode” “LMK04906B, 122.88 MHz VCXO, 122.88 MHz CLKin1”; then press Ctrl+L.
Figure 5: Setting the Default mode for LMK04906
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. Again, remember to press Ctrl+L as the first step after loading a default
mode.
Figure 4 –Loading the Device

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5. Visual Confirmation of FrequencyLock
After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2
are locked to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD
and LD_TYPE = Active High, which are the default settings.
6. Enable Clock Outputs
While the LMK04906B offers programmable clock output buffer formats, the evaluation board
is shipped with preconfigured output terminations to match the default buffer type for each
output. Refer to the CLKout port description in the Evaluation Board Inputs and Outputs section.
To measure phase noise at one of the clock outputs, for example, CLKout0:
1. Click on the Clock Outputs tab,
2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,
3. Set the following settings as needed:
a. Digital Delay value
b. Clock Divider value
c. Analog Delay select and Analog Delay value (if not “Bypassed”)
d. Clock Output type.
4. Depending on the configured output type, the clock output SMAs can be interfaced to a
test instrument with a single-ended 50-ohm input as follows.
a. For LVDS:
i. A balun (like ADT2-1T) is recommended for differential-to-single-ended
conversion.
b. For LVPECL:
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-ohm load and
the other side can be run single-ended to the instrument.
c. For LVCMOS:
i. There are two single-ended outputs,
CLKoutX and CLKoutX*, and each
output can be set to Normal, Inverted, or
Off. There are nine (9) combinations of
LVCMOS modes in the Clock Output list.
ii. One side of the LVCMOS signal can be
terminated with a 50-ohm load and the
other side can be run single-ended to the
instrument.
iii. A balun may also be used. Ensure
CLKoutX and CLKoutX* states are
complementary to each other, i.e.:
Figure 7: Setting LVCMOS modes
Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0

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Norm/Inv or Inv/Norm.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
TI‟s Clock Design Tool can be used to calculate divider values to achieve desired clock output
frequencies. See: http://www.ti.com/tool/codeloader.