Toshiba TC32306FTG User manual

TC32306FTG
2015-10-01
1
TOSHIBA CMOS Integrated Circuit Silicon Monolithic
TC32306FTG
Single-Chip RF Transceiver for Low-Power Systems
1. General Description
The TC32306FTG is a single-chip RF transceiver, which
provides many of the functions required for UHF-band
transceiver applications. It has the most features transmitting
and receiving the signal.
Furthermore, by digital processing, it can reduce significantly the
number of external components and allow fine adjustments.
Various type of applications are supported by this chip as
configuring various settings such as supply voltage, frequency,
modulation and detection.
2. Applications
Remote keyless entry (remote door lock / unlock of equipment),
automotive equipment applications such as tire pressure monitoring system, and remote controller, etc
3. Features
•Integrates LNA, Mixer, IF Filter, IF AMP, RSSI, Signal Detector, Bit Rate Filter, Data Comparator, PLL, VCO
and PA into a single IC.
•Operating voltage range: 2.0 to 3.3 V (For 3V Use), 2.4V to 5.5V (For 5V Use)
•Current consumption: TX 12 mA at +10dBm output level / RX 9.7 mA / Battery Saving 0μA (typ.)
•Use for four RF Band: 315, 434, 868 / 915 MHz
•Supported modulation: ASK / FSK
•Single conversion system
•Two IF Filter bandwidth: wide 320kHz(typ.) at IF = 230kHz / middle 270kHz(typ.) at IF = 280kHz
•Signal Detections: RSSI detection, Noise detection (Only for FSK), Preamble detection
•Receiver sensitivity: under -116dBm (At IF BW = 320kHz, data rate = 600Hz, frequency deviation = +/-40kHz)
•Transmitter power: +10dBm (typ. at setting maximum output)
•Serial control (4 wire SPI) / EEPROM control
•Data Comparator Quick Charge / AutoOff Control / Antenna Switch Control
QFN36-P-0606-0.50
Weight: 0.08 g (typ.)

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4. Block Diagram
19202122242526
27 23
9876432 5
36
35
34
33
32
31
30
29
28
16
17
18
13
14
15
10
11
12
IF Filter
Detector
LPF
RSSIADC
LPF
BRF
Data
COMP
VCOPLL
XOSC
Monitor
SPI
DATA_IO
DET_TMONI1
COM_VDD
MOSI
MISO
CLK
CS
IO_GND
DET_TMONI3 DET_TMONI2 DET_TMONI4
ENB
RSSI_OUT
3V/5V
RX_SW
RF_DEC
RF_IN
A_VDD_3V
RF_OUT
A_VDD_5V
A_REG
A_GND
IF_REF
PA_GND1
PA_OUT
PA_GND2
TX_SW RESET MODE2 MODE1 TEST PLL_REG PLL_GND X_IN X_OUT
D_REG Reference clock
IF AMP
PA
MIX
FSK
ASK
LNA
Limiter
1
RX
TX
Divider
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
Fig 4-1 Block Diagram

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5. Pin Description
5.1 Equivalent Circuit and Function
Table 5-1 Pin Description
- All the values (resistance, capacity, etc.) shown in the internal equivalent circuit diagram are typical values.
- The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purpose.
Pin No. Pin Name I/O Description Internal Equivalent Circuit
1 DET_TMONI2 Digital
Output
Monitor 2
Monitoring internal signals (digital), use
for system control
At no use, open this pin.
1
Control
DET_TMONI2
COM_VDD COM_VDD
2 DET_TMONI3 Analog
Output
Monitor 3
Monitoring internal signals (Converted to
analog / in User Test )
At no use, open this pin.
Notice:
In User Test, Supply at least 3 V to
COM_VDD pin to monitor the signal.
Lower voltage supply causes an incorrect
monitoring.
2
DET_TMONI3
COM_VDD
3 ENB Digital
Input
Enable Pin
Select to enable (In SPI Mode)
Address Setting (In EEPROM Mode)
Set a start address to read memory data.
Notice:
Do not supply higher voltage than the
level of COM_VDD. (For example, in the
case of too low / no power supply.) That
causes overcurrent at this pin, as the
ESD protection elements insertion
between the pin and the voltage source.
3
ENB
COM_VDD
4 DET_TMONI4 Analog
Output
Monitor 4
Monitoring internal signals (Converted to
analog / in User Test)
At no use, open this pin.
Notice:
In User Test, Supply at least 3 V to
COM_VDD pin to monitor the signal.
Lower voltage supply causes an incorrect
monitoring.
DET_TMONI4
4
COM_VDD
5 3V/5V Digital
Input
Supply Voltage Selector
Select supply
voltage. Connect power
supply for 5V use. / Ground for 3V use.
Notice:
Do not supply higher voltage than the
level of COM_VDD. (For example, in the
case of too low / no power supply.) That
causes overcurrent at this pin, as the
ESD protection
elements insertion
between the pin and the voltage source.
5
3V/5V
COM_VDD

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
6 RSSI_OUT Analog
Output
RSSI Output
Output RSSI (= Received Signal Strength
Indication) voltage. Connect ground via a
capacitor. This IC
has another RSSI signal
for digital processing.
At no use, connect ground via a capacitor.
6
RSSI_OUT
A_VDD_3V A_VDD_3V
50kΩ
7 RX_SW
Digital
Output
Antenna Switch Control for RX (In SPI
Mode)
At no use, open this pin.
7
RX_SW
A_VDD_5V A_VDD_5V
20kΩ
100Ω
1kΩ
Digital
Input
Address Setting (In EEPROM Mode)
Set a start address to read memory data.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the ESD
protection elements insertion between the
pin and the voltage source.
8 RF_DEC -
RF Decoupling Pin
Connect a decoupling capacitor.
At no use, open this pin.
9
RF_DEC
A_REG A_VDD_3V
6kΩ
8
RF_IN
A_REG
1kΩ
5pF
9 RF_IN Analog
Input
RF Input Pin
Do not connect DC voltage except ground
to RF_IN pin.
At no use, open this pin.

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
10 A_VDD_5V -
Analog 5V Supply
Supply to mainly analog block.
- For 5V use, supply 5V (typ.).
- For 3V use, connect A_VDD_3V pin and
supply 3V (typ.).
-
11 RF_OUT Analog
Output
RF Output pin
RF signal output from LNA block,
Open drain output. Connect A_VDD_3V
pin via a matching circuit.
At no use, open this pin.
RF_OUT
11
12 A_VDD_3V -
Analog 3V Supply
- For 3V use, supply 3V (typ.).
- For 5V use, voltage regulator output.
Connect a bypass capacitor.
Do not apply current or voltage on this pin
from outside. And do not supply to
external circuits except PA_OUT and
RF_OUT pin.
-
13 A_REG Analog
Output
Regulator Output for Analog Block
Supply to mainly analog block. Connect a
bypass capacitor.
Do not apply current or voltage on this pin
from outside. And do not supply to
external circuits.
A_REG
A_VDD_5V A_VDD_5V
150kΩ
100pF
13
Vref
＋
－
14 A_GND - Ground (Analog) -
15 IF_REF -
IF Reference
Connect ground via a capacitor.
At no use, open this pin.
IF_REF
A_VDD_3V
105kΩ
15
＋
－
100kΩ
16 PA_GND1 - Power Amplifier Ground 1
At no use of PA, connect ground. -

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
17 PA_OUT
Analog
Output
Power Amplifier Output Stage
Open drain output. Connect A_VDD_3V
pin via a matching circuit.
At no use, open this pin.
PA_OUT
17
18 PA_GND2 - Power Amplifier Ground 2
At no use of PA, connect ground. -
19 TX_SW
Digital
Output
Antenna Switch Control for TX (In SPI
Mode)
At no use, open this pin.
TX_SW
A_VDD_5V A_VDD_5V
20kΩ
100Ω
19
1kΩ
Digital
Input
Address Setting (In EEPROM Mode)
Set a start address to read memory data.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the ESD
protection elements insertion between the
pin and the voltage source.
20 RESET Digital
Input
Reset
Initialize TC32306FTG.
RESET
20
21 MODE2 Digital
Input
Mode Control
Select SPI Mode, SPI User Test Mode,
EEPROM Mode, EEPROM User Test
Mode.
MODE2
21
22 MODE1 Digital
Input
Mode Control
Select SPI Mode, SPI User Test Mode,
EEPROM Mode, EEPROM User Test
Mode.
MODE1
22
40kΩ
23 TEST Digital
Input
TEST
Only use for Toshiba test.
Connect ground.
TEST
23
40kΩ

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
24 PLL_REG
Analog
Output
Regulator Output for PLL
Supply to mainly PLL block. Connect a
bypass capacitor.
Do not supply voltage, and do not supply
to an external circuit.
PLL_REG
COM_VDD
150kΩ
100pF
Vref
＋
－
24
COM_VDD
25 PLL_GND - Ground(Digital) -
26 X_IN
Analog
Input
Reference Clock Input
Connect crystal oscillator or external
signal generator.
Do not apply a DC bias voltage.
X_IN
PLL_REG
300kΩ
X_OUT
PLL_REG
26
27
27 X_OUT
Analog
Output
Reference Clock Output
Open this pin except a crystal oscillator
use.
Do not apply current or voltage on this pin
from outside. And do not supply the clock
signal to external circuits.
28 D_REG
Analog
Output
Regulator Output for Digital Block
Supply to mainly digital block. Connect a
bypass capacitor.
Do not apply current or voltage on this pin
from outside. And do not supply to
external circuits.
D_REG
150kΩ
100pF
Vref
＋
－
28
COM_VDD COM_VDD

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
29 CS
Digital
Input
Chip Select Input
In SPI Mode / SPI User Test Mode /
EEPROM User Test Mode.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the
ESD
protection
elements insertion between the
pin and the voltage source.
CS
Control
COM_VDD
COM_VDD
29
Control
Digital
Output
Chip Select Output
In EEPROM Mode.
30 CLK
Digital
Input
SPI Clock Input
In SPI Mode / SPI User Test Mode /
EEPROM User Test Mode.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the
ESD
protection
elements insertion between the
pin and the voltage source.
CLK
Control
COM_VDD
COM_VDD
30
Control
Digital
Output
SPI Clock Output
In EEPROM Mode.
31 MOSI
Digital
Input
Serial Data Input
In SPI Mode / SPI User Test Mode /
EEPROM User Test Mode.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the
ESD
protection
elements insertion between the
pin and the voltage source.
MOSI
Control
COM_VDD
COM_VDD
31
Control
Digital
Output
Serial Data Output
In EEPROM Mode.

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Pin No. Pin Name I/O Description Internal Equivalent Circuit
32 MISO
Digital
Output
Serial Data Output
In SPI Mode / SPI User Test Mode /
EEPROM User Test Mode.
MISO
Control
COM_VDD
COM_VDD
32
Control
Digital
Input
Serial Data Input
In EEPROM Mode.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low / no power supply.) That causes
overcurrent at this pin, as the ESD
protection elements insertion between the
pin and the voltage source.
33 COM_VDD - Common Voltage Supply Use for 3V and 5V.
Supply to mainly control block. -
34 DET_TMONI1 Digital
Output
Monitor 1
Monitoring internal signals (Digital), use
for system control.
At no use, open this pin.
Control
DET_TMONI1
COM_VDD COM_VDD
34
35 DATA_IO
Digital
Output
Data Output
Demodulated signal output at
RF-Receiving. Behavior of this pin is
different for each state of TC32306FTG
reset.
See Table 5-2.
Notice:
Output resistance of this pin is 10kΩwhen
the output drive setting is "Low". Select
proper resistance value of pull-up or pull
down resistor to get enough output level of
the pin, when the output drive setting is
"Low". Or select that the output drive
setting is "High", depending on the
resistance value of the resister. About
output drive settings, see section 6.10.5.
DATA_IO
Control
COM_VDD
COM_VDD
35
Control
Control
COM_VDD
10k
Control
Low Drive
High Drive
Digital
Input
Data Input
Signal input for modulation at
RF-Transmitting. Behavior of this pin is
different for each state of TC32306FTG
reset.
See Table 5-2.
Notice:
Do not supply higher voltage than the level
of COM_VDD. (For example, in the case
of too low /
no power supply.) That causes
overcurrent at this pin, as the ESD
protection elements insertion between the
pin and the voltage source.
36 IO_GND - Ground(I/O Block)
-

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5.2 Pin Behaviors at Reset and Register Initialized
Several pin behaviors of TC32306FTG depend on setting of Reset, register's initial value, or SPI Mode /
EEPROM Mode (including User Test). See Table 5-2.
Table 5-2 Pin Behaviors at Reset and Register Initialized
Pin
SPI Mode
(TC32306FTG is slave.)
(Including SPI User Test Mode)
EEPROM Mode
(TC32306FTG is master.) EEPROM User Test Mode
(TC32306FTG is slave.)
RESET = ”L” Register’s Initial
(Battery Saving)
RESET = ”L” Battery Saving RESET = ”L” Register’s Initial
(Battery Saving)
MODE2 IN IN IN IN IN IN
MODE1 IN IN IN IN IN IN
CS IN IN High Output High Output IN IN
CLK IN IN Low Output Low Output IN IN
MOSI IN IN Low Output Low Output IN IN
MISO Z Z Z Z Z Z
ENB IN IN IN IN IN IN
TX_SW Pull Down Pull Down IN IN IN IN
RX_SW Pull Down Pull Down IN IN IN IN
DATA_IO Z Low Output Z Low Output Z Low Output
DET_TMONI1,2 Low Output Low Output Low Output Low Output Low Output Low Output
DET_TMONI3,4 Z Z Z Z Z Z
Z: High Impedance
Notice: In SPI Mode, TC32306FTG accepts the input of SPI settings at RESET = "L", but will not act.
In Battery Saving Status, DATA_IO pin behavior changes to the value of register:h'0A[D5]RX_TX. Initial
value of register:h’0A[D5]RX_TX is “0”.
Table 5-3 DATA_IO Pin Behavior in Battery Saving
Pin h’0A[D5]RX_TX = ”0”
(RX: Initial) h'0A[D5]RX_TX = ”1” (TX)
DATA_IO Low Output Z
Z: High Impedance
In Battery Saving Status, MISO pin changes its behavior at SPI Read when TC32306FTG is slave.
Table 5-4 MISO Pin Behavior in Battery Saving (TC32306FTG is slave.)
Pin At SPI Read Except SPI Read
MISO OUT Z
Z: High Impedance