WCH CH32V003 Series User manual

CH32V003 Reference Manual
V1.3
Overview
CH32V003seriesareindustrial-grade general-purposemicrocontrollers designed based on 32-bit RISC-V
instruction setand architecture. ItadoptsQingKeV2Acore, RV32ECinstruction set, and supports 2 levelsof
interruptnesting. Theseriesaremounted withrichperipheralinterfacesand function modules.Itsinternal
organizationalstructure meetsthe low-costand low-powerembedded application scenarios.
Thismanualprovidesdetailed information on the useofthe CH32V003seriesforthe user'sapplication
development,and isapplicabletoproductswithdifferentmemorycapacities,functionalresources,and
packagesinthe series;anydifferenceswill be speciallyexplained in the corresponding functionalchapters.
RISC-Vcore versionoverview
Features
Core
versions
Instruction
set
Hardware
stack
levels
Interrupt
nesting
levels
Numberof
fastinterrupt
channels
Integer
division
periodicity
Vector
table
model
Extensions
instruction
Memory
protection
QingKe
V2A RV32EC 2 2 2 None
Address
or
command
Support None
Abbreviated description ofthe bit attribute in the register:
Registerbit
properties Propertydescription
RF Read-onlypropertythatreadsa fixed value.
RO Read-onlyattribute, changedbyhardware.
RZ Read-onlyproperty, auto bit clear0 afterread operation.
WO Write onlyattribute (notreadable, read value uncertain)
WA Write-onlyattribute, writable in Safe mode.
WZ Write onlyattribute, auto bit clear0 afterwrite operation.
RW Readable and writable.
RWA Readable, writable in Safe mode.
RW1 Readable, write 1 isvalid, write 0 isinvalid.
RW0 Readable, write 0 valid, write 1 invalid.
RW1T Readable, write 0 invalid, write 1 flipped.

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V1.3 1
Chapter1Memoryand BusArchitecture
1.1Busarchitecture
The CH32V003 seriesisdesigned based on the RISC-Vinstruction set, and itsarchitecture interactsthe core,
arbitration unit, DMAmodule, SRAMstorage and otherparts throughmultiple buses.Thedesignintegratesa
general-purposeDMAcontrollertoreduce the CPUload and improveaccess efficiency,aswell asdata
protection mechanisms,automaticclock switching protection mechanismsand othermeasurestoincrease
systemstability.The systemblock diagramisshown in Figure 1-1.
Figure 1-1 CH32V003 systemblock diagram
FLASH
CTRL
Flash
Memory
RISC-V(V2A)
PFIC RV32EC
1-wireSDI
SRAM
I-codeBus
D-codeBus
MUX
LSI-RC
HSE
HSI-RC
*2
SYSCLK
Reset&
MUX& DIV
IWDG_CLK
OSC_IN
OSC_OUT
SWIO
V
DD
:2.7V~5.5V
V
SS
DMA 7 Channels
TIM1
USART
PWR
@VDD
RX,TX,CTS,RTS,CK
4channels
3complementaryChannels
ETR,BIKN
SCL,SDA
MUX
SystemBus
AHBFmax = 50MHz
IWDG
EXTI
EXTEN
ADC
AHBCLK
AIN0~AIN7
ETR ETR2
GPIO
PWR_CLK
WWDG
TIM2
4channels,ETR
AFIO
I2C
GPIOA
GPIOC
PA1 ~PA2
PC0~PC7
GPIOD
PD0~PD7
SPI
MOSI,MISO,SCK,NSS
Amplify
Compare
OPAPx
OPANx
(x=0,1)
OPAO
The systemisequippedwith:Flashaccess prefetchingmechanismtospeed upcodeexecution;general-purpose
DMAcontrollertoreducetheCPUburdenandimproveefficiency;clock tree hierarchy managementtoreduce
the totalpowerconsumptionofperipherals,aswell asdataprotection mechanisms,clock securitysystem
protection mechanismsand othermeasuresto increase systemstability.
lThe instruction bus(I-Code)connectsthe coretotheFLASHinstruction interface andprefetching isdone

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V1.3 2
on thisbus.
lThe databus(D-Code)connectsthe coretothe FLASHdatainterface forconstantloading and debugging.
lThe systembusconnectsthe core to thebusmatrix and isused to coordinateaccessesto the core, DMA,
SRAMand peripherals.
lThe DMAbusisresponsibleforthe DMAofthe AHBmasterinterface connectedtothebusmatrix, which
isaccessed byFLASHdata, SRAMand peripherals.
lThe BusMatrixisresponsibleforthe access coordinationbetween the systembus,databus,DMAbus,
SRAMandAHB/APBbridge.
lThe AHB bridge providesfull synchronousconnectionsbetween the AHBbusand thetwoAPBbuses.
Withdifferentperipheralshooked up underdifferentAPBbuses,differentbusclockscan be configured
to optimize performance according to actualneeds.

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V1.3 3
1.2Memoryimage
TheCH32V003familycontainsprogrammemory,datamemory,coreregisters,peripheralregisters,andmore,
all addressed in a 4GBlinearspace.
Systemstorage storesdatainsmall-end format,i.e., lowbytesarestored atthe lowaddress and high bytesare
stored atthe high address.
Figure 1-2 Storage image
Reserved
WWDG
IWDG
PWR
Reserved
AFIO
EXTI
PortA
PortC
TIM1
SPI
DMA
Reserved
RCC
Reserved
FlashInterface
Reserved
I2C
USART
Reserved
TIM2
Reserved
VendorBytes
Option Bytes
Reserved
Reserved
Reserved
Reserved
Reserved
0x0000 0000
0x2000 0000
4Glinearaddressspace
Peripherals
2KBSRAM
0x2000 0800
0x0000 0000
0x0800 0000
0x1FFFF000
0x40000000
0x40000400
0xE0000000
0xFFFFFFFFF
0x4000 0000
0xE0100000 CorePrivate
Peripherals
FLASH
0x1FFFF780
0x1FFFF800
0x1FFFFFFF
CodeFLASH
16KB
SystemFLASH
(BOOT_1920B)
0x1FFFF840
AliasedtoFlashor
systemmemory
dependingon
software
configuration
0x40002C00
0x40003000
0x40003400
0x40012800
0x40011000
0x40007400
0x40010000
0x40010800
0x40007000
0x40012400
0x40011400
0x40010400
0x40010C00
0x40021000
0x40013400
0x40020000
0x40013000
0x40012C00
0x40022000
0x40022400
0x40021400
0x40020400
0x40023C00
0x40023800
0x1FFFF7C0
0x40005400
0x40005800
0x40011800
0x40013800
0x40013C00
0x50050400
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PortD
ADC
EXTEND
0x08004000
Reserved

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V1.3 4
1.2.1 Memory allocation
Built-in2KBSRAM,starting address 0x20000000, supports byte, half-word(2bytes),and full-word(4bytes)
access.
Built-in 16KBprogramFlash memory(CodeFlash)forstoring userapplications.
Built-in 1920BSystemmemory(bootloader) forstoring the systembootloader(factory-cured bootloader).
Built-in 64Bspace forvendorconfiguration word storage,factory-cured and unmodifiable byusers.
Built-in 64Bspace foruser-selected word storage.

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V1.3 5
Chapter2PowerControl(PWR)
2.1Overview
The systemoperating voltage VDD rangesfrom2.7 to5.5V,and the built-involtage regulatorprovidesthe 1.5V
powersupplyrequired bythe core.
Figure 2-1 Block diagramofpowersupplystructure
VDD powersupplydomain
1.5V
powersupply
domain
I/Ocircuit
Standbycircuit
(Wake-uplogic,
IWDG)
CPUcores
memory
Built-in
digital
peripherals
Voltageregulator
VDD
VSS
ADconverters
resetmodule PLL
2.2Powermanagement
2.2.1 Power-onreset andpower-downreset
The systemhasan internalpower-on resetPOR and apower-downresetPDR circuit.When the chipsupply
voltage VDD fallsbelowthe corresponding thresholdvoltage, the systemisresetbythe relevantcircuit,and no
additionalexternalresetcircuit isrequired. Pleaserefertothe corresponding datasheetforthe parameters of
the power-on threshold voltage VPOR and thepower-down threshold voltage VPDR.
Figure 2-2 Schematic diagramofthe operation ofPOR and PDR
2.2.2 Programmablevoltagedetector
The programmablevoltage monitor,PVD,ismainlyusedtomonitorthe change ofthemainpowersupplyof
the systemand compareit withthe thresholdvoltage setbyPLS[2:0]ofthe powercontrolregisterPWR_CTLR,
V
DD(A)
V
POR
V
PDR
40-110mV Hysteresis
Resetlagtime
t
RSTTEMPO
Resetsignal 0 1 0

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V1.3 6
and withthe externalinterruptregister(EXTI)setting, it can generaterelevantinterruptstonotifythe system
in time forpre-powerdown operationssuch asdata saving.
The specific configuration isasfollows.
1) Setthe PLS[2:0]field ofthe PWR_CTLRregisterto selectthe voltage threshold to bemonitored.
2) Optionalinterrupthandling. the PVDfunction internallyconnectstotherising/falling edge triggersetting
ofline 8ofthe EXTImodule, turnson thisinterrupt(configuresEXTI),and generatesaPVDinterrupt
when VDDdropsbelowthe PVDthresholdorrisesabove the PVDthreshold.
3) Setthe PVDEbit ofPWR_CTLRregisterto enable the PVDfunction.
4) Read thePVD0bit ofPWR_CSRstatusregistertoobtainthe currentsystemmainpowerand PLS[2:0]
setting threshold relationship, and performthe corresponding soft processing.
Figure 2-3 Schematic diagramofPVDoperation
2.3Low-powermodes
Afterasystemreset,the microcontrollerisinanormaloperating state(run mode),wheresystempowercan
be saved byreducing thesystemmainfrequencyorturning offtheunusedperipheralclock orreducingthe
operating peripheralclock. Ifthe systemdoesnotneedtowork,you can setthe systemtoenterlow-power
mode and letthe systemjump outofthisstate byspecificevents.
Microcontrollers currentlyoffer2low-powermodes,divided intermsofoperating differencesbetween
processors, peripherals, voltage regulators, etc.
lSleep mode:The corestopsrunning and all peripherals(including coreprivateperipherals) arestill
running.
lStandbymode:Stop all clocks, wake upand switch the clock to HSI.
Table 2-1 Low-powerMode List
Mode Entry Wake-up source Effecton clock Voltage
regulator
Sleep
WFI Anyinterrupt Core clock OFF,
no effecton other
clocks
ON
WFE Wake-up event
Standby
SetSLEEPDEEP
to 1
SetPDDS to 1
WFIorWFE
AWUevent,NRSTpin reset,
IWDG reset.
ote: Any event can also wake
up the system, but the system
does not reset after waking up.
HSE,HSI,PLL
and peripheral
clock OFF
OFF
ote: The SLEEPDEEP bit belongs to the core private peripheral control bit, CH32V003 product reference
PFIC_SCTLR register.
VDD(A)
Approx.
200mV
hysteresis
PVD
valvevalue
PVD
output
01 1

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V1.3 7
2.3.1 Low-powerconfigurationoptions
lWFIand WFE
WFI: The microcontrolleriswoken up byan interruptsource withinterruptcontrollerresponse, and the
interruptservice function willbe executedfirst afterthe systemwakesup (exceptformicrocontrollerreset).
WFE:The wakeup eventtriggers the microcontrollerto exit low-powermode. Wake-up eventsinclude.
1) ConfigureanexternalorinternalEXTIline toeventmode, whennointerruptcontrollerneedstobe
configured.
2) Orconfigurean interruptsource, equivalenttoaWFIwakeup, wherethe systemprioritizesthe execution
ofthe interruptservice function.
3) Orconfigure theSLEEPONPENbit toturn on peripheralinterruptenable,butnotinterruptenable inthe
interruptcontroller, and the interruptpending bit needstobe cleared afterthe systemwakesup.
lSLEEPONEXIT
Enable:Afterexecuting the WFIorWFEinstruction, the microcontrollerensuresthatall pending
interruptservicesare exited and then enters low-powermode.
Notenabled:The microcontrollerenters low-powermode immediatelyafterexecuting the WFIorWFE
command.
lSEVONPEND
Enable:All interruptsorwake-up eventscan wake up the low-powerconsumption entered byexecuting
WFE.
Notenabled:Onlyinterruptsorwake-up eventsenabled in the interruptcontrollercan wake up the low-
powerconsumption entered byexecuting WFE.
2.3.2 Sleepmode
Inthismode, allI/Opinskeep their stateinRun mode and all peripheralclocksarenormal,so tryto turnoff
useless peripheralclocksbefore entering Sleep mode to reduce low-powerconsumption. Thismode takesthe
shortesttime to wake up.
Enter: Configurecoreregistercontrolbit SLEEPDEEP=0, powercontrolregisterPDDS=0, executeWFIor
WFE, optionallySEVONPENDandSLEEPONEXIT.
Exit: Arbitraryinterruptorwakeup event.
2.3.3 Standby mode
Standbymode isacombination ofperipheralclock controlmechanismsbased on the core'sdeep Sleep mode
(SLEEPDEEP)and allowsthe voltage regulatortooperateatamuch lower-powerconsumption. Thismode
hasthe high frequencyclock (HSE/HSI/PLL)domainturned off,theSRAMand registercontentsheld,and
the I/Opinstateheld. The systemcan continue torun afterthismode wakesup, and the HSIiscalled the
default systemclock.
Ifflashprogramming isinprogress,the systemdoesnotenterStop mode until access tomemoryiscomplete;
if access to the APBisin progress, the systemdoesnotenterStop mode until access to the APBiscomplete.
Standbymode can work modules:IndependentWatchdog (IWDG), LowFrequencyClock (LSI).
Enter: Configurethecoreregistercontrolbit SLEEPDEEP=1, PDDS=1inthepowercontrolregister,and
executeWFIorWFE, optionallySEVONPENDandSLEEPONEXIT.
Exit:
1) Anyinterrupt/event(setin the externalinterruptregister).
2) AWUevent,externalresetonNRSTpin,IWDG reset,clock switchestoHSIafterthiswakeup, system
doesnotreset.
2.3.4 Auto-wakeup (AWU)
Auto-wakeup withoutexternalinterruptscan be implemented. The timebasecan be programmed towake up
periodicallyfromStandbymode.

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V1.3 8
Aprecision externallowfrequency128KHz crystalLSIcan be selected asthe auto-wakeup counttime base.
2.4Registerdescription
Table 2-2PWR-related registers list
Name Access address Description Resetvalue
R32_PWR_CTLR 0x40007000 Powercontrolregister 0x00000000
R32_PWR_CSR 0x40007004 Powercontrol/statusregister 0x00000000
R32_PWR_AWUCSR 0x40007008 Auto-wakeup control/statusregister 0x00000000
R32_PWR_AWUWR 0x4000700C Auto-wakeup windowcomparison
value register 0x0000003f
R32_PWR_AWUPSC 0x40007010 Auto-wakeup crossoverfactorregister 0x00000000
2.4.1 Powercontrolregister(PWR_CTLR)
Offsetaddress:0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PLS[2:0]
PVDE
Reserved
PDDS
Reserved
Bit Name Access Description Reset
value
[31:8] Reserved RO Reserved 0
[7:5] PLS[2:0] RW
PVDvoltage monitoringthresholdsetting. See
the
ElectricalCharacteristicssection ofthe
datasheetfor
detailed instructions.
000:2.85Vrising edge/2.7Vfalling edge.
001:3.05Vrising edge/2.9Vfalling edge.
010:3.3Vrising edge/3.15Vfalling edge.
011:3.5Vrising edge/3.3Vfalling edge.
100:3.7Vrising edge/3.5Vfalling edge.
101:3.9Vrising edge/3.7Vfalling edge.
110:4.1Vrising edge/3.9Vfalling edge.
111:4.4Vrising edge/4.2Vfalling edge.
0
4 PVDE RW
Powersupplyvoltage monitoring function enable flag bit
1:Enable the powersupplyvoltage monitoring function.
0:Disable the powersupplyvoltage monitoring function.
0
[3:2] Reserved RO Reserved 0
1 PDDS RW
Standby/Sleep mode selection bit inpower-down
deep
sleep scenario.
1:EnterStandbymode.
0:EnterSleep mode.
0
0 Reserved RO Reserved 0
2.4.2 Powercontrol/status register(PWR_CSR)
Offsetaddress:0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PVD0
Reserved

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V1.3 9
Bit Name Access Description Reset
value
[31:3] Reserved RO Reserved 0
2 PVD0 RO
PVDoutputstatusflag bit.Thisbit isvalid
when PVDE=1
ofPWR_CTLRregister.
1:VDDand VDDAarebelowthe PVD thresholdset
by
PLS[2:0].
0:VDDand VDDAareabovethe PVDthresholdset
by
PLS[2:0].
0
[1:0] Reserved RO Reserved 0
ote: This register remains unchanged after waking up from Standby mode.
2.4.3 Auto-wakeup control/status register(PWR_AWUCSR)
Offsetaddress:0x08
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
AWU
EN
Reser
ved
Bit Name Access Description Reset
value
[31:2] Reserved RO Reserved 0
1 AWUEN RW
EnableAutomatic wake-up
1:Turn on auto-wakeup;
0:Invalid.
0
0 Reserved RO Reserved 0
2.4.4 Auto-wakeup windowcomparisonvalueregister(PWR_AWUWR)
Offsetaddress:0x0C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
AWUUWR
Bit Name Access Description Reset
value
[31:6] Reserved RO Reserved 0
[5:0] AWUWR RW
AWUwindowvalue, whichisused tocomparewith
the
recursivecountervalue and generateawake-up
signal
when the countervalue isequalto the windowvalue.
0x3f
2.4.5 Auto-wakeup windowcomparisonvalueregister(PWR_AWUWR)
Offsetaddress:0x10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

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V1.3 10
Reserved
AWUPSC
Bit Name Access Description Reset
value
[31:4] Reserved RO Reserved 0
[3:0] AWUPSC RW
Counting time base
0000:Prescaleroff.
0001:Prescaleroff.
0010: Divided by 2
0011: Divided by 4
0100: Divided by 8
0101: Divided by 16
0110: Divided by 32
0111: Divided by 64
1000: Divided by 128
1001: Divided by 256
1010: Divided by 512
1011: Divided by 1024
1100: Divided by 2048
1101: Divided by 4096
1110: Divided by 0x2800
1111: Divided by 0xf000
0

CH32V003 Reference Manual http://wch.cn
V1.3 11
Chapter3Reset and ClockControl(RCC)
The controllerprovidesdifferentformsofresetsandconfigurableclocktree structuresbasedonthe division
ofpowerareasand peripheralpowermanagementconsiderationsinthe application. Thissection describesthe
scope ofeach clockin the system.
3.1Mainfeatures
lMultiple resetforms
lMultiple clock sources, busclock management
lBuilt-in externalcrystaloscillation monitoring and clock securitysystem
lIndependentmanagementofeach peripheralclock:reset,on, off
lSupports internalclock output
3.2Reset
The controllerprovides2 formsofreset: powerResetandsystemReset.
3.2.1 PowerReset
When a powerResetoccurs,it willresetall registers.
ApowerResetisgenerated when the following eventoccurs:
lPower-up/power-down reset(POR/PDR)
3.2.2 SystemReset
When asystemResetoccurs,it will resetthe resetflag inaddition tothecontrol/statusregister
RCC_RSTSCKRand all the registers.The source ofthe reseteventisidentified bylooking atthe resetstatus
flag bit in the RCC_RSTSCKRregister.
AsystemResetisgenerated when one ofthe following eventsoccurs:
lLowsignalon NRSTpin (externalreset)
lWindowwatchdog counttermination (WWDGreset)
lIndependentwatchdogcounttermination (IWDG reset)
lSoftware reset(SWreset)
lLow-powermanagementreset
Window/IndependentWatchdog Reset: Generated bythe window/independentwatchdog peripheraltimer
countcycle overflowtrigger,see itscorresponding section fordetailed description.
Softwarereset: The CH32V003productresetsthe systemviaRESETSYSlocation 1oftheinterrupt
configuration registerPFIC_CFGR inthe programmableinterruptcontrollerPFICorSYSRESETlocation 1
ofthe configuration registerPFIC_SCTLRtoresetthe systemcabinet,refertothe corresponding chapterfor
details.
Low-Powermanagementreset: Standbymode resetwill be enabledbyplacing the STANDBY_RSTlocation
01 inthe userselectbyte.Thiswill performasystemResetinstead ofentering Standbymode afterthe process
ofentering Standbymode isexecuted.

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V1.3 12
Figure 3-1 Systemresetstructure
System
Reset
Power Reset
SoftwareReset
WWDGReset
IWDGReset
Low-power managementReset
RPU
VDD/VDDA
NRST

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V1.3 13
3.3Clock
3.3.1 Systemclockstructure
Figure 3-2 CH32V003 clocktree block diagram
128kHz
LSIRC
IWDGCLK
toindependentwatchdog
OSC_IN
OSC_OUT
4~25MHz
HSEOSC
24MHz
HSIRC
*2
SW
MCO
MCO[1:0]
HSE
HSI
PLLCLK
AHBprescaler
/1,/2.../256
toFlash（register）
FCLKcorefreerunningclock
SYSCLK
48MHz max
HCLK
RCC_CFGR0
PLLSRC
peripheralclockenable
toSRAM/DMA
toAHBperipherals
peripheralclockenable
toTIM2
toTIM1
/2,/4,/6,/8,/12,/1
6…,/64,/96,/128
ADCPRE
toADC
toIWDG
/3 toFlash(timebase)
HSI
CSS
/8 toCoreSystemTimer
peripheralclockenable
SW
peripheralclockenable
peripheralclockenable
togpio(internal,totime)
topwr(lowpowerclocksource)

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V1.3 14
3.3.2 High-speedclock(HSI/HSE)
HSIisahigh-speed clock signalgenerated bythe system'sinternal24MHzRC oscillator.HSIRC oscillator
can provide systemclock withoutanyexternaldevices.Ithasashort start-up time. HSIisenabled and disabled
bysetting the HSIONbit inthe RCC_CTLRregister,and theHSIRDYbit indicateswhethertheHSIRC
oscillatorisstable ornot.The systemdefaultsHSION and HSIRDYto 1 (it isrecommended notto turn them
off). If the HSIRDYIEbit in the RCC_INTR registerisset, the corresponding interruptwill be generated.
lFactorycalibration:The difference ofmanufacturing process will causedifferentRC oscillation
frequencyforeach chip, soHSIcalibration isperformed foreach chipbeforeit isshipped. Aftersystem
reset, the factorycalibration value isloaded into HSICAL[7:0]ofthe RCC_CTLRregister.
lUsertuning:Basedondifferentvoltagesorambienttemperatures,the application can adjusttheHSI
frequencybyusing the HSITRIM[4:0]bitsin the RCC_CTLRregister.
ote: If the HSE crystal oscillator fails, the HSI clock is used as a backup clock source (clock safety system).
HSEisan externalhigh speedclock signal,including externalcrystal/ceramicresonatorgeneration orexternal
high speed clock feed.
lExternalCrystal/CeramicResonator(HSECrystal):Anexternal4-25MHzoscillatorprovidesamore
accurateclocksourceforthesystem.Furtherinformationcan befoundintheElectricalCharacteristics
section ofthedatasheet.TheHSEcrystalcan be turnedonandoffbysetting the HSEON bit inthe
RCC_CTLRregister.TheHSERDYbit indicateswhetherthe HSEcrystaloscillation isstableornot,and
the hardwarefeedsthe clock intothe systemonlyafterHSERDYposition 1. Ifthe HSERDYIEbit ofthe
RCC_INTRregisterisset, the corresponding interruptwill be generated.
Figure 3-3 High-speed externalcrystalcircuit
ote: The load capacitor needs to be as close to the oscillator pin as possible and the capacitance value should
be selected according to the crystal manufacturer's parameters.
lExternalHigh-speed ClockSource(HSEBypass):Thismode feedstheclocksource directlyfromthe
externaltothe OSC_INpin,withthe OSC_OUTpindangling. The maximumfrequencysupported is
25MHz. The application needstosetthe HSEBYPbit toturnon the HSEbypass function withthe
HSEONbit at0, and then setthe HSEONbit again.
Figure 3-4 High-speed clock source circuit
OSC_IN
OSC_OUT
C
L1
C
L2
4 ～ 25MHz
Load
Capacitance
OSC_IN
fHSE_ext
Externalclock
source
OSC_OUT
(Suspended)

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V1.3 15
3.3.3 Low-speedclock(LSI)
The LSIisalow-speed clock signalgenerated bythe system'sinternalRC oscillatorofapproximately128
KHz. Itcan be keptrunninginshutdownand standbymodesandprovidesthe clockreference forthe RTC
clock, independentwatchdog andwake-up unit.Furtherinformation can be found intheElectrical
Characteristicssection ofthedatasheet.the LSIcan be enabled and disabled bysettingthe LSION bit inthe
RCC_RSTSCKRregisterand then detecting whethertheLSIRC oscillation isstablebyinterrogating the
LSIRDYbit,andthehardwarefeedstheclockinonlyafterLSIRDYposition 1.Ifthe LSIRDYIEbit inthe
RCC_INTRregisterisset, the corresponding interruptwill be generated.
3.3.4 PLLclock
Byconfiguring the RCC_CFGR0registerand the extended registerEXTEND_CTR,the internalPLLclock
can select2clocksources,thesesettingsmustbe done beforePLListurned on, once PLLisstarted these
parameters cannotbe changed. Setthe PLLON bit in the RCC_CTLRregisterto be enabled and disabled, the
PLLRDYbit toindicatewhetherthe PLLclock isstable, and the hardwaretofeed theclock intothe system
onlyafterPLLposition 1. If the PLLRDYIEbit ofthe RCC_INTR registerisset, the corresponding interrupt
will be generated.
PLLclock source:
lHSIclock
lHSEClock
3.3.5 Bus/Peripheralclock
3.3.5.1 Systemclock (SYSCLK)
Configurethe systemclock source byconfiguring the RCC_CFGR0registerSW[1:0]bits,SWS[1:0]indicates
the currentsystemclock source.
lHSIassystemclock
lHSEassystemclock
lPLLassystemclock
Afteracontrollerreset,the default HSIclock isselected asthe systemclock source. Switching between clock
sourcesmustoccuronlywhen the targetclock source isready.
3.3.5.2 AHB/APB1/APB2busperipheralclock (HCLK/PCLK1/PCLK2)
The AHB,APB1, and APB2busclockscan be configuredbyconfiguring the HPRE[3:0],PPRE1[2:0],and
PPRE2[2:0]bitsofthe RCC_CFGR0register,respectively.Thesebusclocksdetermine the peripheralinterface
access clockreferencethatismounted belowthem.Applicationscan adjustdifferentvaluestoreducethe
powerconsumption when some ofthe peripheralsare operating.
The variousbitsinthe RCC_APB1PRSTR and RCC_APB2PRSTR registers can resetthe differentperipheral
modulesto their initialstate.
Each bit inthe RCC_AHBPCENR,RCC_APB1PCENR,and RCC_APB2PCENRregisters can be usedto
individuallyturnon oroffthecommunication clock interface fordifferentperipheralmodules.When using a
peripheral, you firstneed to turn on itsclock enable bit inorderto access itsregisters.
3.3.5.3 Independentwatchdog clock
Ifthe standalone watchdog hasbeen setbyhardwareconfiguration orstarted bysoftware, the LSIoscillator
will be forced on and cannotbe turned off.Afterthe LSIoscillatorisstabilized, the clock issupplied tothe
IWDG.

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V1.3 16
3.3.5.4 Microcontrollerclock output(MCO)
The microcontrollerallowsoutputting clock signalstothe MCOpins.The following 4clocksignalscan be
selected asMCOclock outputsbyconfiguring the multiplexed push-pull outputmode inthe corresponding
GPIOport registers byconfiguring the MCO[2:0]bitsofthe RCC_CFGR0 register.
lSystemclock (SYSCLK)output
lHSIclock output
lHSEclock output
lPLLclock outputafter2Xfrequency
3.3.6 Clocksecurity system
The clock safetysystemisanoperationalprotection mechanismforthe controllerthatswitchestothe HSI
clock inthe eventofan HSEclock transmit failureand generatesan interruptnotification toallowthe
application software to complete a rescue operation.
The clock securitysystemisactivated bysetting CSSONposition 1 ofthe RCC_CTLRregister.Atthispoint,
the clockmonitorwill be enabled aftertheHSEoscillatorstart (HSERDY=1)delayand will be turnedoffafter
the HSEclock isturned off.Once the HSEclock failsduring systemoperation, the HSEoscillatorwill be
turned off,the clock failureeventwillbe senttothe brake inputofthe advanced-controltimer(TIM1)and a
clock safetyinterruptwill be generated withCSSFposition 1andthe application entersthe NMInon-maskable
interrupt.Bysetting the CSSCbit,the CSSFbit flag can be cleared and the NMIinterruptpendingbit canbe
undone.
Ifthe currentHSEisusedasthe systemclock, orif the currentHSEisusedasthe PLLinputclock and the
PLLisused asthe systemclock, the clocksafety systemwill automaticallyswitch the systemclock tothe HSI
oscillatorand turn offthe HSEoscillatorand PLLin case ofHSEfailure.
3.4Registerdescription
Table 3-1 RCC-related registers list
Name Access address Description Resetvalue
R32_RCC_CTLR 0x40021000 Clock controlregister 0x0000xx83
R32_RCC_CFGR0 0x40021004 Clock configuration register0 0x00000000
R32_RCC_INTR 0x40021008 Clock interruptregister 0x00000000
R32_RCC_APB2PRSTR 0x4002100C APB2 peripheralresetregister 0x00000000
R32_RCC_APB1PRSTR 0x40021010 APB1 peripheralresetregister 0x00000000
R32_RCC_AHBPCENR 0x40021014 AHB peripheralclock enableregister 0x00000014
R32_RCC_APB2PCENR 0x40021018 APB2 peripheralclock enable register 0x00000000
R32_RCC_APB1PCENR 0x4002101C APB1 peripheralclock enable register 0x00000000
R32_RCC_RSTSCKR 0x40021024 Control/statusregister 0x0C000000
3.4.1 Clockcontrolregister(RCC_CTLR)
Offsetaddress:0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PLL
RDY
PLL
ON
Reserved
CSSO
N
HSE
BYP
HSE
RDY
HSE
ON
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HSICAL[7:0] HSITRIM[4:0]
Reser
ved
HSI
RDY
HSIO
N
Bit Name Access Description Reset
value
[31:26] Reserved RO Reserved 0

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V1.3 17
25 PLLRDY RO
PLLclock-readylock flag bit.
1:PLLclock lock.
0:PLLclock isnotlocked.
0
24 PLLON RW
PLLclock enable controlbit.
1:Enablesthe PLLclock.
0:Turn offthe PLLclock.
ote: After entering Standby low-power mode,
this bit is
cleared by hardware to 0.
0
[23:20] Reserved RO Reserved 0
19 CSSON RW
Clock securitysystemenable controlbit.
1:Enablethe clocksecuritysystem.When HSE
isready
(HSERDYsetto1),the hardwareturns
on the clock
monitoring function ofHSEand
triggers CSSFflag and
NMIinterruptwhen HSE
isfound tobe abnormal; when
HSEisnotready,
the hardwareturnsoffthe clock
monitoring function ofHSE.
0:Turnsoffthe clock securitysystem.
0
18 HSEBYP RW
Externalhigh-speed crystalbypass controlbit.
1:Bypass externalhigh-speed crystal/ceramic
resonators
(using an externalclock source).
0:Nobypass ofhigh-speed external
crystal/ceramic
resonators.
ote: This bit needs to be written with HSEO at 0.
0
17 HSERDY RO
Externalhigh-speed crystaloscillation
stabilization ready
flag bit (setbyhardware).
1:Stable externalhigh-speedcrystaloscillation.
0:Externalhigh-speed crystaloscillation isnotstabilized.
ote: After the HSEO bit is cleared to 0, it
takes 6 HSE
cycles for this bit to clear to 0.
0
16 HSEON RW
Externalhigh-speed crystaloscillation enable controlbit.
1:Enablesthe HSEoscillator.
0:Turn offthe HSEoscillator.
ote: This bit is cleared to 0 by hardware after
entering
Standby low-power mode.
0
[15:8] HSICAL RO Internalhigh-speed clock calibration values,
which are
automaticallyinitialized atsystemstartup. xxh
[7:3] HSITRIM RW
Internalhigh-speed clock adjustmentvalue.
The usercanenteran adjustmentvalue to
superimposeon
the HSICAL[7:0]value toadjust
the frequencyofthe
internalHSIRCoscillator
based on voltage and
temperature variations.
The default value is16, which can adjustthe
HSIto
24MHz 1%; the change ofHSICALis
adjusted about
60KHz perstep.
10000
2 Reserved RO Reserved 0
1 HSIRDY RO
Internalhigh-speed clock (24MHz)Stable
Readyflag bit
(setbyhardware).
1:Stable internalhigh-speed clock (24MHz).
0:The internalhigh-speed clock (24MHz)isnotstable.
ote: After the HSIO bit is cleared to 0, it
takes 6 HSI
cycles for the bit to be cleared to 0.
1
0 HSION RW
Internalhigh-speed clock (24MHz)enable controlbit.
1:Enablesthe HSIoscillator.
0:Turn offthe HSIoscillator.
ote: This bit is set to 1 by hardware to start
the internal
24MHz RC oscillator when
returning from standby mode
or when the external
oscillator HSE used as the system
clock fails.
1

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V1.3 18
3.4.2 Clockconfigurationregister0(RCC_CFGR0)
Offsetaddress:0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved MCO[2:0] Reserved
PLL
SRC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCPRE[
4
:0]
Reserved
HPRE[3:0]
SWS[1:0]
SW[1:0]
Bit Name Access Description Reset
value
[31:27] Reserved RO Reserved 0
[26:24] MCO RW
MicrocontrollerMCOpin clock outputcontrol.
0xx:no clock output.
100:Systemclock (SYSCLK)output.
101:Internal24 MHzRCoscillatorclock
(HSI)output.
110:Externaloscillatorclock (HSE)output.
111:PLLclock output.
0
[23:17] Reserved RO Reserved 0
16 PLLSRC RW
Inputclock source forPLL(write onlywhen PLLisoff).
1:HSEisfed intoPLLwithoutdividing the frequency.
0:HSIisnotdivided and sentto PLL.
0
[15:11] ADCPRE RW
ADC clock source prescalercontrol{13:11,15:14}.
000xx:AHBCLKdivided by2 asADCclock.
010xx:AHBCLKdivided by4 asADCclock.
100xx:AHBCLKdivided by6 asADCclock.
110xx:AHBCLKdivided by8 asADCclock.
00100:AHBCLKdivided by4 asADCclock.
01100:AHBCLKdivided by8 asADCclock.
10100:AHBCLKdivided by12 asADCclock.
11100:AHBCLKdivided by16 asADCclock.
00101:AHBCLKdivided by8 asADCclock.
01101:AHBCLKdivided by16 asADCclock.
10101:AHBCLKdivided by24 asADCclock.
11101:AHBCLKdivided by32 asADCclock.
00110:AHBCLKdivided by16 asADCclock.
01110:AHBCLKdivided by32 asADCclock.
10110:AHBCLKdivided by48 asADCclock.
11110:AHBCLKdivided by64 asADCclock.
00111:AHBCLKdivided by32 asADCclock.
01111:AHBCLKdivided by64 asADCclock.
10111:AHBCLKdivided by96 asADCclock.
11111:AHBCLKdivided by128 asADC clock.
ote: The ADC clock should not exceed a maximum
of
24MHz.
0
[10:8] Reserved RW Reserved 0
[7:4] HPRE RW
AHB clock source prescalercontrol.
0000:Prescaleroff.
0001:SYSCLKdivided by2.
0010:SYSCLKdivided by3.
0011:SYSCLKdivided by4.
0100:SYSCLKdivided by5.
0101:SYSCLKdivided by6.
0110:SYSCLKdivided by7.
0

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V1.3 19
0111:SYSCLKdivided by8.
1000:SYSCLKdivided by2.
1001:SYSCLKdivided by4.
1010:SYSCLKdivided by8.
1011:SYSCLKdivided by16.
1100:SYSCLKdivided by32.
1101:SYSCLKdivided by64.
1110:SYSCLKdivided by128.
1111:SYSCLKdivided by256.
ote: When the prescaler factor of the AHB clock
source is
greater than 1, the prefetch buffer must be turned on.
[3:2] SWS RO
Systemclock (SYSCLK)status(hardware set).
00:the systemclock source isHSI.
01:The systemclock source isHSE.
10:The systemclock source isa PLL.
11:Notavailable.
0
[1:0] SW RW
Selectthe systemclock source.
00:HSIassystemclock.
01:HSEassystemclock.
10:PLLoutputassystemclock.
11:Notavailable.
ote: With Clock Safe enabled (CSSO=1), HSI is
forced
by hardware to be selected as the system
clock when
returning from Standby and Stop mode
or when the
external oscillator HSE used as the system clock fails.
0
3.4.3 Clockinterruptregister(RCC_INTR)
Offsetaddress:0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved CS
SC
Reserved
PLL
RDY
C
HSE
RDY
C
HSI
RDY
C
Reser
ved
LSI
RDY
C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PLL
RDYI
E
HSE
RDYI
E
HSI
RDYI
E
Reserv
ed
LSI
RDYIE
CS
SF
Reserved
PLL
RDY
F
HSE
RDY
F
HSI
RDY
F
Reser
ved
LSI
RDY
F
Bit Name Access Description Reset
value
[31:24] Reserved RO Reserved 0
23 CSSC WO
Clearthe clock securitysysteminterruptflag bit (CSSF).
1:Clearthe CSSFinterruptflag.
0:No action.
0
[22:21] Reserved RO Reserved 0
20 PLLRDYC WO
Clearthe PLL-readyinterruptflag bit.
1:Clearthe PLLRDYFinterruptflag.
0:No action.
0
19 HSERDYC WO
Clearthe HSEoscillatorreadyinterruptflag bit.
1:Clearthe HSERDYFinterruptflag.
0:No action.
0
18 HSIRDYC WO
Clearthe HSIoscillatorreadyinterruptflag bit.
1:Clearthe HSIRDYFinterruptflag.
0:No action.
0
17 Reserved RO Reserved 0
16 LSIRDYC WO
Clearthe LSIoscillatorreadyinterruptflag bit.
1:Clearthe LSIRDYFinterruptflag. 0