Texas Instruments MSP430F42 series User manual

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 400 μA at 1 MHz, 3.0 V
− Standby Mode: 1.6 μA
− Off Mode (RAM Retention): 0.1 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
DFrequency-Locked Loop, FLL+
D16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
DThree Independent 16-bit Sigma-Delta A/D
Converters With Differential PGA Inputs
D16-Bit Timer_A With Three
Capture/Compare Registers
DIntegrated LCD Driver for 128 Segments
DSerial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader in Flash Devices
DFamily Members Include:
− MSP430F423:
8KB + 256B Flash Memory,
256B RAM
− MSP430F425:
16KB + 256B Flash Memory,
512B RAM
− MSP430F427:
32KB + 256B Flash Memory,
1KB RAM
DAvailable in 64-Pin Quad Flat Pack (QFP)
DFor Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430F42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D
converters, each with an integrated differential programmable gain amplifier input stage. Also included is a
built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier, and 14 I/O pins.
Typical applications include high resolution applications such as handheld metering equipment, weigh scales,
and energy meters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Copyright ©2004−2007 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC 64-PIN QFP
(PM)
−40°C to 85°C
MSP430F423IPM
MSP430F425IPM
MSP430F427IPM
pin designation{
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.5/TACLK/ACLK/S28
P2.3/SVSIN P2.4/UTXD0 P2.5/URXD0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1/S31 P1.3/SVSOUT/S3
0
P1.4/S29
S5 S6 S7 S8 S9
S10 S11 S12 S13 S14 S15 S16 S17
S18
S19 S20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P2.0/TA2/S25
P2.1/UCLK0/S24
R33
R23
R13
R03
COM3
COM2
COM1
COM0
S23
S21
S22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0.0+
A0.0−
A1.0+
A1.0−
A2.0+
A2.0−
XIN
XOUT
P2.2/STE0
S0
S1
S2
S4
S3
MSP430F42x
VREF
AVCC
DVCC
AVSS
DVSS
†Open connection recommended for all unused analog inputs.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
functional block diagram
SD16
Three 16-bit
Sigma-Delta
A/D
Converters
DVCC DVSS AVCC AVSS
RST/NMI
P1
Flash
32KB
16KB
8KB
RAM
1KB
512B
256B
Watchdog
WDT+
15/16-Bit
Timer_A3
3 CC Reg
Port 1
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128
Segments
1,2,3,4 MUX
fLCD
8
USART0
UART or
SPI
Function
Oscillators
FLL+
MCLK
8 MHz
CPU
incl. 16
Registers
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P2
Port 2
6 I/O
Interrupt
Capability
6
Module Hardware
Multiplier
MPY, MPYS
MAC,MACS

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
MSP430F42x Terminal Functions
TERMINAL
PN I/O DESCRIPTION
NAME NO.
I/O
DESCRIPTION
DVCC 1Digital supply voltage, positive terminal.
A0.0+ 2 I Internal connection to SD16 Channel 0, input 0 +. (see Note 1)
A0.0− 3 I Internal connection to SD16 Channel 0, input 0 −. (see Note 1)
A1.0+ 4 I Internal connection to SD16 Channel 1, input 0 +. (see Note 1)
A1.0− 5 I Internal connection to SD16 Channel 1, input 0 −. (see Note 1)
A2.0+ 6 I Internal connection to SD16 Channel 2, input 0 +. (see Note 1)
A2.0− 7 I Internal connection to SD16 Channel 2, input 0 −. (see Note 1)
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VREF 10 I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
P2.2/STE0 11 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
S0 12 O LCD segment output 0
S1 13 O LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
COM0 36 O Common output, COM0−3 are used for LCD backplanes.
COM1 37 O Common output, COM0−3 are used for LCD backplanes.
COM2 38 O Common output, COM0−3 are used for LCD backplanes.
COM3 39 O Common output, COM0−3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
NOTE 1: Open connection recommended for all unused analog inputs.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
MSP430F42x Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
R13 41 I Input port of third most positive analog LCD level (V4 or V3)
R23 42 I Input port of second most positive analog LCD level (V2)
R33 43 O Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24 44 I/O General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.0/TA2/S25 45 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
P1.7/SOMI0/S26 46 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.6/SIMO0/S27 47 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28 48 I/O General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) / LCD segment output 28 (See Note 1)
P1.4/S29 49 I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30 50 I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
P1.2/TA1/S31 51 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.1/TA0/MCLK 52 I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 58 I Reset input or nonmaskable interrupt input port
P2.5/URXD0 59 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 60 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/SVSIN 61 I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
AVSS 62 Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.
DVSS 63 Digital supply voltage, negative terminal
AVCC 64 Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry; must not power up prior to DVCC.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control remains active
DLow-power mode 1 (LPM1)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
0FFFAh 13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFF8h 12
0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable 0FFEAh 5
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (from 0600h to 0BFFh).

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
321
rw–0 rw–0 rw–0
Address
0h URXIE0 ACCVIE NMIIE
rw–0 rw–0 rw–0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
7654 0321
Address
1h BTIE
rw-0
BTIE: Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
321
rw–0 rw–1 rw–(0)
Address
02h URXIFG0 NMIIFG
rw–1 rw–0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0321
Address
3h BTIFG
rw-0
BTIFG: Basic Timer1 interrupt flag

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
module enable registers 1 and 2
7654 0
UTXE0
321
rw–0 rw–0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0321
Address
05h
Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC.
rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.
memory organization
MSP430F423 MSP430F425 MSP430F427
Memory
Interrupt vector
Code memory
Size
Flash
Flash
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory Size 256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory Size 1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
RAM Size 256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function PM Package Pins
Data Transmit 53 - P1.0
Data Receive 52 - P1.1

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
11
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
With Interrupt Vectors
Segment 1
Segment 2
Segment n−1
Segment n
32KB
Segment A
Segment B
Main Memory
Information Memory
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
08400h
083FFh
08200h
081FFh
01000h
010FFh
08000h
01080h
0107Fh
16KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
01000h
010FFh
0C000h
01080h
0107Fh
8KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0E400h
0E3FFh
0E200h
0E1FFh
01000h
010FFh
0E000h
01080h
0107Fh

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
12 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, TI literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430F42x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low
power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with
a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module
provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
DRead/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port
P2 are implemented.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
13
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number
48 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
48 - P1.5 TACLK INCLK
53 - P1.0 TA0 CCI0A 53 - P1.0
52 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
51 - P1.2 TA1 CCI1A 51 - P1.2
51 - P1.2 TA1 CCI1B
CCR1
TA1
DVSS GND CCR1 TA1
DVCC VCC
45 - P2.0 TA2 CCI2A 45 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
USART0
The MSP430F42x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
SD16
The SD16 module integrates three independent 16-bit sigma-delta A/D converters, internal temperature sensor
and built-in voltage reference. Each channel is designed with a fully differential analog input pair and
programmable gain amplifier input stage.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
14 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog Timer control WDTCTL 0120h
Timer_A3 Timer_A interrupt vector TAIV 012Eh
_
Timer_A control TACTL 0160h
Capture/compare control 0 TACCTL0 0162h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 2 TACCTL2 0166h
Timer_A register TAR 0170h
Capture/compare register 0 TACCR0 0172h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 2 TACCR2 0176h
Hardware Multiplier Sum extend SUMEXT 013Eh
p
Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
SD16 General Control SD16CTL 0100h
(see also: Peripherals
with Byte Access)
Channel 0 Control SD16CCTL0 0102h
with Byte Access) Channel 1 Control SD16CCTL1 0104h
Channel 2 Control SD16CCTL2 0106h
Reserved 0108h
Reserved 010Ah
Reserved 010Ch
Reserved 010Eh
Interrupt vector word register SD16IV 0110h
Channel 0 conversion memory SD16MEM0 0112h
Channel 1 conversion memory SD16MEM1 0114h
Channel 2 conversion memory SD16MEM2 0116h
Reserved 0118h
Reserved 011Ah
Reserved 011Ch
Reserved 011Eh

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
15
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
SD16 Channel 0 Input Control SD16INCTL0 0B0h
(see also: Peripherals
with Word Access)
Channel 1 Input Control SD16INCTL1 0B1h
with Word Access) Channel 2 Input Control SD16INCTL2 0B2h
Reserved 0B3h
Reserved 0B4h
Reserved 0B5h
Reserved 0B6h
Reserved 0B7h
Channel 0 preload SD16PRE0 0B8h
Channel 1 preload SD16PRE1 0B9h
Channel 2 preload SD16PRE2 0BAh
Reserved 0BBh
Reserved 0BCh
Reserved 0BDh
Reserved 0BEh
Reserved 0BFh
LCD LCD memory 20 LCDM20 0A4h
: : :
LCD memory 16 LCDM16 0A0h
LCD memory 15 LCDM15 09Fh
: : :
LCD memory 1 LCDM1 091h
LCD control and mode LCDCTL 090h
USART0 Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Brownout, SVS SVS control register SVSCTL 056h
FLL+ Clock FLL+ Control1 FLL_CTL1 054h
FLL+ Control0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter2 BTCNT2 047h
BT counter1 BTCNT1 046h
BT control BTCTL 040h

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
16 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
17
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
absolute maximum ratings†
Voltage applied at VCC to VSS −0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note 1) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
PARAMETER MIN NOM MAX UNITS
Supply voltage during program execution; SD16 disabled.
VCC (AVCC = DVCC = VCC) (see Note 1) MSP430F42x 1.8 3.6 V
Supply voltage during program execution; SD16 disabled, SVS enabled, and
PORON = 1. VCC (AVCC = DVCC = VCC) (see Note 1 and Note 2) MSP430F42x 2.0 3.6 V
Supply voltage during program execution; SD16 enabled or
during programming of flash memory. VCC (AVCC = DVCC = VCC)MSP430F42x 2.7 3.6 V
Supply voltage, VSS (AVSS = DVSS = VSS) 0 0 V
Operating free-air temperature range, TAMSP430F42x −40 85 °C
LF selected, XTS_FLL=0 Watch crystal 32768 Hz
LFXT1 crystal frequency, f
(
LFXT1
)
(see Note 3) XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000 kHz
LFXT1
crystal
frequency,
f(LFXT1)
(see
Note
3)
XT1 selected, XTS_FLL=1 Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f
VCC = 1.8 V DC 4.15
MHz
Processor frequency (signal MCLK), f(System) VCC = 3.6 V DC 8 MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The LFXT1 oscillator in LF-mode requires a watch crystal.
f (MHz)
1.8 V 3.6 V
2.7 V 3 V
4.15 MHz
8 MHz
VCC − Supply Voltage − V
fSystem − Maximum Processor Frequency − MHz
Supply Voltage Range with SD16
Enabled or During Programming
of the Flash Memory
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Supply Voltage Range
During Program
Execution
6 MHz
Figure 1. Frequency vs Supply Voltage

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
18 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
I(AM)
Active mode,
f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
(program executes in flash)
TA= −40°C to 85°C VCC = 3 V 400 500 μA
I(LPM0)
Low-power mode, (LPM0/LPM1)
f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0 (see Note 2)
TA= −40°C to 85°C VCC = 3 V 130 150 μA
I(LPM2) Low-power mode, (LPM2) (see Note 2) TA= −40°C to 85°C VCC = 3 V 10 22 μA
TA= −40°C 1.5 2.0
I
Low power mode (LPM3) (see Note 2)
TA= 25°C
V3V
1.6 2.1
A
I(LPM3) Low-power mode, (LPM3) (see Note 2) TA= 60°CVCC = 3 V 1.7 2.2 μA
TA= 85°C 2.0 2.6
TA= −40°C 0.1 0.5
I
(
LPM4
)
Low-power mode, (LPM4) (see Note 2) TA= 25°CVCC = 3 V 0.1 0.5 μA
I(LPM4)
Low power
mode,
(LPM4)
(see
Note
2)
TA= 85°C
VCC
3
V
0.8 2.5
μA
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The current consumption in LPM2, LPM3, and LPM4 are measured with active Basic Timer1 and LCD (ACLK selected).
The current consumption of the SD16 and the SVS module are specified in their respective sections.
LPMx currents measured with WDT disabled.
The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
2. Current for brownout included.
current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] ×f(System) [MHz]
current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 170 μA/V ×(VCC – 3 V)

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
19
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.98 V
VIT− Negative-going input threshold voltage VCC = 3 V 0.9 1.3 V
Vhys Input voltage hysteresis (VIT+ − VIT−) VCC = 3 V 0.45 1 V
inputs Px.x, TAx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, External tri
gg
er si
g
nal 3 V 1.5 cycle
t(int) External interrupt timing
Port
P1
,
P2:
P1
.
x
to
P2
.
x
,
External
trigger
signal
for the interrupt flag, (see Note 1) 3 V 50 ns
t(cap) Timer_A, capture timing TAx 3 V 50 ns
f(TAext) Timer_A clock frequency
externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz
f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Ilkg(P1.x) Leaka
g
ePort P1 Port 1: V(P1.x) (see Note 2)
V=3V
±50
nA
Ilkg(P2.x)
Leakage
current Port P2 Port 2: V(P2.x) (see Note 2) VCC = 3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
outputs − Ports P1 and P2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
High level output voltage
IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC
V
VOH High-level output voltage IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC V
V
Low level output voltage
IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25
V
VOL Low-level output voltage IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the
maximum specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the
maximum specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fPx.y (1 ≤x ≤2, 0 ≤y ≤7) CL= 20 pF,
IL= ±1.5mA VCC = 3 V DC 12 MHz
fACLK,
fMCLK,
fSMCLK
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28 CL= 20 pF VCC = 3 V 12 MHz
P1.5/TACLK/ACLK/
fACLK = fLFXT1 = fXT1 40% 60%
P1
.
5/TACLK/ACLK/
S28, CL= 20 pF fACLK = fLFXT1 = fLF 30% 70%
tXdc
Duty cycle of output frequency
S28,
CL
20
pF
VCC = 3 V fACLK = fLFXT1 50%
t
Xdc
Duty
cycle
of
output
frequency
P1.1/TA0/MCLK,
CL= 20 pF,
VCC = 3 V
fMCLK = fDCOCLK 50%−
15 ns 50% 50%+ 15 ns

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
20 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 and P2 (continued)
Figure 2
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.1
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA= 25°C
TA= 85°C
OL
I− Typical Low-level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.1
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA= 25°C
TA= 85°C
OL
I− Typical Low-level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.1
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA= 25°C
TA= 85°C
OL
I− Typical High-level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−50
−40
−30
−20
−10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.1
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA= 25°C
TA= 85°C
OL
I− Typical High-level Output Current − mA
NOTE: One output loaded at a time