Texas Instruments MSP430F42 series User manual

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 400 μA at 1 MHz, 3.0 V
− Standby Mode: 1.6 μA
− Off Mode (RAM Retention): 0.1 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
DFrequency-Locked Loop, FLL+
D16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
DThree Independent 16-bit Sigma-Delta A/D
Converters With Differential PGA Inputs
D16-Bit Timer_A With Three
Capture/Compare Registers
DIntegrated LCD Driver for 128 Segments
DSerial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader in Flash Devices
DFamily Members Include:
− MSP430F423:
8KB + 256B Flash Memory,
256B RAM
− MSP430F425:
16KB + 256B Flash Memory,
512B RAM
− MSP430F427:
32KB + 256B Flash Memory,
1KB RAM
DAvailable in 64-Pin Quad Flat Pack (QFP)
DFor Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430F42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D
converters, each with an integrated differential programmable gain amplifier input stage. Also included is a
built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier, and 14 I/O pins.
Typical applications include high resolution applications such as handheld metering equipment, weigh scales,
and energy meters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Copyright ©2004−2007 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC 64-PIN QFP
(PM)
−40°C to 85°C
MSP430F423IPM
MSP430F425IPM
MSP430F427IPM
pin designation{
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.5/TACLK/ACLK/S28
P2.3/SVSIN P2.4/UTXD0 P2.5/URXD0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1/S31 P1.3/SVSOUT/S3
0
P1.4/S29
S5 S6 S7 S8 S9
S10 S11 S12 S13 S14 S15 S16 S17
S18
S19 S20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P2.0/TA2/S25
P2.1/UCLK0/S24
R33
R23
R13
R03
COM3
COM2
COM1
COM0
S23
S21
S22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0.0+
A0.0−
A1.0+
A1.0−
A2.0+
A2.0−
XIN
XOUT
P2.2/STE0
S0
S1
S2
S4
S3
MSP430F42x
VREF
AVCC
DVCC
AVSS
DVSS
†Open connection recommended for all unused analog inputs.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
functional block diagram
SD16
Three 16-bit
Sigma-Delta
A/D
Converters
DVCC DVSS AVCC AVSS
RST/NMI
P1
Flash
32KB
16KB
8KB
RAM
1KB
512B
256B
Watchdog
WDT+
15/16-Bit
Timer_A3
3 CC Reg
Port 1
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128
Segments
1,2,3,4 MUX
fLCD
8
USART0
UART or
SPI
Function
Oscillators
FLL+
MCLK
8 MHz
CPU
incl. 16
Registers
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P2
Port 2
6 I/O
Interrupt
Capability
6
Module Hardware
Multiplier
MPY, MPYS
MAC,MACS

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
MSP430F42x Terminal Functions
TERMINAL
PN I/O DESCRIPTION
NAME NO.
I/O
DESCRIPTION
DVCC 1Digital supply voltage, positive terminal.
A0.0+ 2 I Internal connection to SD16 Channel 0, input 0 +. (see Note 1)
A0.0− 3 I Internal connection to SD16 Channel 0, input 0 −. (see Note 1)
A1.0+ 4 I Internal connection to SD16 Channel 1, input 0 +. (see Note 1)
A1.0− 5 I Internal connection to SD16 Channel 1, input 0 −. (see Note 1)
A2.0+ 6 I Internal connection to SD16 Channel 2, input 0 +. (see Note 1)
A2.0− 7 I Internal connection to SD16 Channel 2, input 0 −. (see Note 1)
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VREF 10 I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
P2.2/STE0 11 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
S0 12 O LCD segment output 0
S1 13 O LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
COM0 36 O Common output, COM0−3 are used for LCD backplanes.
COM1 37 O Common output, COM0−3 are used for LCD backplanes.
COM2 38 O Common output, COM0−3 are used for LCD backplanes.
COM3 39 O Common output, COM0−3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
NOTE 1: Open connection recommended for all unused analog inputs.

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
MSP430F42x Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
R13 41 I Input port of third most positive analog LCD level (V4 or V3)
R23 42 I Input port of second most positive analog LCD level (V2)
R33 43 O Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24 44 I/O General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.0/TA2/S25 45 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
P1.7/SOMI0/S26 46 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.6/SIMO0/S27 47 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28 48 I/O General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) / LCD segment output 28 (See Note 1)
P1.4/S29 49 I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30 50 I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
P1.2/TA1/S31 51 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.1/TA0/MCLK 52 I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 58 I Reset input or nonmaskable interrupt input port
P2.5/URXD0 59 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 60 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/SVSIN 61 I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
AVSS 62 Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.
DVSS 63 Digital supply voltage, negative terminal
AVCC 64 Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry; must not power up prior to DVCC.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control remains active
DLow-power mode 1 (LPM1)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ loop control is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
0FFFAh 13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFF8h 12
0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable 0FFEAh 5
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (from 0600h to 0BFFh).

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
321
rw–0 rw–0 rw–0
Address
0h URXIE0 ACCVIE NMIIE
rw–0 rw–0 rw–0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
7654 0321
Address
1h BTIE
rw-0
BTIE: Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
321
rw–0 rw–1 rw–(0)
Address
02h URXIFG0 NMIIFG
rw–1 rw–0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0321
Address
3h BTIFG
rw-0
BTIFG: Basic Timer1 interrupt flag

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
module enable registers 1 and 2
7654 0
UTXE0
321
rw–0 rw–0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0321
Address
05h
Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC.
rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.
memory organization
MSP430F423 MSP430F425 MSP430F427
Memory
Interrupt vector
Code memory
Size
Flash
Flash
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory Size 256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory Size 1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
RAM Size 256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function PM Package Pins
Data Transmit 53 - P1.0
Data Receive 52 - P1.1