Siemens C16 Series Setup guide

InstructionSetManualVersion1.2,12.97
InstructionSetManual
fortheC16xFamilyof
Siemens16-BitCMOSSingle-ChipMicrocontrollers
http://www.siemens.de/
Semiconductor/

Version 1.2, 12.97
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C166 Family Microcontroller Instruction Set Manual
Revision History: Version 1.2, 12.97
Previous Releases: Version 1.1, 09.95
03.94
Page Subjects
8 BFLD* code size corrected
35 ADDCB: spelling corrected
38 ASHR: "operation" corrected
43, 44 BFLD*: Note improved, format corrected
51 CALLI: "operation" corrected
67 EINIT: Syntax corrected
75 JBC: Condition flags corrected
77 JMPI: "operation" corrected
81 JNBS: Condition flags corrected
86, 87 MUL(U): Flag N corrected
95 PRIOR: "Operation" corrected
104 SCXT: Data Type added
108 SRVWDT: Syntax corrected
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C166 Family Instruction Set
Table of Contents
Table of Contents Page
Semiconductor Group 4 Version 1.2, 12.97
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Short Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7 Instruction State Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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C166 Family Instruction Set
Introduction
1 Introduction
The Siemens familyof 16-bit microcontrollers offers devices thatprovide various levels of peripheral
performance and programmability. This allows to equip each specific application with the
microcontroller that fits best to the required functionality and performance.
Still the Siemens family concept provides an easy path to upgrade existing applications or to climb
the next level of performance in order to realize a subsequent more sophisticated design. Two
major characteristics enable this upgrade path to save and reuse almost all of the engineering
efforts that have been made for previous designs:
• All family members are based on the same basic architecture
• All family members execute the same instructions (except for upgrades for new members)
The fact that all members execute the same instructions (almost) saves knowhow with respect to
the understanding of the controller itself and also with respect to the used tools (assembler,
disassembler, compiler, etc.).
This instruction set manual provides an easy and direct access to the instructions of the Siemens
16-bit microcontrollers by listing them according to different criteria, and also unloads the technical
manuals for the different devices from redundant information.
This manual also describes the different addressing mechanisms and the relation between the
logical addresses used in a program and the resulting physical addresses.
There is also information provided tocalculate the execution time for specificinstructions depending
on the used address locations and also specific exceptions to the standard rules.
Description Levels
In the following sections the instructions are compiled according to different criteria in order to
provide different levels of precision:
• Cross Reference Tables summarize all instructions in condensed tables
• The Instruction Set Summary groups the individual instructions into functional groups
• The Opcode Table references the instructions by their hexadecimal opcode
• The Instruction Description describes each instruction in full detail
All instructions listed in this manual are executed by the following devices (new derivatives will be
added to this list):
C161V, C161K, C161O, C161RI, C161SI, C161CI, C163, C163F, C164CI, C165, C167, C167CR,
C167SR, C167S, C167CS.
A few instructions (ATOMIC and EXTended instructions) have been added for these devices and
are not recognized by the following devices:
SAB 80C166, SAB 80C166W, SAB 83C166, SAB 83C166W, SAB 88C166, SAB 88C166W.
These differences are noted for each instruction, where applicable.

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C166 Family Instruction Set
Short Instruction Summary
2 Short Instruction Summary
The following compressed cross-reference tables quickly identify a specific instruction and provide
basic information about it. Two ordering schemes are included:
The first table (two pages) is a compressed cross-reference table that quickly identifies a specific
hexadecimal opcode with the respective mnemonic.
The second table lists the instructions by their mnemonic and identifies the addressing modes that
may be used with a specific instruction and the instruction length depending on the selected
addressing mode. This reference helps to optimize instruction sequencesin terms of code size and/
or execution time.
•0x1x2x3x4x5x6x7x
x0 ADD ADDC SUB SUBC CMP XOR AND OR
x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
x2 ADD ADDC SUB SUBC CMP XOR AND OR
x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
x4 ADD ADDC SUB SUBC - XOR AND OR
x5 ADDB ADDCB SUBB SUBCB - XORB ANDB ORB
x6 ADD ADDC SUB SUBC CMP XOR AND OR
x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
x8 ADD ADDC SUB SUBC CMP XOR AND OR
x9 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
xA BFLDL BFLDH BCMP BMOVN BMOV BOR BAND BXOR
xB MUL MULU PRIOR - DIV DIVU DIVL DIVLU
xC ROL ROL ROR ROR SHL SHL SHR SHR
xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR
xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR
xF BSET BSET BSET BSET BSET BSET BSET BSET

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C166 Family Instruction Set
Short Instruction Summary
Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailled
lists in the following sections of this manual.
Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
They are
marked in the cross-reference table.
8x 9x Ax Bx Cx Dx Ex Fx
x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV
x1 NEG CPL NEGB CPLB -
AT/EXTR MOVB MOVB
x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV
x3 -------MOVB
x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB
x5 - - DISWDT EINIT MOVBZ MOVBS - -
x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV
x7 IDLE PWRDN SRVWDT SRST -
EXTP/S/R MOVB MOVB
x8 MOV MOV MOV MOV MOV MOV MOV -
x9 MOVB MOVB MOVB MOVB MOVB MOVB MOVB -
xA JB JNB JBC JNBS CALLA CALLS JMPA JMPS
xB - TRAP CALLI CALLR RET RETS RETP RETI
xC - JMPI ASHR ASHR NOP
EXTP/S/R PUSH POP
xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR
xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR
xF BSET BSET BSET BSET BSET BSET BSET BSET

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C166 Family Instruction Set
Short Instruction Summary
1) Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rwn]!).
2) Byte oriented instructions (suffix ‘B’) use #data8 instead of #data16.
3) The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
Mnemonic Addressing ModesBytes Mnemonic Addressing ModesBytes
ADD[B]
ADDC[B]
AND[B]
OR[B]
SUB[B]
SUBC[B]
XOR[B]
Rwn Rwm 1)
Rwn [Rwi] 1)
Rwn [Rwi+] 1)
Rwn #data3 1)
reg #data16 2)
reg mem
mem reg
2
2
2
2
4
4
4
CPL[B]
NEG[B] Rwn 1) 2
DIV
DIVL
DIVLU
DIVU
Rwn 2
MUL
MULU Rwn Rwm 2
ASHR
ROL / ROR
SHL / SHR
Rwn Rwm
Rwn #data4 2 2CMPD1/2 CMPI1/2 Rwn #data4 Rwn #data16
Rwn mem
2
4
4
BAND
BCMP
BMOV
BMOVN
BOR /
BXOR
bitaddrZ.z bitaddrQ.q 4 CMP[B] Rwn Rwm 1)
Rwn [Rwi] 1)
Rwn [Rwi+] 1)
Rwn #data3 1)
reg #data16 2)
reg mem
2
2
2
2
4
4
BCLR
BSET bitaddrQ.q 2 CALLA JMPA cc caddr 4
BFLDH
BFLDL bitoffQ #mask8#data8 4 CALLI JMPI cc [Rwn] 2
MOV[B] Rwn Rwm 1)
Rwn #data4 1)
Rwn [Rwm] 1)
Rwn [Rwm+] 1)
[Rwm] Rwn 1)
[-Rwm] Rwn 1)
[Rwn] [Rwm]
[Rwn+] [Rwm]
[Rwn] [Rwm+]
reg #data16 2)
Rwn [Rwm+#d16] 1)
[Rwm+#d16] Rwn 1)
[Rwn] mem
mem [Rwn]
reg mem
mem reg
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
CALLS
JMPS seg caddr 4
CALLR rel 2
JMPR cc rel 2
JB
JBC
JNB
JNBS
bitaddrQ.q rel 4
PCALL reg caddr 4
POP
PUSH
RETP
reg 2
SCXT reg #data16
reg mem 4 4
PRIOR Rwn Rwm 2
MOVBS
MOVBZ Rwn Rbm reg mem
mem reg
2
4
4
TRAP #trap7 2
ATOMIC
EXTR #irang2 3) 2
EXTS
EXTSR Rwm #irang2 3)
#seg #irang2 2 4EXTP EXTPR Rwm #irang2 3) #pag #irang2 2 4
NOP
RET
RETI
RETS
- 2 SRST/IDLE
PWRDN
SRVWDT
DISWDT
EINIT
-4

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C166 Family Instruction Set
Instruction Set Summary
3 Instruction Set Summary
This chapter summarizes the instructions by listing them according to their functional class. This
allows to identify the right instruction(s) for a specific required function.
The following notes apply to this summary:
Data Addressing Modes
Rw: – Word GPR (R0, R1, … , R15)
Rb: – Byte GPR (RL0, RH0, …, RL7, RH7)
reg: – SFR or GPR
(in case of a byte operation on an SFR, only the low byte can be accessed via ‘reg’)
mem: – Direct word or byte memory location
[…]: – Indirect word or byte memory location
(Any word GPR can be used as indirect address pointer, except for the arithmetic,
logical and compare instructions, where only R0 to R3 are allowed)
bitaddr: – Direct bit in the bit-addressable memory area
bitoff: – Direct word in the bit-addressable memory area
#data: – Immediate constant
(The number of significant bits which can be specified by the user is represented by
the respective appendix ’x’)
#mask8: – Immediate 8-bit mask used for bit-field modifications
Multiply and Divide Operations
The MDL and MDH registers are implicit source and/or destination operands of the multiply and
divide instructions.
Branch Target Addressing Modes
caddr: – Direct 16-bit jump target address (Updates the Instruction Pointer)
seg: – Direct 2-bit segment address
(Updates the Code Segment Pointer)
rel: – Signed 8-bit jump target word offset address relative to the Instruction Pointer of the
following instruction
#trap7: – Immediate 7-bit trap or interrupt number.

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C166 Family Instruction Set
Instruction Set Summary
Extension Operations
The EXT* instructions override the standard DPP addressing scheme:
#pag10: – Immediate 10-bit page address.
#seg8: – Immediate 8-bit segment address.
Note: The EXTended instructions are not available in the SAB 8XC166(W) devices.
Branch Condition Codes
cc: Symbolically specifiable condition codes
cc_UC – Unconditional
cc_Z – Zero
cc_NZ – Not Zero
cc_V – Overflow
cc_NV – No Overflow
cc_N – Negative
cc_NN – Not Negative
cc_C – Carry
cc_NC – No Carry
cc_EQ – Equal
cc_NE – Not Equal
cc_ULT – Unsigned Less Than
cc_ULE – Unsigned Less Than or Equal
cc_UGE – Unsigned Greater Than or Equal
cc_UGT – Unsigned Greater Than
cc_SLE – Signed Less Than or Equal
cc_SGE – Signed Greater Than or Equal
cc_SGT – Signed Greater Than
cc_NET – Not Equal and Not End-of-Table

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C166 Family Instruction Set
Instruction Set Summary
Instruction Set Summary
Mnemonic Description Bytes
Arithmetic Operations
ADD Rw, Rw Add direct word GPR to direct GPR 2
ADD Rw, [Rw] Add indirect word memory to direct GPR 2
ADD Rw, [Rw +] Add indirect word memory to direct GPR and post-
increment source pointer by 2 2
ADD Rw, #data3 Add immediate word data to direct GPR 2
ADD reg, #data16 Add immediate word data to direct register 4
ADD reg, mem Add direct word memory to direct register 4
ADD mem, reg Add direct word register to direct memory 4
ADDB Rb, Rb Add direct byte GPR to direct GPR 2
ADDB Rb, [Rw] Add indirect byte memory to direct GPR 2
ADDB Rb, [Rw +] Add indirect byte memory to direct GPR and
post-increment source pointer by 1 2
ADDB Rb, #data3 Add immediate byte data to direct GPR 2
ADDB reg, #data8 Add immediate byte data to direct register 4
ADDB reg, mem Add direct byte memory to direct register 4
ADDB mem, reg Add direct byte register to direct memory 4
ADDC Rw, Rw Add direct word GPR to direct GPR with Carry 2
ADDC Rw, [Rw] Add indirect word memory to direct GPR with Carry 2
ADDC Rw, [Rw +] Add indirect word memory to direct GPR with Carry and
post-increment source pointer by 2 2
ADDC Rw, #data3 Add immediate word data to direct GPR with Carry 2
ADDC reg, #data16 Add immediate word data to direct register with Carry 4
ADDC reg, mem Add direct word memory to direct register with Carry 4
ADDC mem, reg Add direct word register to direct memory with Carry 4
ADDCB Rb, Rb Add direct byte GPR to direct GPR with Carry 2
ADDCB Rb, [Rw] Add indirect byte memory to direct GPR with Carry 2
ADDCB Rb, [Rw +] Add indirect byte memory to direct GPR with Carry and
post-increment source pointer by 1 2
ADDCB Rb, #data3 Add immediate byte data to direct GPR with Carry 2
ADDCB reg, #data8 Add immediate byte data to direct register with Carry 4
ADDCB reg, mem Add direct byte memory to direct register with Carry 4

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C166 Family Instruction Set
Instruction Set Summary
Arithmetic Operations (cont’d)
ADDCB mem, reg Add direct byte register to direct memory with Carry 4
SUB Rw, Rw Subtract direct word GPR from direct GPR 2
SUB Rw, [Rw] Subtract indirect word memory from direct GPR 2
SUB Rw, [Rw +] Subtract indirect word memory from direct GPR and
post-increment source pointer by 2 2
SUB Rw, #data3 Subtract immediate word data from direct GPR 2
SUB reg, #data16 Subtract immediate word data from direct register 4
SUB reg, mem Subtract direct word memory from direct register 4
SUB mem, reg Subtract direct word register from direct memory 4
SUBB Rb, Rb Subtract direct byte GPR from direct GPR 2
SUBB Rb, [Rw] Subtract indirect byte memory from direct GPR 2
SUBB Rb, [Rw +] Subtract indirect byte memory from direct GPR and
post-increment source pointer by 1 2
SUBB Rb, #data3 Subtract immediate byte data from direct GPR 2
SUBB reg, #data8 Subtract immediate byte data from direct register 4
SUBB reg, mem Subtract direct byte memory from direct register 4
SUBB mem, reg Subtract direct byte register from direct memory 4
SUBC Rw, Rw Subtract direct word GPR from direct GPR with Carry 2
SUBC Rw, [Rw] Subtract indirect word memory from direct GPR with Carry 2
SUBC Rw, [Rw +] Subtract indirect word memory from direct GPR with
Carry and post-increment source pointer by 2 2
SUBC Rw, #data3 Subtract immediate word data from direct GPR with Carry 2
SUBC reg, #data16 Subtract immediate word data from direct register with
Carry 4
SUBC reg, mem Subtract direct word memory from direct register with Carry 4
SUBC mem, reg Subtract direct word register from direct memory with Carry 4
SUBCB Rb, Rb Subtract direct byte GPR from direct GPR with Carry 2
SUBCB Rb, [Rw] Subtract indirect byte memory from direct GPR with Carry 2
SUBCB Rb, [Rw +] Subtract indirect byte memory from direct GPR with Carry
and post-increment source pointer by 1 2
SUBCB Rb, #data3 Subtract immediate byte data from direct GPR with Carry 2
SUBCB reg, #data8 Subtract immediate byte data from direct register with Carry 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

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C166 Family Instruction Set
Instruction Set Summary
Arithmetic Operations (cont’d)
SUBCB reg, mem Subtract direct byte memory from direct register with Carry 4
SUBCB mem, reg Subtract direct byte register from direct memory with Carry 4
MUL Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) 2
MULU Rw, Rw Unsigned multiply direct GPR by direct GPR (16-16-bit) 2
DIV Rw Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL Rw Signed long divide register MD by direct GPR (32-/16-bit) 2
DIVLU Rw Unsigned long divide register MD by direct GPR
(32-/16-bit) 2
DIVU Rw Unsigned divide register MDL by direct GPR (16-/16-bit) 2
CPL Rw Complement direct word GPR 2
CPLB Rb Complement direct byte GPR 2
NEG Rw Negate direct word GPR 2
NEGB Rb Negate direct byte GPR 2
Logical Instructions
AND Rw, Rw Bitwise AND direct word GPR with direct GPR 2
AND Rw, [Rw] Bitwise AND indirect word memory with direct GPR 2
AND Rw, [Rw +] Bitwise AND indirect word memory with direct GPR and
post-increment source pointer by 2 2
AND Rw, #data3 Bitwise AND immediate word data with direct GPR 2
AND reg, #data16 Bitwise AND immediate word data with direct register 4
AND reg, mem Bitwise AND direct word memory with direct register 4
AND mem, reg Bitwise AND direct word register with direct memory 4
ANDB Rb, Rb Bitwise AND direct byte GPR with direct GPR 2
ANDB Rb, [Rw] Bitwise AND indirect byte memory with direct GPR 2
ANDB Rb, [Rw +] Bitwise AND indirect byte memory with direct GPR
and post-increment source pointer by 1 2
ANDB Rb, #data3 Bitwise AND immediate byte data with direct GPR 2
ANDB reg, #data8 Bitwise AND immediate byte data with direct register 4
ANDB reg, mem Bitwise AND direct byte memory with direct register 4
ANDB mem, reg Bitwise AND direct byte register with direct memory 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

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C166 Family Instruction Set
Instruction Set Summary
Logical Instructions (cont’d)
OR Rw, Rw Bitwise OR direct word GPR with direct GPR 2
OR Rw, [Rw] Bitwise OR indirect word memory with direct GPR 2
OR Rw, [Rw +] Bitwise OR indirect word memory with direct GPR
and post-increment source pointer by 2 2
OR Rw, #data3 Bitwise OR immediate word data with direct GPR 2
OR reg, #data16 Bitwise OR immediate word data with direct register 4
OR reg, mem Bitwise OR direct word memory with direct register 4
OR mem, reg Bitwise OR direct word register with direct memory 4
ORB Rb, Rb Bitwise OR direct byte GPR with direct GPR 2
ORB Rb, [Rw] Bitwise OR indirect byte memory with direct GPR 2
ORB Rb, [Rw +] Bitwise OR indirect byte memory with direct GPR and
post-increment source pointer by 1 2
ORB Rb, #data3 Bitwise OR immediate byte data with direct GPR 2
ORB reg, #data8 Bitwise OR immediate byte data with direct register 4
ORB reg, mem Bitwise OR direct byte memory with direct register 4
ORB mem, reg Bitwise OR direct byte register with direct memory 4
XOR Rw, Rw Bitwise XOR direct word GPR with direct GPR 2
XOR Rw, [Rw] Bitwise XOR indirect word memory with direct GPR 2
XOR Rw, [Rw +] Bitwise XOR indirect word memory with direct GPR and
post-increment source pointer by 2 2
XOR Rw, #data3 Bitwise XOR immediate word data with direct GPR 2
XOR reg, #data16 Bitwise XOR immediate word data with direct register 4
XOR reg, mem Bitwise XOR direct word memory with direct register 4
XOR mem, reg Bitwise XOR direct word register with direct memory 4
XORB Rb, Rb Bitwise XOR direct byte GPR with direct GPR 2
XORB Rb, [Rw] Bitwise XOR indirect byte memory with direct GPR 2
XORB Rb, [Rw +] Bitwise XOR indirect byte memory with direct GPR and
post-increment source pointer by 1 2
XORB Rb, #data3 Bitwise XOR immediate byte data with direct GPR 2
XORB reg, #data8 Bitwise XOR immediate byte data with direct register 4
XORB reg, mem Bitwise XOR direct byte memory with direct register 4
XORB mem, reg Bitwise XOR direct byte register with direct memory 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

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C166 Family Instruction Set
Instruction Set Summary
Boolean Bit Manipulation Operations
BCLR bitaddr Clear direct bit 2
BSET bitaddr Set direct bit 2
BMOV bitaddr, bitaddr Move direct bit to direct bit 4
BMOVN bitaddr, bitaddr Move negated direct bit to direct bit 4
BAND bitaddr, bitaddr AND direct bit with direct bit 4
BOR bitaddr, bitaddr OR direct bit with direct bit 4
BXOR bitaddr, bitaddr XOR direct bit with direct bit 4
BCMP bitaddr, bitaddr Compare direct bit to direct bit 4
BFLDH bitoff, #mask8,
#data8 Bitwise modify masked high byte of bit-addressable direct word memory with immediate data 4
BFLDL bitoff, #mask8,
#data8 Bitwise modify masked low byte of bit-addressable direct word memory with immediate data 4
CMP Rw, Rw Compare direct word GPR to direct GPR 2
CMP Rw, [Rw] Compare indirect word memory to direct GPR 2
CMP Rw, [Rw +] Compare indirect word memory to direct GPR and
post-increment source pointer by 2 2
CMP Rw, #data3 Compare immediate word data to direct GPR 2
CMP reg, #data16 Compare immediate word data to direct register 4
CMP reg, mem Compare direct word memory to direct register 4
CMPB Rb, Rb Compare direct byte GPR to direct GPR 2
CMPB Rb, [Rw] Compare indirect byte memory to direct GPR 2
CMPB Rb, [Rw +] Compare indirect byte memory to direct GPR and
post-increment source pointer by 1 2
CMPB Rb, #data3 Compare immediate byte data to direct GPR 2
CMPB reg, #data8 Compare immediate byte data to direct register 4
CMPB reg, mem Compare direct byte memory to direct register 4
Compare and Loop Control Instructions
CMPD1 Rw, #data4 Compare immediate word data to direct GPR and
decrement GPR by 1 2
CMPD1 Rw, #data16 Compare immediate word data to direct GPR and
decrement GPR by 1 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

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C166 Family Instruction Set
Instruction Set Summary
Compare and Loop Control Instructions (cont’d)
CMPD1 Rw, mem Compare direct word memory to direct GPR and
decrement GPR by 1 4
CMPD2 Rw, #data4 Compare immediate word data to direct GPR and
decrement GPR by 2 2
CMPD2 Rw, #data16 Compare immediate word data to direct GPR and
decrement GPR by 2 4
CMPD2 Rw, mem Compare direct word memory to direct GPR and
decrement GPR by 2 4
CMPI1 Rw, #data4 Compare immediate word data to direct GPR and
increment GPR by 1 2
CMPI1 Rw, #data16 Compare immediate word data to direct GPR and
increment GPR by 1 4
CMPI1 Rw, mem Compare direct word memory to direct GPR and
increment GPR by 1 4
CMPI2 Rw, #data4 Compare immediate word data to direct GPR and
increment GPR by 2 2
CMPI2 Rw, #data16 Compare immediate word data to direct GPR and
increment GPR by 2 4
CMPI2 Rw, mem Compare direct word memory to direct GPR and
increment GPR by 2 4
Prioritize Instruction
PRIOR Rw, Rw Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR 2
Shift and Rotate Instructions
SHL Rw, Rw Shift left direct word GPR;
number of shift cycles specified by direct GPR 2
SHL Rw, #data4 Shift left direct word GPR;
number of shift cycles specified by immediate data 2
SHR Rw, Rw Shift right direct word GPR;
number of shift cycles specified by direct GPR 2
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

30Mar98@15:00h
Semiconductor Group 17 Version 1.2, 12.97
C166 Family Instruction Set
Instruction Set Summary
Shift and Rotate Instructions (cont’d)
SHR Rw, #data4 Shift right direct word GPR;
number of shift cycles specified by immediate data 2
ROL Rw, Rw Rotate left direct word GPR;
number of shift cycles specified by direct GPR 2
ROL Rw, #data4 Rotate left direct word GPR;
number of shift cycles specified by immediate data 2
ROR Rw, Rw Rotate right direct word GPR;
number of shift cycles specified by direct GPR 2
ROR Rw, #data4 Rotate right direct word GPR;
number of shift cycles specified by immediate data 2
ASHR Rw, Rw Arithmetic (sign bit) shift right direct word GPR;
number of shift cycles specified by direct GPR 2
ASHR Rw, #data4 Arithmetic (sign bit) shift right direct word GPR;
number of shift cycles specified by immediate data 2
Data Movement
MOV Rw, Rw Move direct word GPR to direct GPR 2
MOV Rw, #data4 Move immediate word data to direct GPR 2
MOV reg, #data16 Move immediate word data to direct register 4
MOV Rw, [Rw] Move indirect word memory to direct GPR 2
MOV Rw, [Rw +] Move indirect word memory to direct GPR and
post-increment source pointer by 2 2
MOV [Rw], Rw Move direct word GPR to indirect memory 2
MOV [-Rw], Rw Pre-decrement destination pointer by 2 and move direct
word GPR to indirect memory 2
MOV [Rw], [Rw] Move indirect word memory to indirect memory 2
MOV [Rw +], [Rw] Move indirect word memory to indirect memory and
post-increment destination pointer by 2 2
MOV [Rw], [Rw +] Move indirect word memory to indirect memory and
post-increment source pointer by 2 2
MOV Rw,
[Rw + #data16] Move indirect word memory by base plus constant to direct GPR 4
MOV [Rw + #data16],
Rw Move direct word GPR to indirect memory by base plus constant 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

30Mar98@15:00h
Semiconductor Group 18 Version 1.2, 12.97
C166 Family Instruction Set
Instruction Set Summary
Data Movement (cont’d)
MOV [Rw], mem Move direct word memory to indirect memory 4
MOV mem, [Rw] Move indirect word memory to direct memory 4
MOV reg, mem Move direct word memory to direct register 4
MOV mem, reg Move direct word register to direct memory 4
MOVB Rb, Rb Move direct byte GPR to direct GPR 2
MOVB Rb, #data4 Move immediate byte data to direct GPR 2
MOVB reg, #data8 Move immediate byte data to direct register 4
MOVB Rb, [Rw] Move indirect byte memory to direct GPR 2
MOVB Rb, [Rw +] Move indirect byte memory to direct GPR and
post-increment source pointer by 1 2
MOVB [Rw], Rb Move direct byte GPR to indirect memory 2
MOVB [-Rw], Rb Pre-decrement destination pointer by 1 and move
direct byte GPR to indirect memory 2
MOVB [Rw], [Rw] Move indirect byte memory to indirect memory 2
MOVB [Rw +], [Rw] Move indirect byte memory to indirect memory and
post-increment destination pointer by 1 2
MOVB [Rw], [Rw +] Move indirect byte memory to indirect memory and
post-increment source pointer by 1 2
MOVB Rb,
[Rw + #data16] Move indirect byte memory by base plus constant to direct GPR 4
MOVB [Rw + #data16],
Rb Move direct byte GPR to indirect memory by base plus constant 4
MOVB [Rw], mem Move direct byte memory to indirect memory 4
MOVB mem, [Rw] Move indirect byte memory to direct memory 4
MOVB reg, mem Move direct byte memory to direct register 4
MOVB mem, reg Move direct byte register to direct memory 4
MOVBS Rw, Rb Move direct byte GPR with sign extension to direct
word GPR 2
MOVBS reg, mem Move direct byte memory with sign extension to direct
word register 4
MOVBS mem, reg Move direct byte register with sign extension to direct
word memory 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

30Mar98@15:00h
Semiconductor Group 19 Version 1.2, 12.97
C166 Family Instruction Set
Instruction Set Summary
Data Movement (cont’d)
MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct
word GPR 2
MOVBZ reg, mem Move direct byte memory with zero extension to direct
word register 4
MOVBZ mem, reg Move direct byte register with zero extension to direct
word memory 4
Jump and Call Operations
JMPA cc, caddr Jump absolute if condition is met 4
JMPI cc, [Rw] Jump indirect if condition is met 2
JMPR cc, rel Jump relative if condition is met 2
JMPS seg, caddr Jump absolute to a code segment 4
JB bitaddr, rel Jump relative if direct bit is set 4
JBC bitaddr, rel Jump relative and clear bit if direct bit is set 4
JNB bitaddr, rel Jump relative if direct bit is not set 4
JNBS bitaddr, rel Jump relative and set bit if direct bit is not set 4
CALLA cc, caddr Call absolute subroutine if condition is met 4
CALLI cc, [Rw] Call indirect subroutine if condition is met 2
CALLR rel Call relative subroutine 2
CALLS seg, caddr Call absolute subroutine in any code segment 4
PCALL reg, caddr Push direct word register onto system stack and call
absolute subroutine 4
TRAP #trap7 Call interrupt service routine via immediate trap number 2
System Stack Operations
POP reg Pop direct word register from system stack 2
PUSH reg Push direct word register onto system stack 2
SCXT reg, #data16 Push direct word register onto system stack und update
register with immediate data 4
SCXT reg, mem Push direct word register onto system stack und update
register with direct memory 4
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes

30Mar98@15:00h
Semiconductor Group 20 Version 1.2, 12.97
C166 Family Instruction Set
Instruction Set Summary
*) The EXTended instructions are not available in the SAB 8XC166(W) devices.
Return Operations
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP reg Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
System Control
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode
(supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC #irang2 Begin ATOMIC sequence *) 2
EXTR #irang2 Begin EXTended Register sequence *) 2
EXTP Rw, #irang2 Begin EXTended Page sequence *) 2
EXTP #pag10, #irang2 Begin EXTended Page sequence *) 4
EXTPR Rw, #irang2 Begin EXTended Page and Register sequence *) 2
EXTPR #pag10, #irang2 Begin EXTended Page and Register sequence *) 4
EXTS Rw, #irang2 Begin EXTended Segment sequence *) 2
EXTS #seg8, #irang2 Begin EXTended Segment sequence *) 4
EXTSR Rw, #irang2 Begin EXTended Segment and Register sequence *) 2
EXTSR #seg8, #irang2 Begin EXTended Segment and Register sequence *) 4
Miscellaneous
NOP Null operation 2
Instruction Set Summary (cont’d)*
Mnemonic Description Bytes