Texas Instruments C2000 Piccolo LaunchPad User manual

C2000™ Microcontroller Workshop
Workshop Guide and Lab Manual
F28xMcuMdw
Revision 5.0
May 2014
Technical Training
Organization

Important Notice
ii C2000 Microcontroller Workshop - Introduction
Important Notice
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to
discontinue any product or service without notice, and advise customers to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and
complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the
extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or
represent that any license, either express or implied, is granted under any patent right, copyright, mask
work right, or other intellectual property right of TI covering or relating to any combination, machine, or
process in which such semiconductor products or services might be or are used. TI’s publication of
information regarding any third party’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
Copyright 2009 – 2014 Texas Instruments Incorporated
Revision History
September 2009 – Revision 1.0
May 2010 – Revision 2.0
December 2010 – Revision 2.1
July 2011 – Revision 3.0
September 2011 – Revision 3.1
October 2012 – Revision 4.0
May 2014 – Revision 5.0
Mailing Address
Texas Instruments
Training Technical Organization
6500 Chase Oaks Blvd Building 2
M/S 8437
Plano, Texas 75023

C2000™ Microcontroller Workshop
C2000 Microcontroller Workshop - Introduction iii
C2000™ Microcontroller Workshop
C2000™ Microcontroller Workshop
Texas Instruments
Technical Training
Copyright © 2014 Texas Instruments. All rights reserved.
C2000 is trademarks of Texas Instruments.
The objective of this workshop is to gain a fully understand and a complete working knowledge
of the C2000 microcontroller. This will be accomplished through detailed presentations and
hands-on lab exercises.
The workshop will start with the basic topics and progress to more advanced topics in a logical
flow such that each topic and lab exercise builds on the previous one presented. At the end of the
workshop, you should be confident in applying the skills learned in your product design.

C2000™ Microcontroller Workshop
iv C2000 Microcontroller Workshop - Introduction
C2000™ Microcontroller Workshop Outline
C2000™ Microcontroller Workshop Outline
1. Architecture Overview
2. Programming Development Environment Lab: Linker command file
3. Peripheral Register Header Files
4. Reset and Interrupts
5. System Initialization Lab: Watchdog and interrupts
6. Analog-to-Digital Converter Lab: Build a data acquisition system
7. Control Peripherals Lab: Generate and graph a PWM waveform
8. Numerical Concepts Lab: Low-pass filter the PWM waveform
9. Direct Memory Access (DMA) Lab: Use DMA to buffer ADC results
10. Control Law Accelerator (CLA) Lab: Use CLA to filter PWM waveform
11. Viterbi, Complex Math, CRC Unit (VCU)
12. System Design Lab: Run the code from flash memory
13. Communications
14. Support Resources
Required Workshop Materials
Required Workshop Materials
http://processors.wiki.ti.com/index.php/
C2000_Piccolo_Multi-Day_Workshop
F28069 Experimenter’s Kit (TMDXDOCK28069)
Install Code Composer Studio v6.0.0
Run the workshop installer
C2000 Microcontroller Workshop-5.0-Setup.exe
Lab Files / Solution Files
Student Guide and Documentation
The materials required for this workshop are available using the links shown at the top of this
slide. An F28069 Experimenter’s Kit and a jumper wire will be needed for the lab exercises. The

C2000™ Microcontroller Workshop
C2000 Microcontroller Workshop - Introduction v
lab directions are written based on the version of Code Composer Studio as shown on this slide.
The workshop installer will automatically install the lab files, solution files, workshop manual,
and documentation.
C2000™ Experimenter Kit
C2000™ Experimenter Kit
controlCARD
USB Docking Station
The development tool for this workshop will be the TMS320F28069 Experimenter’s Kit. The kit
consists of a controlCARD and USB Docking Station. It is a self-contained system that plugs
into a free USB port on your computer. The USB port provides power, as well as communicates
to the onboard JTAG emulation controller. LED LD1 on the Docking Station and LED LD1 on
the controlCARD illuminates when the board is powered. LED LD2 on the controlCARD is
connected to GPIO34. We will be using this LED as a visual indicator during the lab exercises.
The GPIO and ADC lines from the F28069 device are pinned out to the Docking Station headers.
We will be using a jumper wire to connect various GPIO and ADC lines on these headers.

C2000™ Microcontroller Workshop
vi C2000 Microcontroller Workshop - Introduction
C2000 Delfino / Piccolo Comparison
C2000 Delfino / Piccolo Comparison
F2833x F2803x F2806x
Clock
150 MHz 60 MHz 90 MHz
Flash / RAM
128Kw / 34Kw 64Kw / 10Kw 128Kw / 50Kw
On
-chip Oscillators - 2 2
VREG / POR / BOR
- 
Watchdog
Timer 
12
-bit ADC SEQ -based SOC -based SOC -based
Analog COMP
w/ DAC - 
FPU
-
6
-Channel DMA -
CLA
- 
VCU
- - 
ePWM
/ HR ePWM /   /   / 
eCAP
/ HR eCAP / -/ -/ 
eQEP

SCI / SPI / I2C

LIN
--
McBSP
-
USB
- - 
External Interface
- -
When comparing the Delfino and Piccolo product lines, you will notice that the Piccolo F2806x
devices share many features with the Delfino product line. The Delfino product line is shown in
the table by the F2833x column; therefore, the F28069, being the most feature-rich Piccolo
device, was chosen as the platform for this workshop. The knowledge learned from this device
will be applicable to all C2000 product lines.

C2000 Microcontroller Workshop - Architecture Overview 1 - 1
Architecture Overview
Introduction
This architectural overview introduces the basic architecture of the C2000™ Piccolo™ series of
microcontrollers from Texas Instruments. The Piccolo™ series adds a new level of general
purpose processing ability unseen in any previous DSP/MCU chips. The C2000™ is ideal for
applications combining digital signal processing, microcontroller processing, efficient C code
execution, and operating system tasks.
Unless otherwise noted, the terms C28x, F28x and F2806x refer to TMS320F2806x devices
throughout the remainder of these notes. For specific details and differences please refer to the
device data sheet and user’s guide.
Module Objectives
When this module is complete, you should have a basic understanding of the F28x architecture
and how all of its components work together to create a high-end, uniprocessor control system.
Module Objectives
Review the F28x block diagram and
device features
Describe the F28x bus structure and
memory map
Identify the various memory blocks on
the F28x
Identify the peripherals available on
the F28x

Module Topics
1 - 2 C2000 Microcontroller Workshop - Architecture Overview
Module Topics
Architecture Overview...............................................................................................................................1-1
Module Topics..........................................................................................................................................1-2
What is the TMS320C2000™?.................................................................................................................1-3
TMS320C2000™ Internal Bussing .....................................................................................................1-4
F28x CPU + FPU + VCU and CLA........................................................................................................1-5
Special Instructions..............................................................................................................................1-6
Pipeline Advantage..............................................................................................................................1-7
F28x CPU + FPU + VCU Pipeline......................................................................................................1-8
Memory....................................................................................................................................................1-9
Memory Map.......................................................................................................................................1-9
Code Security Module (CSM)...........................................................................................................1-10
Peripherals.........................................................................................................................................1-10
Fast Interrupt Response.........................................................................................................................1-11
Summary ................................................................................................................................................1-12

What is the TMS320C2000™?
C2000 Microcontroller Workshop - Architecture Overview 1 - 3
What is the TMS320C2000™?
The TMS320C2000™ is a 32-bit fixed point microcontroller that specializes in high performance
control applications such as, robotics, industrial automation, mass storage devices, lighting,
optical networking, power supplies, and other control applications needing a single processor to
solve a high performance application.
TMS320F2806x Block Diagram
Sectored
Flash
Program Bus
Data Bus
RAM
Boot
ROM
3
32-bit
Timers
PIE
Interrupt
Manager
eQEP
Watchdog
I2C
SCI
SPI
GPIO
eCAP
CLA
CAN 2.0B
12-bit ADC
CLA Bus
32x32 bit
Multiplier
CPU
Register Bus
R-M-W
Atomic
ALU
FPU
VCU
DMA
6 Ch.
DMA Bus
McBSP
ePWM
USB 2.0
This block diagram represents an overview of all device features and is not specific to any one
device. The F28069 device is designed around a multibus architecture, also known as a modified
Harvard architecture. This can be seen in the block diagram by the separate program bus and data
bus, along with the link between the two buses. This type of architecture greatly enhances the
performance of the device.
In the upper left area of the block diagram, you will find the memory section, which consists of
the boot ROM, sectored flash, and RAM. Also, you will notice that the six-channel DMA has its
own set of buses.
In the lower left area of the block diagram, you will find the execution section, which consists of
a 32-bit by 32-bit hardware multiplier, a read-modify-write atomic ALU, a floating-point unit,
and a Viterbi complex math CRC unit. The control law accelerator coprocessor is an independent
and separate unit that has its own set of buses.
The peripherals are grouped on the right side of the block diagram. The upper set is the control
peripherals, which consists of the ePWM, eCAP, eQEP, and ADC. The lower set is the
communication peripherals and consists of the multichannel buffered serial port, I2C, SCI, SPI,
CAN, and USB.
The PIE block, or Peripheral Interrupt Expansion block, manages the interrupts from the
peripherals. In the bottom right corner is the general-purpose I/O. Also, the CPU has a watchdog
module and three 32-bit general-purpose timers available.

What is the TMS320C2000™?
1 - 4 C2000 Microcontroller Workshop - Architecture Overview
TMS320C2000™ Internal Bussing
As with many DSP-type devices, multiple busses are used to move data between the memories
and peripherals and the CPU. The F28x memory bus architecture contains:
•A program read bus (22-bit address line and 32-bit data line)
•A data read bus (32-bit address line and 32-bit data line)
•A data write bus (32-bit address line and 32-bit data line)
Program-read Data Bus (32)
F28x CPU Internal Bus Structure
Data-write Address Bus (32)
Program Address Bus (22)
Execution
R-M-W
Atomic
ALU
Real-Time
JTAG
Emulation
Program
Decoder
PC
XAR0
to
XAR7
SP
DP @X
ARAU MPY32x32
XT
P
ACC
ALU
Registers Debug
Register Bus / Result Bus
Data/Program-write Data Bus (32)
Data-read Address Bus (32)
Data-read Data Bus (32)
FPU
R0H-R7H
Program
Memory
Data
Memory
Peripherals
VCU
VR0-VR8
CLA
MR0-MR3
The 32-bit-wide data busses provide single cycle 32-bit operations. This multiple bus
architecture, known as a Harvard Bus Architecture, enables the F28x to fetch an instruction, read
a data value and write a data value in a single cycle. All peripherals and memories are attached to
the memory bus and will prioritize memory accesses.

F28x CPU + FPU + VCU and CLA
C2000 Microcontroller Workshop - Architecture Overview 1 - 5
F28x CPU + FPU + VCU and CLA
The F28x is a highly integrated, high performance solution for demanding control applications.
The F28x is a cross between a general purpose microcontroller and a digital signal processor,
balancing the code density of a RISC processor and the execution speed of a DSP with the
architecture, firmware, and development tools of a microcontroller.
The DSP features include a modified Harvard architecture and circular addressing. The RISC
features are single-cycle instruction execution, register-to-register operations, and a modified
Harvard architecture. The microcontroller features include ease of use through an intuitive
instruction set, byte packing and unpacking, and bit manipulation.
F28x CPU + FPU + VCU and CLA
MCU/DSP balancing code density &
execution time
 16-bit instructions for improved code density
 32-bit instructions for improved execution time
32-bit fixed-point CPU + FPU
32x32 fixed-point MAC, doubles as dual
16x16 MAC
IEEE Single-precision floating point
hardware and MAC
Floating-point simplifies software
development and boosts performance
Viterbi, Complex Math, CRC Unit (VCU)
adds support for Viterbi decode, complex
math and CRC operations
Parallel processing Control Law Accelerator
(CLA) adds IEEE Single-precision 32-bit
floating point math operations
CLA algorithm execution is independent of
the main CPU
Fast interrupt service time
Single cycle read-modify-write instructions
Unique real-time debugging capabilities
Data Bus
3
32-bit
Timers
CPU
Register Bus
Program Bus
32x32 bit
Multiplier
R-M-W
Atomic
ALU CLA
CLA Bus
FPU
VCU
PIE
Watchdog
The F28x design supports an efficient C engine with hardware that allows the C compiler to
generate compact code. Multiple busses and an internal register bus allow an efficient and
flexible way to operate on the data. The architecture is also supported by powerful addressing
modes, which allow the compiler as well as the assembly programmer to generate compact code
that is almost one to one corresponded to the C code.
The F28x is as efficient in DSP math tasks as it is in system control tasks. This efficiency
removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of
the F28x and its 64-bit processing capabilities, enable the F28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive solution. Along
with this is the capability to perform two 16 x 16-bit multiply accumulate instructions
simultaneously or Dual MACs (DMAC). Also, some devices feature a floating-point unit.
The, F28x is source code compatible with the 24x/240x devices and previously written code can
be reassembled to run on a F28x device, allowing for migration of existing code onto the F28x.

F28x CPU + FPU + VCU and CLA
1 - 6 C2000 Microcontroller Workshop - Architecture Overview
Special Instructions
F28x Atomic Read/Modify/Write
Registers ALU / MPY
LOAD
STORE
WRITE
READ
CPU
Mem
Atomic Instructions Benefits
Simpler programming
Smaller, faster code
Uninterruptible (Atomic)
More efficient compiler
AND *XAR2,#1234h
2 words / 1 cycles
Atomic Read/Modify/Write
MOV AL,*XAR2
AND AL,#1234h
MOV *XAR2,AL
DINT
EINT
6 words / 6 cycles
Standard Load/Store
Atomics are small common instructions that are non-interuptable. The atomic ALU capability
supports instructions and code that manages tasks and processes. These instructions usually
execute several cycles faster than traditional coding.

F28x CPU + FPU + VCU and CLA
C2000 Microcontroller Workshop - Architecture Overview 1 - 7
Pipeline Advantage
F
1
F
2
D
1
D
2
R
1
R
2
E
F28x CPU Pipeline
Protected Pipeline
Order of results are as written in
source code
Programmer need not worry about
the pipeline
8-stage pipeline
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
F
1
F
2
D
1
D
2
R
1
R
2
E
A
B
C
D
E
F
G
W
W
W
W
W
W
W
W
E & G Access
same address
R
1
R
2
E W
D
2
R
1
R
2
E W
F1: Instruction Address
F2: Instruction Content
D1: Decode Instruction
D2: Resolve Operand Addr
R1: Operand Address
R2: Get Operand
E: CPU doing “real” work
W: store content to memory
H
The F28x uses a special 8-stage protected pipeline to maximize the throughput. This protected
pipeline prevents a write to and a read from the same location from occurring out of order.
This pipelining also enables the F28x to execute at high speeds without resorting to expensive
high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.

F28x CPU + FPU + VCU and CLA
1 - 8 C2000 Microcontroller Workshop - Architecture Overview
F28x CPU + FPU + VCU Pipeline
F28x CPU + FPU + VCU Pipeline
Floating Point Unit and VCU has an unprotected pipeline
 i.e. FPU/VCU can issue an instruction before previous instruction has
written results
Compiler prevents pipeline conflicts
Assembler detects pipeline conflicts
Performance improvement by placing non-conflicting
instructions in floating-point pipeline delay slots
F
1
F
2
D
1
D
2
R
1
R
2
EW
F28x Pipeline
Fetch Decode Read Exe Write
Floating-point math operations, conversions between integer and floating-
point formats, and complex MPY/MAC require 1 delay slot –everything else
does not require a delay slot (load, store, max, min, absolute, negative, etc.)
LoadStore
0 delay slot instruction
1 delay slot instruction
D R E
1
E
2
/W
VCU Instruction
D R E
1
E
2
/W
FPU Instruction
Floating-point and VCU operations are not pipeline protected. Some instructions require delay
slots for the operation to complete. This can be accomplished by insert NOPs or other non-
conflicting instructions between operations.
In the user’s guide, instructions requiring delay slots have a ‘p’ after their cycle count. The 2p
stands for 2 pipelined cycles. A new instruction can be started on each cycle. The result is valid
only 2 instructions later.
Three general guideslines for the FPU/VCU pipeline are:
Math MPYF32, ADDF32,
SUBF32, MACF32,
VCMPY
2p cycles
One delay slot
Conversion I16TOF32, F32TOI16,
F32TOI16R, etc… 2p cycles One delay slot
Everything else* Load, Store, Compare,
Min, Max, Absolute and
Negative value
Single cycle
No delay slot
* Note: MOV32 between FPU and CPU registers is a special case.

Memory
C2000 Microcontroller Workshop - Architecture Overview 1 - 9
Memory
The memory space on the F28x is divided into program memory and data memory. There are
several different types of memory available that can be used as both program memory and data
memory. They include the flash memory, single access RAM (SARAM), OTP, and Boot ROM
which is factory programmed with boot software routines and standard tables used in math related
algorithms.
Memory Map
The F28x CPU contains no memory, but can access memory on chip. The F28x uses 32-bit data
addresses and 22-bit program addresses. This allows for a total address reach of 4G words (1
word = 16-bits) in data memory and 4M words in program memory. Memory blocks on all F28x
designs are uniformly mapped to both program and data space.
This memory map shows the different blocks of memory available to the program and data space.
TMS320F28069 Memory Map
0x000000
0x000400
0x000800
M1 SARAM (1Kw)
M0 SARAM (1Kw)
Data Program
PIE Vectors
(256 w)
PF 0 (6Kw) reserved
PF 3 (4Kw)
PF 1 (4Kw)
L0 DPSARAM (2Kw)
L1 DPSARAM (1Kw)
L2 DPSARAM (1Kw)
L3 DPSARAM (4Kw)
0x000D00
0x002000
0x005000
0x006000
0x008000
0x008800
0x008C00
0x00A000
0x000E00
0x009000
reserved
Data Program
FLASH (128Kw)
PASSWORDS (8w)
0x3D7CC0
0x3D7C80
0x3D8000
Boot ROM (32Kw)
0x3F7FF8
0x3F8000
0x3FFFFF
CSM Protected:
L0, L1, L2, L3, L4,
OTP, FLASH,
ADC CAL,
Flash Regs in PF0
0x3FFFC0
BROM Vectors (64w)
ADC / OSC cal. data
DPSARAM L0, L1, L2 & L3
accessible by CPU & CLA
PF 2 (4Kw)
0x007000
0x014000
0x3D7800
0x3D7C00
User OTP (1Kw)
reserved
reserved
L4 SARAM (8Kw)
L5 DPSARAM (8Kw)
L6 DPSARAM (8Kw)
L7 DPSARAM (8Kw)
0x00C000
0x00E000
0x012000
0x010000
L8 DPSARAM (8Kw)
0x014000
DPSARAM L5, L6, L7 & L8
accessible by DMA
The F28069 utilizes a contiguous memory map, also known as a von-Neumann architecture. This
type of memory map lends itself well to higher-level languages. This can be seen by the labels
located at the top of the memory map where the memory blocks extend between both the data
space and program space.
At the top of the map, we have two blocks of RAM called M0 and M1. Then we see PF0 through
PF3, which are the peripheral frames. This is the area where you will find the peripheral
registers. Also in this space, you will find the PIE block. Memory blocks L0 through L8 are
grouped together. L0 through L3 are accessible by the CPU and CLA. L5 through L8 are
accessible by the DMA.

Memory
1 - 10 C2000 Microcontroller Workshop - Architecture Overview
The user OTP is a one-time, programmable, memory block. TI reserves a small space in the map
for the ADC and oscillator calibration data. The flash block contains a section for passwords,
which are used by the code security module. The boot ROM and boot ROM vectors are located
at the bottom of the memory map.
Code Security Module (CSM)
Code Security Module
 Prevents reverse engineering and protects
valuable intellectual property
128-bit user defined password is stored in Flash
128-bits = 2
128
= 3.4 x 10
38
possible passwords
To try 1 password every 8 cycles at 80 MHz, it would
take at least 1.1 x 10
24
years to try all possible
combinations!
L0 DPSARAM (2Kw)
L1 DPSARAM (1Kw)
L2 DPSARAM (1Kw)
L3 DPSARAM (4Kw)
User OTP (1Kw)
ADC / OSC cal. data
reserved
reserved
FLASH (128Kw)
PASSWORDS (8w)
reserved
0x008000
0x008800
0x008C00
0x00A000
0x009000
0x3D7800
0x3D7C00
0x3D7C80
0x3D7CC0
0x3D8000
0x3F7FF8
0x3F8000
L4 DPSARAM (8Kw)
0x00C000
Peripherals
The F28x comes with many built in peripherals optimized to support control applications. These
peripherals vary depending on which F28x device you choose.
•ePWM •SPI
•eCAP •SCI
•eQEP •I2C
•Analog-to-Digital Converter •McBSP
•Watchdog Timer •eCAN
•CLA
•DMA
•USB
•GPIO

Fast Interrupt Response
C2000 Microcontroller Workshop - Architecture Overview 1 - 11
Fast Interrupt Response
The fast interrupt response, with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. F28x implements a
zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature
helps reduces the interrupt service routine overheads.
F28x Fast Interrupt Response Manager
96 dedicated PIE
vectors
No software decision
making required
Direct access to RAM
vectors
Auto flags update
Concurrent auto
context save
28x CPU Interrupt logic
28x
CPU
INTM
96
Peripheral Interrupts 12x8 = 96
12 interrupts
INT1 to
INT12
PIE
Register
Map
PIE module
For 96
interrupts
TST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)
Auto Context Save
IFR IER
The C2000 devices feature a very fast interrupt response manager using the PIE block. This
allows up to 96 possible interrupt vectors to be processed by the CPU. More details about this
will be covered in the reset, interrupts, and system initialization modules.

Summary
1 - 12 C2000 Microcontroller Workshop - Architecture Overview
Summary
Summary
 High performance 32-bit CPU
32x32 bit or dual 16x16 bit MAC
IEEE single-precision floating point unit (FPU)
Hardware Control Law Accelerator (CLA)
Viterbi, complex math, CRC unit (VCU)
Atomic read-modify-write instructions
Fast interrupt response manager
128Kw on-chip flash memory
Code security module (CSM)
Control peripherals
12-bit ADC module
Comparators
Direct memory access (DMA)
Up to 54 shared GPIO pins
Communications peripherals

C2000 Microcontroller Workshop - Programming Development Environment 2 - 1
Programming Development Environment
Introduction
This module will explain how to use Code Composer Studio (CCS) integrated development
environment (IDE) tools to develop a program. Creating projects and setting building options
will be covered. Use and the purpose of the linker command file will be described.
Module Objectives
Module Objectives
Use Code Composer Studio to:
 Create a Project
Set Build Options
Create a user linker command file which:
 Describes a system’s available memory
Indicates where sections will be placed
in memory

Module Topics
2 - 2 C2000 Microcontroller Workshop - Programming Development Environment
Module Topics
Programming Development Environment...............................................................................................2-1
Module Topics..........................................................................................................................................2-2
Code Composer Studio ............................................................................................................................2-3
Software Development and COFF Concepts.......................................................................................2-3
Code Composer Studio........................................................................................................................2-4
Edit and Debug Perspective (CCSv6)..................................................................................................2-5
Target Configuration ...........................................................................................................................2-6
CCSv6 Project.....................................................................................................................................2-7
Creating a New CCSv6 Project ...........................................................................................................2-8
CCSv6 Build Options – Compiler / Linker .........................................................................................2-9
CCSv6 Debug Environment..............................................................................................................2-10
Creating a Linker Command File..........................................................................................................2-12
Sections..............................................................................................................................................2-12
Linker Command Files (.cmd).........................................................................................................2-15
Memory-Map Description.................................................................................................................2-15
Section Placement..............................................................................................................................2-16
Summary: Linker Command File ......................................................................................................2-17
Lab File Directory Structure..................................................................................................................2-18
Lab 2: Linker Command File.................................................................................................................2-19