WinSystems EBC-LP User manual

OPERATIONS MANUAL
EBC-LP
WinSystems reserves the right to make changes in the circuitry
and specifications at any time without notice.
Copyright 2003 by WinSystems. All Rights Reserved.
NOTE: This manual has been designed and created for use as part of the WinS
y
stems’ Technical Manuals
CD and/or the WinSystems’ website. If this manual or any portion of the manual is downloaded, co
p
ied or
emailed, the links to additional information (i.e. software, cable drawings) will be inoperable.

REVISION HISTORY
P/N 403-0306-000B
ECO Number Date Code Rev Level
ORIGINATED 030110 B
03-59 030530 B1

TABLE OF CONTENTS
Section Paragraph Title Page
Visual Index – Quick Reference i
1 General Information 1-1
1.1 Features 1-1
1.2 General Description 1-1
1.3 Specifications 1-2
2 EBC-LP Technical Reference 2-1
2.1 Introduction 2-1
2.2 Intel FW82439TX Chipset 2-1
2.3 CPU Speed Selection 2-2
2.4 Memory Installation 2-3
2.5 Interrupt Routing 2-3
2.6 Power/Reset Connections 2-4
2.7 Mouse Interface 2-4
2.8 Real Time Clock/Calendar 2-5
2.9 Keyboard Interface 2-5
2.10 Serial Interface 2-6
2.11 Parallel Printer Port 2-13
2.12 Speaker/Sound Interface 2-14
2.13 PC/104 Interface 2-14
2.14 PC/104-Plus Bus Interface 2-15
2.15 Floppy Interface 2-16
2.16 IDE Hard Disk Interface 2-16
2.17 Watchdog Timer Configuration 2-17
2.18 Status LED 2-18
2.19 Battery Selection Control 2-18
2.20 DiskOnChip Configuration 2-18
2.21 Parallel I/O 2-19
2.22 VGA Configuration 2-22
2.23 Flat Panel Output Connection 2-24
2.24 Ethernet Controller 2-25
2.25 Fan Power Connector 2-25
2.26 Multi-I/O Connector 2-26
2.27 USB Connector 2-26

Section Paragraph Title Page
3 Award BIOS Configuration 3-1
3.1 General Information 3-1
3.2 Entering Setup 3-1
3.3 Setup Main Menu 3-1
3.4 Standard CMOS Setup 3-2
3.5 BIOS Features Setup 3-7
3.6 Chipset Features Setup 3-11
3.7 Power Management 3-14
3.8 PnP/PCI Configuration 3-19
3.9 Load BIOS Defaults 3-20
3.10 Load Setup Defaults 3-21
3.11 Password Setting 3-21
3.12 IDE HDD Auto Detection 3-21
3.13 Save & Exit Setup 3-21
3.14 Exit without Saving 3-21
4 DiskOnChip Configuration 4-1
4.1 DiskOnChip Usage 4-1
5 WS16C48 Programming Reference 5-1
5.1 Introduction 5-1
5.2 Function Definitions 5-1
5.3 Sample Programs 5-6
APPENDIX A I/O Port Map
APPENDIX B Interrupt Map
APPENDIX C EBC-LP Mechanical Drawing
APPENDIX D WS16C48 I/O Routines and Sample Program Listings
APPENDIX E Cable Drawings and Software Drivers & Examples
Warranty and Repair Information

Visual Index – Quick Reference
Connectors
For the convenience of the user, a copy of the Visual Index has been provided with direct
links to connector and jumper configuration data.
i EBC-LP OPERATIONS MANUAL 030530
J1 RJ45 EthernetJ2 J3
FP/100
J4 VGA Video
J7 Fan Power
J9
PC/104 Plus
J8
Flat Panel Power
J15 J16
PC/104
J17
Interrupt Routing
Header
J18
Power Reset
J19 J20
Parallel I/O
J23 Mouse
J25
COM3/COM4
I/O
J32 USB
J28
Floppy Drive
J29
Primary
Hard Drive
J30
Secondary
Hard Drive
J27 Multi I/O

Visual Index – Quick Reference
For the convenience of the user, a copy of the Visual Index has been provided with direct
links to connector and jumper configuration data.
ii EBC-LP OPERATIONS MANUAL 030530
J5
Panel Backlight Enable
J6
CPU Configuration
J10
Master Battery
Selection
J11 J12
COM1
Configuration
J13 J14
COM2
Configuration
J21
COM3/4 Enable
J22
DiskOnChip
Address Selection
J24
DiskOnChip
Enable
J26
Parallel I/O VCC
Selection
J31
Parallel I/O
Selection

1General Information
1.1 Features
nIntel Pentium 166MMX or 266MMX CPU
nPC Compatible uses Intel 430TX chip set
nEBX-compliant board
n512KB of pipeline burst L2 cache
nUp to 256MB of SDRAM
nSocket for up to 288MB bootable DiskOnChip or DIP
socket for BIOS extension support of Flash or ROM
nOn board high resolution video controller with CRT on
nFlat panel video support
nSupports resolutions up to 1280 x 1024
nSimultaneous CRT and LCD operation
nPC/104-Plus and PC/104 expansion buses
n10/100 Mbps Ethernet using Intel 82559
n4 RS-232 serial ports with FIFO, COM1 & COM2
supports optional RS-422/485/J1708 support
nBi-directional LPT port supports EPP/ECP
n48 bi-directional TTL digital I/O lines
nUSB support
1.2 General Description
The EBC-LP is a small, high-performance, embeddable computer system on a single board. It
integrates a number of popular I/O options including VGA, Ethernet, Solid-State Disk, and High-
Density Parallel I/O. Four PC compatible serial ports are standard, as are the floppy, hard disk, and
parallel printer interfaces. The EBC-LP is populated with either an Intel Pentium 166MMX or Intel
Pentium 266MMX processor. Up to 256Mbytes of user installable DIMM memory is supported.
512KB of pipeline burst, level two cache is also standard. A full 16-bit PC/104 expansion bus is
provided for further expansion to an entire industry of add-on peripherals including sound and speech
modules, SCSI controllers, analog I/O modules, and literally hundreds of other options available from
WinSystems and a variety of vendors supporting the PC/104 and PC/104-Plus standards. An onb oard
32-pin silicon disk socket supports the M-Systems DiskOnChipFlashmodulesinsizesranging from 8
Megabytes to 288 Megabytes.
030530 EBC-LP OPERATIONS MANUAL Page 1-1

1.3 Specifications
1.3.1 Electrical
Bus Interface : PC/104 8-Bit or 16-Bit expansion bus
PC/104-Plus 32-bit expansion bus
System Clock : 66MHz
Interrupts : TTL Level input
VCC : +5V +/- 5% at 1.6A typical with an Intel Pentium 166MMX
processor with 32Mb SDRAM
+5V +/- 5% at 2.0A typical with an Intel Pentium 266MMX
processor with 32Mb SDRAM
VCC1 : +12V +/-5% (Not required. PC/104 Expansion, Flat Panel, use only)
VCC2 : -12V +/-5% (Not required. PC/104 Expansion or Flat Panel use only)
VCC3 : 3.3V (Not required. PC/104-Plus Expansion only)
1.3.2 Memory
Addressing : 256 Megabyte addressing
BIOS ROM : 128K Flash
Memory DIMM Socket : 168-pin 3.3V Dimm Module; PC-66 or PC-100 SDRAM Module.
SSD Memory : One 32-pin JEDEC standard socket supporting the M-Systems 32-Pin DOC
(DiskOnChip) module.
1.3.3 Mechanical
Dimensions : 5.75 X 8.0 (without PC/104 modules or cables)
PC-Board : FR4 Epoxy Glass with 5 signal layers and 3 power planes with screened
component legend and plated through holes.
Jumpers : 0.025" square posts on 0.100" centers
Connectors : Multi I/O : 50-pin RN type IDH-50LP
COM3/COM4 : 20-pin RN type IDH-20LP
Floppy Disk : 34-pin RN type IDH-34-LP
Page 1-2EBC-LP OPERATIONS MANUAL 030530
WinSystems - "The Embedded Authority"

CRT : 14-pin 2mm Molex Type 87331-1420
Flat Panel : Two, 50-pin 2mm Molex type 87331-5020
Power/Reset : 9-pin in-line Molex type 26-60-7091
Fan Power : 3-pin in-line Molex type 22-11-2032
Mouse : 5-pin in-line latching Molex type 22-11-2052
USB : 4-pin in-line latching Molex type 22-11-2042
PC/104 Bus : 64-Pin SAMTEC type ESQ-132-12-G-D
40-Pin SAMTEC type ESQ-120-12-G-D
PC/104-Plus Bus : 120-Pin SAMTEC type TS-30-Q
IDE : Two 40-pin 2mm Molex Type 70246-4021
1.3.4 Environmental :
Operating Temperature : -40°to +85°C using Pentium 166 MHz
-40°to +60°C using Pentium 266 MHz
Non-condensing relative humidity : 5% to 95%
030530 EBC-LP OPERATIONS MANUAL Page 1-3
WinSystems - "The Embedded Authority"

2EBC-LP Technical Reference
2.1 Introduction
Thissectionofthemanualisintendedtoprovidesufficientinformationregardingtheconfiguration
and usage of the EBC-LP board. WinSystems maintains a Technical Support group to help answer
questions regarding configuration, usage, or programming of the board. For answers to questions not
adequately addressed in this manual, contact Technical Support at [phone] between 8AM and
5PM Central Time.
2.2 Intel FW82439TX Chipset
The EBC-LP utilizes the Intel FW82439TX Chipset which provides a highly-integrated, high-
performance backbone for full Pentium class compatibility. The Chipset contains the logic for DRAM
and bus state control as well as the standard complement of 'AT' class peripherals, including :
Two-82C37 DMA controllers
Two-82C59 Interrupt controllers
82C54 Timer/Counter
Real Time Clock
Enhanced Power Management
Full Plug and Play compatibility
These functional units are 100% PC/AT compatible and are supported by the Award BIOS and
setup. Users desiring to access these internal peripherals directly should refer to any manufacturers
generic literature on the equivalent discrete component.
There are a number of internal registers within the Intel TX chipset that are used by the BIOS for
control and configuration. Refer to the I/O map in Appendix A for port usage to avoid conf licts when
adding external I/O devices.
030530 EBC-LP OPERATIONS MANUAL Page 2-1

2.3 CPU Speed Selection
The EBC-LP uses a crystal controlled frequency synthesizer to control the base CPU clock
frequency.TheprocessorsavailablefromWinSystemsandthejumperingforthemareshownbelow.
Page 2-2EBC-LP OPERATIONS MANUAL 030530
WinSystems - "The Embedded Authority"
3 2 1
o o o
J6
CPU Speed Select
Jumper J6
3 2 1
o o o
J6
3 2 1
o o o
J6
Pentium 166MHz MMX Pentium 266MHz MMX

2.4 Memory Installation
The EBC-LP supports a single, user-installable 168-pin standard DIMM. DIMM modules should
be a minimum speed of PC-66 or PC-100 and x64 as there is no support for the parity or ECC bits
provided by x72 bit modules. A single DIMM socket is provided which can support SDRAM sizes
from32MBto256MB.ForalistofqualifiedDIMMs,gotohttp://www.winsystems.com/memory.
Installation is accomplished with power off by inserting the DIMM module directly into the
connector at M1. The DIMM module is keyed in 2 places and cannot be inserted backwards witho ut
extreme force. The module is inserted until the retaining clips snap into place. Removal is the reverse
process. Push down on the retaining clips, moving them outward. The DIMM module, once released,
will be forced up to an appropriate removal position.
2.5 Interrupt Routing
All interrupts on the EBC-LP are routed to their respective PC/104 bus pins. Onboard non-PnP
peripherals,arerouted totheirtypical usageinterruptsusingthejumperblockatJ17.Thisblockallows
disconnecting or rerouting of the onboard interrupts. The layout for the J17 header and the default
jumper settings are shown below.
030530 EBC-LP OPERATIONS MANUAL Page 2-3
WinSystems - "The Embedded Authority"
21 19 17 15 13 11 9 7 5 3 1
o o o o o o o o o o o
o o o o o o o o o o o
22 20 18 16 14 12 10 8 6 4 2 J17 Interrupt Routing Header
22 o o 21
20 o o 19
18 o o 17
16 o o 15
14 o o 13
12 o o 11
10 o o 9
8 o o 7
6 o o 5
4 o o 3
2 o o 1
J17
COM4
16C48
COM3
COM4
SECONDARYHD
PRIMARYHD
NC
NC
COM3
NC
NC
IRQ9
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
IRQ6
IRQ7
IRQ5
IRQ4
IRQ3

2.6 Power/Reset Connections
Power is applied to the EBC-LP via the connectoratJ18(Molexpartnumber26-60-7091).Thepin
definitionsforJ18aregivenbelow.Anoptionalpush-button-reset(NormallyOpen)mayalsobe routed
into J18 if desired. Momentary closure to ground forces a hardware reset.
2.7 Mouse Interface
A PS/2 mouse may be attached via the connector at J23. An adapter cable, CBL-225-1, is available
fromWinSystemstoadapttoaconventionalPS/2mouseconnector. ThepinoutforJ23isshownhere.
Page 2-4EBC-LP OPERATIONS MANUAL 030530
WinSystems - "The Embedded Authority"
J18
o1
o2
o3
o4
o5
o6
o7
o 8
o9 o 1
o2
o3
o4
o5
J23
J18
o 1
o 2
o3
o 4
o 5
o6
o7
o8
o9
+5V
GND
GND
+12V
+3.3V
GND
+5V
-12V
PB Reset
1 o
2 o
3 o
4 o
5 o
J23
MSDATA
N/C
GND
VCC
MSCLK

2.8 Real Time Clock/Calendar
The EBC-LP contains an onboard Clock/Calendar within the PIIX4E chip. This clock is fully
compatible with the MC146818A used in the original PC-AT computers. This clock has a number of
features including periodic and alarm interrupt capabilities. In addition to the time and date keeping
functions, the system configurationiskept withintheCMOS RAMcontainedintheclocksection.This
RAM holds all of the setup information regarding hard and floppy disk types, video type, shadowing,
wait states, etc. Refer to the section on the Award BIOS Setup for what is configured via the CMOS
RAM.
ItmaybecomenecessaryatsometimetomaketheCMOSRAMforgetitscurrentconfigurationand
tostartfreshwithfactorydefaults.Thismaybeaccomplishedbyremovingpowerfromtheboard . Then
remove the jumper from pins 2-3 on J10 and place on pins 1-2 for 10 seconds. Replace the jumper on
J10 pins 2-3, power-up, and reconfigure the CMOS settings as desired.
2.9 Keyboard Interface
The EBC-LP contains an onboard PS/2 style keyboard controller. Keyboard connection is made
through the Multi-I/O connector at J27. An adapter cable P/N CBL-247-1 is available from
WinSystems to make ready access to all of the devices terminated at the Multi-I/O connector. Users
desiring custom connections should refer to the Multi-I/O connector pin definitions given later in this
manual.
030530 EBC-LP OPERATIONS MANUAL Page 2-5
WinSystems - "The Embedded Authority"
3 2 1
o o o
J10
Master Battery
Select Jumper J10

2.10 Serial Interface
The EBC-LP provides four 16550 compatible RS-232 serial ports at the following addresses :
COM1 3F8H at IRQ 4 (PnP Device)
COM2 2F8H at IRQ 3 (PnP Device)
COM3 3E8H* at IRQ 5**
COM4 2E8H* at IRQ 9**
*COM ports 3 and 4 can be enabledordisabledindividually via the jumper block at J21. When J21
pins 1-2 are jumpered, COM3 is enabled. When J21 pins 3-4 are jumpered, COM4 is enabled.
**The interrupts are not disconnected when COM3 or COM4 are disabled. Use the interrupt
routing block J17 described earlier to disconnect the default interrupts if desired.
Page 2-6EBC-LP OPERATIONS MANUAL 030530
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3 o o 1
4 o o 2
J21
U25 U24U26
1 o
2 o
3 o
J11 o o o
3 2 1 J12
U28 U30U29
1 o
2 o
3 o
J13 o o o
3 2 1 J14

The two primary serial ports, COM1 and COM2 are configurable for RS-422, RS-485 or J1708,
withtheadditionofoptionaldriverICs.Theconfigurationoptionsforeachofthesupported modes are
shown on the following pages. Connection to COM1 and COM2 is made through the Multi-I/O
connector at J27. An adapter cable (P/N CBL-247-1) is available from WinSystems’ to adapt to
standard DB9 connectors.
COM1 - RS-232
COM2 - RS-232
COM3/COM4 - RS-232
COM3 and COM4 are RS-232 only and are terminated at J25. An adapter cable is available from
WinSystems (P/N CBL-173-1), which adapts J25 to two standard DB9M connectors. The pin
definitions for J25 are shown here :
030530 EBC-LP OPERATIONS MANUAL Page 2-7
WinSystems - "The Embedded Authority"
3 2 1
o o o 1 2 3 o o o
U24 - Installed
U25 - Not Installed
U26 - Not Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J11 J12
COM1 DB9
CD
RX Data
TX Data
DTR
GND
DSR
RTS
CTS
RI
3 2 1
o o o 1 2 3 o o o
U28 - Installed
U29 - Not Installed
U30 - Not Installed
J13 J14
COM2 DB9
CD
RX Data
TX Data
DTR
GND
DSR
RTS
CTS
RI
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
COM3 DCD
COM3 RX
COM3 TX
COM3 DTR
GND
COM4 DCD
COM4 RX
COM4 TX
COM4 DTR
GND
COM3 DSR
COM3 RTS
COM3 CTR
COM3 RI
N/C
COM4 DSR
COM4 RTS
COM4 CTS
COM4 RI
N/C
J25

2.10.1 RS-422 Mode Configuration
RS-422 levels are supported on both COM1 and COM2 with the installation of the optional “Chip
Kit”, WinSystems part number CK-75176-2. This kit provides the driver ICs necessary for a sing le
channel of RS-422. If two channels of RS-422 are required then two kits will be needed. RS-422 is a
4-wirepoint-to-pointfull-duplexinterfaceallowingmuchlongercablerunsthanarepossible with RS-
232. The differential transmitter and receiver twisted pairs offer a high degree of noise immunity. RS-
422 usually requires the lines be terminated at both ends. This termination can be accomplished either
on the cable or by installing resisters on the board in locations reserved for them. The method for
determining the correct resistor valuesisbeyondthescopeofthisdocumentbutitisrecommendedthat
trial values of 100 ohms be used in all three locations at the receiver end. The following illustration
shows the correct mode jumpering, driver IC installation, I/O connector pin definitions, and
termination resistor locations for each of the channels when used in RS-422 mode.
COM1 - RS-422
* Important Note: All serial termination
components are surface mount 0805 packages. These should only be installed by surface mount
qualified individuals.
Page 2-8EBC-LP OPERATIONS MANUAL 030530
WinSystems - "The Embedded Authority"
3 2 1
o o o 1 2 3 o o o
U24 - Not Installed
U25 - Installed
U26 - Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J11 J12
COM1 DB9
N/C
TX+
TX-
N/C
GND
RX+
RX-
N/C
N/C
VCC
R17
R14
R11
RX+
RX-
RS-422 NOTE : When used in RS-422 mode,
thetransmittermustbeenabledbysettingtheRTS
bit in the Modem Control Register (Bit1).

COM2 - RS-422
Important Note: All serial termination components are surface mount 0805 packages. These
should only be installed by surface mount qualified individuals.
2.10.2 RS-485 Mode Configuration
The RS-485 Multi-dropinterfaceissupportedonbothchannelswiththeinstallationoftheoptional
“Chip Kit”, WinSystems’ part number CK-75176-2. A single kit is sufficient to configure both
channels for RS-485. RS-485 is a 2-wire multi-drop interface where only one station at a time talks
(transmits) while all others listen (receive). RS-485 usually requires the twisted pair be terminated at
each end of the run. The requiredterminationvaluesaredependentuponanumberoffactorsincluding:
line impedance, line length, etc. A good trial value is 100 ohms in all three resistor locations. The
following illustrations show the correct jumpering, driver IC installation, I/O connector pinout, and
termination resistor locations for each of the channels when used in RS-485 mode.
030530 EBC-LP OPERATIONS MANUAL Page 2-9
WinSystems - "The Embedded Authority"
3 2 1
o o o 1 2 3 o o o
U28 - Not Installed
U29 - Installed
U30 - Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J13 J14
COM2 DB9
N/C
TX+
TX-
N/C
GND
VCC
R29
R31
R32
RX+
TX-
RS-422 NOTE: When used in RS-422 mode,
the transmitter must be enabled by setting the RTS
bit in the Modem Control Register (Bit1).
RX+
RX-
N/C
N/C

COM1 - RS-485
Important Note: All serial termination components are surface mount 0805 packages. These
should only be installed by surface mount qualified individuals.
Page 2-10 EBC-LP OPERATIONS MANUAL 030530
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3 2 1
o o o 1 2 3 o o o
U24 - Not Installed
U25 - Installed
U26 - Not Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J11 J12
COM1 DB9
N/C
TX/RX+
TX/RX-
N/C
GND
N/C
N/C
N/C
N/C
VCC
R17
R14
R11
TX/RX+
TX/RX-
RS-485 NOTE : Because RS-485 uses a single
twisted-pair, all transmitters are connected in
parallel. Only one station at a time may transmit or
have its transmitter enabled. The transmitter
Enable/Disable is controlled in software using bit 1
intheModemControlRegister(RTS).WhenRTSis
set, the transmitter is enabled,andwhencleared(the
normal state) the transmitter is disabled and the
receiverisenabled.Notethatitisnecessarytoallow
some minimal settling time after enabling the
transmitter before transmitting the first character.
Likewise, following a transmission, it is necessary
to be sure that all characters have been completely
shifted out of the UART (Check Bit 6 in the Line
Status Register) before disabling the transmitter to
avoid chopping off the last character.

COM2 - RS-485
ImportantNote: Allserialterminationcomponents aresurfacemount0805 packages.These
should only be installed by surface mount qualified individuals.
2.10.3 SAE J1708 Configuration
The Society of Automotive Engineers (SAE) J1708 interface is a variation of the RS-485 interface
which is used for “Serial Data Communications between Microcomputer Systems in Heavy Duty
Vehicle Applications”. It is beyond the scope of this document to go into detail on the J1708
specification.TheEBC-LPmaybeuserconfiguredforJ1708bytheadditionoftheCK-75176-2 “Chip
Kit”. One “Chip Kit” is sufficient to configure both channels for J1708. The illustrations that follow
show the correct jumpering, driver IC installation, I/O connector pin definitions, and the termination
network details for each of the channels when used in J1708 mode.
030530 EBC-LP OPERATIONS MANUAL Page 2-11
WinSystems - "The Embedded Authority"
3 2 1
o o o 1 2 3 o o o
U28 - Not Installed
U29 - Installed
U30 - Not Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J13 J14
COM2 DB9
N/C
TX/RX+
TX/RX-
N/C
GND
N/C
N/C
N/C
N/C
VCC
R29
R31
R32
TX/RX+
TX/RX-
RS-485 NOTE : Because RS-485 uses a single
twisted-pair, all transmitters are connected in
parallel. Only one station at a time may transmit or
have its transmitter enabled. The transmitter
Enable/Disable is controlled in software using bit 1
intheModemControlRegister(RTS).WhenRTSis
set, the transmitter is enabled,andwhencleared(the
normal state) the transmitter is disabled and the
receiverisenabled.Notethatitisnecessarytoallow
some minimal settling time after enabling the
transmitter before transmitting the first character.
Likewise, following a transmission, it is necessary
to be sure that all characters have been completely
shifted out of the UART (Check Bit 6 in the Line
Status Register) before disabling the transmitter to
avoid chopping off the last character.