Xilinx ML365 Virtex-II Pro QDR II SRAM M User manual

R
ML365 Virtex-II Pro
QDR II SRAM (200 MHz)
Memory Board User Guide
UG066 (v1.0) June 29, 2004
Product Not Recommended for New Designs

ML365 Virtex-II Pro QDR II SRAM Mem. Board www.xilinx.com UG066 (v1.0) June 29, 2004
1-800-255-7778
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ML365 Virtex-II Pro QDR II SRAM Memory Board User Guide
UG066 (v1.0) June 29, 2004)
The following table shows the revision history for this document.
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Version Revision
06/29/04 1.0 Initial Xilinx Release
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UG066 (v1.0) June 29, 2004 1-800-255-7778
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Preface
About This Guide
This document describes the design of the ML365 Virtex-II Pro™ QDR II SRAM (200 MHz)
Memory Board, which connects a Virtex-II Pro FPGA to Quad Data Rate (QDR) memories.
Guide Contents
This manual contains the following chapters:
•Chapter 1, “Introduction,” describes the purpose of the ML365 board and provides its
key features.
•Chapter 2, “Architecture,” provides a block diagram of the memory board and
describes the key components.
•Chapter 3, “Electrical Requirements,” lists the electrical specifications for the memory
board.
•Chapter 4, “Signal Integrity Recommendations and Simulations,” provides
information on termination, transmission lines, and duty cycles. It also gives the
results of several IBIS simulations.
•Chapter 5, “Board Layout Guidelines,” provides information on decoupling
capacitors, ground signals, and PCB layout.
•Appendix 1, “Related Documentation,” lists data sheet and external website
references specific to the ML365 components.
•Appendix 2, “FPGA Pinout,” provides the pinout of the Virtex-II Pro FPGA.
•Appendix 3, “Memory Board Schematics and Characterization Results” shows the
schematics for the board.
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists
some of the resources you can access from this website. You can also directly access these
resources using the provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to
verification and debugging:
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser Database of Xilinx solution records:
http://support.xilinx.com/xlnx/xil_ans_browser.jsp
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UG066 (v1.0) June 29, 2004 1-800-255-7778
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Online Document
The following conventions are used in this document:
Application Notes Descriptions of device-specific design techniques and approaches:
http://support.xilinx.com/apps/appsweb.htm
Data Sheets Device-specific information on Xilinx device characteristics,
including readback, boundary scan, configuration, length count,
and debugging:
http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Problem Solvers Interactive tools that allow you to troubleshoot your design issues:
http://support.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips Latest news, design tips, and patch information for the Xilinx
design environment:
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
Resource Description/URL
Convention Meaning or Use Example
Italic font
References to other manuals See the Development System Reference Guide for more
information.
Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol,
the two nets are not connected.
Convention Meaning or Use Example
Blue text Cross-reference link to a location in the current
document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.
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UG066 (v1.0) June 29, 2004 1-800-255-7778
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1: Introduction
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2: Architecture
ML365 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
QDR II SRAM (U5, Banks 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
QDR II SRAM (U11, Banks 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
QDR II SRAM (U12, Banks 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RS232 (J5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
200 MHz LVPECL Clock (Y1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
250 MHz LVPECL Clock (Y2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SMA Clock Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
GPIO (P19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DIP Switch (SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Push Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power On or Off Slide Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Grounded I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Liquid Crystal Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Cycle for the LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Display Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table of Contents
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2.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.8 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Selecting the Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Slave Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SystemAce Configuration (Default Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SelectMap Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 3: Electrical Requirements
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 4: Signal Integrity Recommendations and Simulations
Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Terminations and Transmission Lines for QDR Components . . . . . . . . . . . . . . . . 34
Data and Clock Signals (D, Q, CQ, CQ, and CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Address and Control Signals (A, R, W, BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IBIS Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Notes on the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Signals from the FPGA to the Memory (HSTL_18_C2 at FPGA) . . . . . . . . . . . . 37
Data Signals from the QDR II SRAM, Component U11 to the FPGA Measured at the FPGA39
Eye Diagram for the Component U11, Bit 4 Signal Measured at the FPGA . . . . . . . . 40
Clock Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical, Slow, and Fast Cases for Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address and Control Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical Case Simulation at All Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 5: Board Layout Guidelines
Decoupling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Providing Additional Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Board Stackup Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Appendix 1: Related Documentation
Appendix 2: FPGA Pinout
Appendix 3: Memory Board Schematics and Characterization Results
Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Long-Term Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Corners Results Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Chapter 1: Introduction
Figure 1-1: Simplified Block Diagram of Memory Board Interface. . . . . . . . . . . . . . . . . . 11
Chapter 2: Architecture
Figure 2-1: ML365 Board Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2-2: LCD Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2-3: Display Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2-4: LCD Panel Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2-5: SelectMap Connectors P99 and P111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-6: SystemAce and JTAG Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2-7: JTAG I/O Connector P103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 3: Electrical Requirements
Chapter 4: Signal Integrity Recommendations and Simulations
Figure 4-1: Signal Terminations for Transmitted and Received Data. . . . . . . . . . . . . . . . 36
Figure 4-2: Data Signal Bit 4 from the FPGA to the Memory (Typical Case). . . . . . . . . . 37
Figure 4-3: Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM, U11 . . . . 38
Figure 4-4: Data Signals from the QDR II SRAM U11 at the FPGA (Typical,
Slow/Weak and Fast/Strong Cases) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 4-5: Eye Diagram for Data Bit 4 at the FPGA from Component U11. . . . . . . . . . . 40
Figure 4-6: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 4-7: Clock K Signal from the FPGA to the QDR II SRAM, Component U11 . . . 42
Figure 4-8: Clock CQ Signal from the FPGA to the QDR II SRAM Component U11 . . 43
Figure 4-9: Address and Control Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-10: Address/Control Signals for the QDR II SRAM, Component U11, Bit 4 . . 45
Chapter 5: Board Layout Guidelines
Figure 5-1: Picture of the Top Layer of the ML365 Revision 1.0b Board. . . . . . . . . . . . . . 50
Figure 5-2: Picture of the Bottom Layer of the ML365 Revision 1.0b Board. . . . . . . . . . . 51
Appendix 1: Related Documentation
Appendix 2: FPGA Pinout
Appendix 3: Memory Board Schematics and Characterization Results
Schedule of Figures
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Chapter 1: Introduction
Chapter 2: Architecture
Table 2-1: GPIO Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2-2: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-3: Power-On Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-4: FPGA Configuration Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-5: SystemAce Configuration Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-6: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2-7: LCD Pin Descriptions and PFGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2-8: LCD Write Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2-9: Instruction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2-10: Configuration Modes Supported on the QDR II SRAM Demonstration Board 24
Table 2-11: Jumper Positions for SystemAce Configuration . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2-12: JTAG Connector Pins (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 3: Electrical Requirements
Table 3-1: ML365 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3-2: XC2VP20FF1152 Estimated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3-3: XC2VP20FF1152 Temperature Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3-4: Device Quiescent Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3-5: CLB Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3-6: Digital Clock Manager Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3-7: Input/Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 4: Signal Integrity Recommendations and Simulations
Table 4-1: QDR SRAM Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 5: Board Layout Guidelines
Table 5-1: Decoupling Capacitor Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5-2: Suggested Stackup for a 12-layer board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Appendix 1: Related Documentation
Appendix 2: FPGA Pinout
Table 2-1: FPGA Pin Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix 3: Memory Board Schematics and Characterization Results
Table 3-1: Corners Results Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Schedule of Tables
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Chapter 1
Introduction
Overview
The ML365 Virtex-II Pro QDR II SRAM Memory Board provides a communications
platform between a Virtex-II Pro FPGA and high-speed, quad data-rate (QDR) memories
with operating speeds up to 200 MHz. The ML365 has three major functions:
•Test and verify the interoperability of Virtex-II Pro devices with high-speed QDR II
SRAM memories
•Serve as a development platform for Xilinx and its customers to use for building
memory interfaces
•Provide a means by which Xilinx can demonstrate high-speed QDR II SRAM memory
interoperability
This document describes the functional blocks within the ML365. It also provides various
recommendations and requirements for usage of the board, including electrical
requirements, logic analyzer requirements, and signal integrity issues. Simulation results
using IBIS also are included.
Figure 1-1 shows a simplified block diagram of the ML365 memory interfaces.
Figure 1-1: Simplified Block Diagram of Memory Board Interface
ug124_01_062204
QDR II SRAM
1M x 36
FBGA 165
4-Word Burst
QDR II SRAM
1M x 36
FBGA 165
4-Word Burst
Virtex-II Pro FPGA
XC2VP20FF1152-6
QDR II SRAM
1M x 36
FBGA 165
4-Word Burst
D
(36-bits)
Q
(36-bits)
Addr,
Ctrl
Q (36-bits)
D (36-bits)
K, K
C, C
CQ, CQ
Addr, Ctrl
Q (36-bits)
D (36-bits)
K, K
C, C
CQ, CQ
Addr, Ctrl
C,
C
K,
K
CQ,
CQ
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The ML365 demonstrates a 36-bit interface to a 36 MByte, 200 MHz QDR II SRAM
component. There are three independent 36-bit interfaces on the board; one on the left side
of the FPGA, the second on the right side of the FPGA, and the third on top of the FPGA.
Features
The key features of the ML365 are summarized as follows:
•One Virtex-II Pro FPGA (XC2VP20FF1152)
•Three QDR II SRAM Components (Samsung K7R323684M or NEC UPD44165364F5)
♦18 MBytes
♦36-bit Data interface
•Three separate controllers for each 36-bit memory interface
•Characterized 200 MHz clock operation for interfaces A (interface to the FPGA on the
right side, U5) and B (interface to the FPGA on the left side, U11)
•One additional memory interface on the top banks of the FPGA (interface C, U12)
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Chapter 2
Architecture
This chapter provides functional descriptions of the major blocks within the ML365 board
design. For additional detailed information on the design, refer to the schematics, which
are located at http://www.xilinx.com/bvdocs/userguides/ug066.zip.
ML365 Board Block Diagram
Figure 2-1 shows a block diagram of the ML365 board. Refer to “Block Descriptions” for
additional information on the major blocks.
Figure 2-1: ML365 Board Block Diagram
ug066_c2_01_060804
FPGA
Reset
PROG
Mode
DIP
SW QDR II SRAM
1M x 36
QDR II SRAM
1M x 36
QDR II SRAM
1M x 36
USER2
Switch
USER1
Switch
USER2
LED
USER1
LED
SystemAce
Reset
JTAG
Header
JTAG
Parallel
PC-IV
Port
JTAG
Jumpers
SystemAce
File Select
Rotary Switch
SYSTEM ACE
Controller
TQFP144
SEIKO 1X16
LCD Display
L167100J000
XC2VP20
FF1152C
SelectMap
Header
Clock
250 MHz
Clock
200 MHz
RS-232
Serial
Port
GPIO Header
TPS54810
1.8V, 8A
Regulator
PT5501N
3.3V, 3A
Regulator
PT5502N
2.5V, 3A
Regulator
PT5505N
1.5V, 3A
Regulator
On / Off
Switch
DC 5V
Input Jack
SMA SMA
XCONFIG
Header
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Chapter 2: Architecture
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Block Descriptions
This section describes the major blocks of the ML365 board.
FPGA
The ML365 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged
in a 1152-pin BGA package with a -6 speed grade. Refer to Appendix 2, “FPGA Pinout,”for
a complete pinout of the Virtex-II Pro device.
Memories
The ML365 board supports three types of memories in two speed grades.
QDR II SRAM (U5, Banks 6 and 7)
The QDR II SRAM component connected to FPGA I/O banks 6 and 7 is a 165-pin, 200 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM in a Ball Grid Array package. This
component has a 36-bit wide data interface.
QDR II SRAM (U11, Banks 2 and 3)
The QDR II SRAM component connected to FPGA I/O banks 2 and 3 is a 165-pin, 200 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide
data interface.
QDR II SRAM (U12, Banks 0 and 1)
The QDR II SRAM component connected to FPGA I/O banks 0 and 1 is a 165-pin, 250 MHz
Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide
data interface.
RS232 (J5)
The ML365 board provides an RS232 serial interface using a Maxim MAX3316ECUP
device. The maximum speed of this device is 460 Kb/s. The RS232 interface is accessible
through a male DB9 serial connector.
Clocks
The ML365 board has 200 MHz and 250 MHz LVPECL (2.5 V) clock oscillators on board. It
also has two SMA connectors for external differential clock inputs.
200 MHz LVPECL Clock (Y1)
The LVPECL clock is an Epson EG-2121CA-200 MHz oscillator with a differential output.
The oscillator runs at 200 MHz ±100 PPM with an operating voltage of 2.5 V ±5%. It is
terminated at the FPGA with a 50 ohm resistor. FPGA pins AH17 and AJ17 in Bank 4 serve
as the OSC_200M_N and OSC_200M_P inputs, respectively.
250 MHz LVPECL Clock (Y2)
The LVPECL clock is an Epson EG-2121CA-250 MHz clock oscillator with a differential
output. This oscillator runs at 250 MHz ±100 PPM with an operating voltage of 2.5 V ±5%.
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Block Descriptions R
FPGA pins AK17 and AL17 in Bank 4 serve as the OSC_250M_N and OSC_250M_P inputs,
respectively.
SMA Clock Connectors
Two SMA connectors are provided for the input of an off-board differential clock. The
traces from the SMAs are run as a pair to the FPGA where they are terminated with a
50 ohm resistor. AK18 serves as the EXTCLK1_P input, and AL18 serves as the
EXTCLK1_N input for the SMA connector pair.
User I/Os
This subsection describes the devices that connect to the User I/Os of the ML365 board.
GPIO (P19)
The ML365 board contains 16 General-Purpose I/Os (GPIOs) that are accessible through a
2 x 16 .100" pin header (P19). The odd-numbered pins on each header are connected to an
FPGA pin, and the even-numbered pins on each header are connected to GND (refer to
Table 2-1). The GPIO header pins are accessed through I/Os in Bank 0. The header pins
each have a pull-down resistor of 51 ohms.
Table 2-1: GPIO Header Pins
GPIO Header Pin # FPGA I/O Pin GPIO Header Pin #
Ground Connections
G1 AL13 G2
G3 AL12 G4
G5 AD16 G6
G7 AE16 G8
G9 AM14 G10
G11 AM13 G12
G13 AF16 G14
G15 AG16 G16
G17 AH15 G18
G19AJ15G20
G21AD17G22
G23 AE17 G24
G25 AH16 G26
G27AJ16G28
G29AK16G30
G31 AF17 G32
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Chapter 2: Architecture
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DIP Switch (SW3)
One 3-position DIP switch (SW3) is connected to the FPGA I/O as shown in Table 2-2.
These switches are used to set the FPGA configuration mode pins M0, M1, and M2.
LEDs
Eleven surface-mounted blue LEDs are installed as status indicators. Refer to Table 2-3,
Table 2-4, and Table 2-5.
Table 2-2: DIP Switch Connections
DIP Switch Input FPGA I/O Pin #
DIP1 AF26 (M0)
DIP2 AE26 (M1)
DIP3 AE25 (M2)
Table 2-3: Power-On Status
Status Indication FPGA I/O Pin #
5.0V on D9
2.5V on D7
3.3V on D5
1.8V on D8
1.5V on D6
Table 2-4: FPGA Configuration Status
Configuration INIT D3
Configuration DONE D4
Table 2-5: SystemAce Configuration Status
System Ace LEDs Error D2
Status D1
User LEDs USER1 AF15
USER2 AE15
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Push Buttons
The ML365 board contains five momentary push buttons. Their functions are as follows:
•Program the FPGA
•Reset FPGA
•Reset SystemAce
•USER1
•USER2
Rotary Switch
The ML365 board contains one eight-position rotary switch used to select the SystemAce
file address. One of eight configuration file images is loaded from the Compact Flash card
present in the socket.
Power On or Off Slide Switch
The power on or off slide switch is a DPST slide switch used to apply 5V input power to the
board.
Jumper Settings
Table 2-6 lists the jumper settings for the complete PCB.
Grounded I/Os
Unused I/Os are connected to GND in all FPGA banks. This was done to improve power
dissipation and SSO ground bounce. Users must not drive any unused I/Os that are
connected to GND.
Table 2-6: Jumper Settings
Pin # Purpose
Jumper Position
1 - 2 2 - 3
P6 QDR II U5 DLL enable DLL enable DLL bypass
P7 QDR II U5 ZQ select Minimum Z mode 0.2RQ = 50 ohm
P20 QDR II U11 DLL enable DLL enable DLL bypass
P21 QDR II U11 ZQ select Minimum Z mode 0.2RQ = 50 ohm
P22 QDR II U12 DLL enable DLL enable DLL bypass
P23 QDR II U12 ZQ select Minimum Z mode 0.2RQ = 50 ohm
P2 System Ace On = Disable after reset
Off = Enable after reset
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Chapter 2: Architecture
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Liquid Crystal Display
The Seiko L167100J000 Liquid Crystal Display (LCD) is a 5V, 1-line X16 character display
without a backlight. The LCD is connected to the PCB using two rows of 1 x 16 pin SIP
headers placed 31 mm. apart. The LCD interfaces uses bank 5 of the FPGA. The LCD pin
descriptions and FPGA pinouts are listed in Table 2-7.
The information needed to control the LCD panel is provided in the following figures and
tables. Figure 2-2 shows the LCD write timing diagram, and Table 2-8 lists the LCD write
timing parameters.
Table 2-9 shows the instruction codes for the LCD. Figure 2-3 shows the Display
Initialization Sequence, and Figure 2-7, the LCD panel character set. For complete
information, refer to the manufacturer’s data sheet.
Write Cycle for the LCD
Reading from the LCD panel memory is not implemented on this demonstration board.
Table 2-7: LCD Pin Descriptions and PFGA Connections
Symbol Function FPGA Pin #
VSS Power supply (GND) N/A
VDD Power supply (+5V) N/A
VOContrast adjustment N/A
RS Register selection AF22
R/W Read / Write selection AG22
E Read / Write enable AE22
DB (0-7) Data bus AF25 (DB0),AL28,AM28, AE24,
AF24, AG25, AH25, AK27 (DB7)
Figure 2-2: LCD Write Timing Diagram
RS
R / W
E
DB[7:0]
tAS
tER tEF
tDSW tH
tCYCE
tAH
PWEH
ug066_c2_02_060704
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Display Commands
Table 2-9 provides display commands or instruction code for the LCD. Refer to the Table
Notes for additional information.
Table 2-8: LCD Write Timing Parameters
Item Symbol
Standard
Unit
Minimum Maximum
Enable cycle time tCYCE500 ns
Enable pause width / High Level PWEH 230 ns
Enable rise and fall time tER, tEF 20 ns
Address setup time / RS, R/W - E tAS 40 ns
Address hold time tAH 10 ns
Data setup time tDSW 80 ns
Data hold time tH10 ns
Table 2-9: Instruction Code
Instruction Code Description
(Notes 2 and 3)
Maximum
Execution
Time
(Note 1)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Display
000000 0 0 0 1Clearsentiredisplayandsets
Data Display RAM (DDR)
address 0 in the address
counter.
82 µs -
1.64 ms
Return
Home
000000 0 0 1 *SetsDDRaddress0inthe
address counter. Also returns
display being shifted to
original position. DDR
contents remain unchanged.
40 µs -
1.6 ms
Entry
Mode
Set
000000 0 1I/DSSetscursormovedirection
and specifies shift of display.
These operations are
performed during data write
and read.
40 µs –
1.64 ms
Display
On/Off
Control
000000 1 D CBSetsON/OFFofentire
display (D), cursor ON/OFF
(C), and blink of cursor
position character (B).
40 µs
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*Not applicable
Notes:
1.Maximum execution time is when fcp or fosc is 250 kHz. Execution time changes when frequency
changes.
2.DD RAM: Display data RAM
CG RAM: Character generator RAM
ACG: CG RAM address
ADD: DDR address - corresponds to cursor address
AC: Address counter used for both DDR and CG RAM address
I/D = 1: Increment or I/D = 0: Decrement
S = 1: Display shift or S = 0: No Display shift
D=1:DisplayONorD=0:DisplayOFF
C = 1: Cursor ON or C = 0: Cursor OFF
B = 1: Blink ON or B = 0: Blink OFF
S/C = 1: Display shift or S/C = 0: Cursor move
R/L = 1: Shift to the right or R/L = 0: Shift to the left
DL = 1: 8 bits or DL = 0: 4 bits
N=1:2lines
F=0:5x7 dots
BF = 1: Internally operating or BF = 0: Can accept instruction
Cursor or
Display
Shift
000001S/CR/L* *Movescursorandshifts
display without changing
DDR contents.
40 µs
Function
Set
00001DLN F * *Setsinterfacedatalength(DL),
number of display lines (L),
and character fonts (F).
40 µs
Set
CG RAM
Address
0001 A
CC Sets Character Generator
RAM (CGR) address. CGR
data is sent and received after
this setting.
40 µs
Set
DD RAM
Address
00 1 A
DD Sets DDR address. CGR data
is sent and received after this
setting.
40 µs
Read
Busy Flag
and
Address
01BF A
CReads Busy flag (BF)
indicating internal operation
is being performed and reads
address counter contents.
1µs
Write Data
to CG
or DDR
1 0 Write Data Writes data into DDR or CGR. 40 µs
Table 2-9: Instruction Code
Instruction Code Description
(Notes 2 and 3)
Maximum
Execution
Time
(Note 1)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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