ZiLOG Z80 series User manual
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User Manual
Z80 Family
CPU User Manual
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This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Table of Contents
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This user manual describes the architecture and instruction set of the Z80
CPU.
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ZiLOG recommends that the user read and understand everything in this
manual before setting up and using the product. However, we recognize
that users have different styles of learning: some will want to set up and
use their new evaluation kit while they read about it; others will open
these pages only to check on a particular specification. Therefore, we
have designed this manual to be used either as a how to procedural
manual or a reference guide to important data.
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This document is written for ZiLOG customers who are experienced at
working with microprocessors or in writing assembly code or compilers.
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The Z80 CPU User’s Manual is divided into four chapters.
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Presents an overview of the User’s Manual Architecture, Pin descriptions,
timing and Interrupt Response.
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Presents examples of the User’s Manual hardware and software.
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Presents the User’s Manual instruction types, addressing modes and
instruction Op Codes.
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Presents an overview of the User’s Manual assenbly language, status
indicator flags and the Z80 instructions.
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The following assumptions and conventions are adopted to provide clarity
and ease of use:
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The words set and clear imply that a register bit or a condition contains
the values logical 1 and logical 0, respectively. When either of these
terms is followed by a number, the word logical may not be included, but
it is implied.
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A field of bits within a register is designated as: Register (n–n). For
example: PWM_CR (31–20). A field of bits within a bus is designated as:
Busn–n. For example: PCntl7–4. A range of similar (whole) registers is
designated as: Registern–Registern. For example: OPBCS5–OPBCS0.
Part Number Title DC number
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In this document, the terms LSB and MSB, when appearing in upper case,
mean least significant byte and most significant byte, respectively. The
lowercase forms, msb and lsb, mean least significant bit and most
significant bit, respectively.
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Commands, code lines and fragments, register (and other) mnemonics,
values, equations, and various executable items are distinguished from
general text by the use of the Courier font. This convention is not used
within tables. For example: The STP bit in the CNTR register must be 1.
Where the use of the font is not possible, as in the Index, the name of the
entity is presented in upper case.
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Hexadecimal values are designated by a uppercase Hand appear in the
Courier typeface. For example: STAT is set to F8H.
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The use of all uppercase letters designates the names of states and
commands. For example: The receiver can force the SCL line to Low to
force the transmitter into a WAIT state. The bus is considered BUSY after
the Start condition. A START command triggers the processing of the
initialization sequence.
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Initial uppercase letters designate settings, modes, and conditions in
general text. For example: The Slave receiver leaves the data line High. In
Transmit mode, the byte is sent most significant bit first. The Master can
generate a Stop condition to abort the transfer.
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Register access is designated by the following abbreviations:
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Z80, Z180, Z380 and Z80382 are trademarks of ZiLOG, Inc.
Designation Description
R Read Only
R/W Read/Write
WWriteOnly
–Unspecified or indeterminate
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The ZiLOG Z80 CPU family of components are fourth-generation
enhanced microprocessors with exceptional computational power. They
offer higher system throughput and more efficient memory utilization
than comparable second- and third-generation microprocessors. The
speed offerings from 6–20 MHz suit a wide range of applications which
migrate software. The internal registers contain 208 bits of read/write
memory that are accessible to the programmer. These registers include
two sets of six general purpose registers which may be used individually
as either 8-bit registers or as 16-bit register pairs. In addition, there are
two sets of accumulator and flag registers.
The Z80 CPU also contains a Stack Pointer, Program Counter, two index
registers, a REFRESH register, and an INTERRUPT register. The CPU is
easy to incorporate into a system since it requires only a single +5V
power source. All output signals are fully decoded and timed to control
standard memory or peripheral circuits; the Z80 CPU is supported by an
extensive family of peripheral controllers.
Figure 1 illustrates the internal architecture and major elements of the
Z80 CPU.
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The Z80 CPU contains 208 bits of R/W memory that are available to the
programmer. Figure 2 illustrates how this memory is configured to
eighteen 8-bit registers and four 16-bit registers. All Z80 registers are
implemented using static RAM. The registers include two sets of six
general-purpose registers that may be used individually as 8-bit registers
or in pairs as 16-bit registers. There are also two sets of accumulator and
flag registers and six special-purpose registers.
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