ZiLOG Z80380 User manual

DC-8297-03
PREFACE
Thank you for your interest in the Z380
™
Central Processing Unit (CPU) and its
associated family of products. This Technical Manual describes programming
and operation of the Z380
™
Superintegration
™
Core CPU, which is found in the
Z380 Microprocessor Unit (MPU), and products built around Z380
™
CPU core.
This Z380 User's Manual consists of the following Sections:
1. Z380™Architectural Overview
Chapter 1 is an introductory section covering the key features and
giving an overview of the architecture of the device.
2. Address Spaces
Chapter 2 explains the address spaces the Z380 CPU can handle.
Also, this chapter includes a brief description of the on-chip regis-
ters.
3. Native/Extended Mode, Word/Long Word Mode of Operation,
and Decoder Directives
This chapter provides a detailed explanation on the Z380’s unique
features, operation modes, and the Decoder Directives.
4. Addressing Modes and Data Types
Chapter4describestheAddressingmodeanddatatypeswhichthe
Z380 can handle.
5. Instruction Set
Chapter 5 contains an overview of the instruction set; as well as a
detailedinstruction-by-instructiondescriptioninalphabeticalorder.
6. Interrupts and Traps
Chapter 6 explains the interrupts and traps features of the Z380.
7. Reset
Chapter 7 describes the Reset function.
8. Z380 Benchmark Appnote
9. Z380 Questions & Answers
Z80380 CPU
USER'SMANUAL

ZILOG
DC-8297-03
Appendix A
Appendix A covers the Z380’s instruction format.
Appendix B
Appendix B contains all Z380 instructions sorted in Alphabetical
Order.
Appendix C
Appendix C contains all Z380 instructions sorted in Numerical
Order.
Appendix D
TheTablesinAppendixDlistsalltheZ380instructionsininstruction
affected by Native/Extended mode and Word/Long Word mode.
Appendix E
TheTables inAppendixElistsalltheZ380 instructionsininstruction
affected by DDIR IM (Immediate Decoder Directives) mode.
Index
A to Z listing of Z380™User's Manual key words and phrases.
This manual assumes the reader has a basic knowledge of CPU-
based system architectures and software development systems,
such as the use of the text editor, and invoking the assembler/
compiler.Also,knowledgeoftheZ80
®
CPUarchitectureisdesirable.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreementpertainingtosuchintendeduseisexecutedbetween
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
providedin thelabeling,can be reasonablyexpected to resultin
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
Telex 910-338-7621
FAX [phone]
Internet: http://www.zilog.com
© 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No
part of this document may be copied or reproduced in any form
or by any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change without
notice. Devices sold by Zilog, Inc. are covered by warranty and
patentindemnificationprovisionsappearinginZilog,Inc.Terms
and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,
IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-
TIONSET FORTH HEREIN OR REGARDINGTHEFREEDOM OF
THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT.ZILOG,INC.MAKESNOWARRANTYOFMER-
CHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog,Inc.shallnotberesponsibleforanyerrorsthatmayappear
in this document. Zilog, Inc. makes no commitment to update or
keep current the information contained in this document.

U SER ' S M ANUAL
Z ILOG
1.1 INTRODUCTION
USER’sMANUAL
CHAPTER 1
Z380™ARCHITECTURAL OVERVIEW
The Z380 CPU incorporates advanced architectural fea-
turesthatallowfastandefficientthroughputandincreased
memory addressing capabilities while maintaining Z80®
CPUandZ180®MPUobject-codecompatibility.TheZ380
CPU core provides a continuing growth path for present
Z80- or Z180®-based designs and offers the following key
features:
■Full Static CMOS Design with Low Power Standby
Mode Support
■DC to 18 MHz Operating Frequency @ 5 Volts VCC
■DC to 10 MHz Operating Frequency @ 33 Volts VCC
■Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80 and Z180 Microprocessors
■16-Bit (64K) or 32-Bit (4G) Linear Address Space
■16-Bit Internal Data Bus
■Two Clock Cycle Instruction Execution (Minimum)
■Multiple On-Chip Register Files (Z380 MPU has Four
Banks)
■BC/DE/HL/IX/IY Registers are Augmented by 16-Bit
Extended Registers (BCz/DEz/HLz/IXz/IYz), PC/SP/I
RegistersareAugmentedbyExtendedRegisters(PCz/
SPz/Iz) for 32-Bit Addressing Capability.
■Newly Added IX’ and IY’ Registers with Extended
Registers (IXz’/IYz’)
■Enhanced Interrupt Capabilities, Including 16-Bit
Vector
■UndefinedOpcodeTrapforFull Z380CPUInstruction
Set
The Z380 CPU, an enhanced version of the Z80 CPU,
retains the Z80 CPU instruction set to maintain complete
binary-codecompatiblitywithpresentZ80andZ180codes.
The basic addressing modes of the Z80 microprocessor
have been augmented with Stack Pointer Relative loads
and stores, 16-bit and 24-bit Indexed offsets, and in-
creased Indirect register addressing flexibility, with all of
theaddressing modes allowing accessto the entire 32-bit
address space. Significant additions have been made to
theinstructionsetiincorporating16-bitarithmeticandlogi-
cal operations, 16-bit I/O operations, multiply and divide,
acompletesetofregister-to-registerloadsandexchanges,
plus 32-bit load and exchange, and 32-bit arithmetic
operation for address calculation.
The basic register file of the Z80 microprocessor is ex-
panded toinclude alternateregister versions of the IX and
IYregisters.TherearefoursetsofthisbasicZ80micropro-
cessorregisterfilepresentintheZ380MPU,alongwiththe
necessary resources to manage switching between the
different register sets. All of the register pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
TheZ380 CPUexpands the basic 64 KbyteZ80 and Z180
address space to a full 4 Gbyte (32-bit) address space.
Thisaddressspace islinear andcompletelyaccessibleto
the user program. The external I/O address space is
similarlyexpandedtoafull4Gbyte(32-bit)range,and16-
bit I/O, both simple and block move are included. A 256
byte-wide internal I/O space has been added. This space
will be used to access on-chip I/O resources on future
Superintegration implementation of this CPU core.
Figure 1-1 provides a detailed description of the basic
register architecture of the Z380 CPU with the size of the
registerbanksshownatfoureach,however,theZ380CPU
architecture allows future expansion of up to 128 sets of
each.

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1.1 INTRODUCTION (Continued)
AF
BC
DE
HL
IXU IXL
IYU IYL
A' F'
B' C'
D' E'
H' L'
IXU' IXL'
IYU' IYL'
BCz'
DEz'
HLz'
IXz'
IYz'
BCz
DEz
HLz
IXz
IYz
R
I
SPz
PCz
Iz
SP
PC
4 Sets of Registers
Figure 1-1. Z380™CPU Register Architecture

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1.2 CPU ARCHITECTURE
TheZ380CPUisabinary-compatibleextensionoftheZ80
CPU and the Z180 CPU architecture. High throughput
rates are achieved by a high clock rate, high bus band-
width, and instruction fetch/execute overlap. Communi-
cating to the external world through an 8-bit or 16-bit data
bus, the Z380 CPU is a full 32-bit machine internally, with
a 32-bit ALU and 32-bit registers.
1.2.1 Modes of Operation
To maintain compatibility with the Z80/Z180 CPU while
having the capability to manipulate 4 Gbytes of memory
address range, the Z380 CPU has two bits in the Select
Register (SR) to control the modes of operation. One bit
controls the address manipulation mode: Native mode or
Extended mode; and the other bit controls the data ma-
nipulation mode: Word mode or Long Word mode. In
result, the Z380 CPU has four modes of operation. On
reset, the Z380 CPU is in Native/Word mode, which is
compatible to the Z80/Z180’s operation mode. For details
onthissubject,refertoChapter3,“Native/ExtendedMode,
Word/LongWord Mode of Operation, and DecoderDirec-
tive Instructions.”
1.2.1.1 Native Mode and Extended Mode
The Z380 CPU can operate in either Native or Extended
mode, as controlled by a bit in the Select Register (SR). In
Native mode (the Reset configuration), all address ma-
nipulations are performed modulo 65536 (216). In this
mode, the Program Counter (PC) only increments across
16 bits, all address manipulation instructions (increment,
decrement,add,subtract,indexed,stackrelative,andPC
relative)onlyoperateon16bits,andtheStackPointer(SP)
only increments and decrements across 16 bits. The PC
high-orderwordisleftatall zeros,asthehigh-orderwords
of the SP and the I register. Thus, Native mode is fully
compatiblewith theZ80CPU’s64Kbyteaddressmode. It
is still possible to address memory outside of 64 Kbyte
address space for data storage and retrieval in Native
mode,however,sincedirectaddresses,indirectaddresses,
and the high-order word of the SP, I, and the IX and IY
registers may be loaded with non-zero values. Executed
code and interrupt service routines must reside in the
lowest 64 Kbytes of the address space.
In Extended mode, however, all address manipulation
instructions operate on 32 bits, allowing access to the
entire 4 Gbyte address space of the Z380 CPU. In both
Native and Extended modes, the Z380 drives all 32 bits of
the address onto the external address bus; only the width
of the manipulated addresses distinguishes Native from
Extended mode. The Z380 CPU implements one instruc-
tion to allow switching from Native to Extended mode
(SETC XM); however, once in Extended mode, only Reset
will return the Z380 CPU to Native mode. This restriction
appliesbecauseofthepossibilityof“misplacing”interrupt
service routines or vector tables during the transition from
Extended mode back to Native mode.
1.2.1.2 Word or Long Word Mode
In addition to Native and Extended mode, which are
specific to memory space addressing, the Z380 CPU can
operateineitherWordorLongWordmodespecifictodata
load and exchange operations. In Word mode (the Reset
configuration), all word load and exchange operations
manipulate 16-bit quantities. For example, only the low-
order words of the source and destination are exchanged
in an exchange operation, with the high-order words
unaffected.
In the Long Word mode, all 32 bits of the source and
destination are exchanged. The Z380 CPU implements
twoinstructionsplusdecoderdirectivestoallowswitching
between Word and Long Word mode; SETC LW (Set
Control Long Word) and RESC LW (Reset Control Long
Word) perform a global switch, while DDIR W, DDIR LW
and their variants are decoder directives that select a
particular mode only for the instruction that they precede.
Note that all word data arithmetic (as opposed to address
manipulation arithmetic), rotate, shift, and logical opera-
tions are always in 16-bit quantities. They are not con-
trolled by either the Native/Extended or Word/Long Word
selections. The exceptions to the 16-bit quantities are, of
course, those multiply and divide operations with 32-bit
products or dividends.
All word Input/Output operations are performed on 16-bit
values, regardless of Word/Long Word operation.
1.2.2 Address Spaces
Addressing spaces in the Z380 CPU include the CPU
register, the CPU control register, the memory address,
on-chip I/O address, and the external I/O address. The
CPU register space is a superset of the Z80 CPU register
set, and consists of all of the registers in the CPU register
file. These CPU registers are used for data and address
manipulation,andareanextensionoftheZ80CPUregister
set, with four sets of this extended Z80 CPU register set
present in the Z380 CPU. Access to these registers is
specified in the instruction, with the active register set
selected by bits in the Select Register (SR) in the CPU
control register space.

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1.2.2 Address Spaces (Continued)
Eachregister set includes theprimaryregisters A, F, B,C,
D, E, H, L, IX, and IY, as well as the alternate registers A’,
F’, B’, C’, D’, E’, H’, L’, IX’, and IY’. Also, IX, IX’, IY, and IY’
registersareaccessibleastwobyteregisters,eachnamed
as IXU, IXL, IXU’ IXL’, IYU, IYL, IYU’, and IYL’. These byte
registerscan bepaired Bwith C,D withE, Hwith L,B’ with
C’, D’ with E’, and H’ with L’ to form word registers, and
these word registers are extended to 32 bits with the “z”
extension to the register. This register extension is only
accessible when using the register as a 32-bit register (in
the Long Word mode) or when swapping between the
most-significant and least-significant word of a 32-bit
registerusingSWAPinstructions.Wheneveraninstruction
refers to a word register, the implicit size is controlled by
Word or Long Word mode. Also included are the R, I, and
SP registers, as well as the PC.
The Select Register (SR) determines the operation of the
Z380CPU.ThecontentsofthisregisterdeterminetheCPU
operating mode, which register bank will be used, the
interrupt mode in effect, and so on.
TheZ380CPU’smemoryaddressspaceislinear4Gbytes.
Tokeep compatibility with the Z80 CPU memory address-
ing model, it has two control bits to change its operation
modes—Native or Extended, Word or Long Word.
The Z380 CPU architecture also distinguishes between
the memory and I/O addressing space and, therefore,
requires specific I/O instructions. Furthermore, I/O ad-
dressingspaceissubdividedintotheon-chipI/Oaddress
space and the external I/O addressing space. External
I/Oaddressingspace inthe Z380CPU is32 bitslong, and
internal I/O addressing space is 8-bits long. There are
separate sets of I/O instructions for each I/O addressing
space.
Some of the Internal I/O registers are used to control the
functionalityofthedevice,suchastoprogram/readstatus
of Trap, Assigned Vector Base address, enabling of inter-
rupts, and to get Chip version ID.
For details on this topic, refer to Chapter 2, “Address
Spaces.”
1.2.3 Data Types
ManydatatypesaresupportedbytheZ380CPUarchitec-
ture.Thebasicdatatypeis the8-bitbyte,whichis alsothe
basicaddressablememoryelement.Thearchitecturealso
supportsoperationsonbits,BCD(BinaryCodedDecimal)
digits, words (16 bits or 32 bits), byte strings and word
strings.For detailson thistopic, refertoSection 4.3,“Data
Types.”
1.2.4. Addressing Modes
AddressingmodesareusedbytheZ380CPUtocalculate
the effective address of an operand needed for execution
ofan instruction. Seven addressing modes aresupported
bytheZ380 CPU.Ofthese seven,oneis anadditionto the
Z80 CPU addressing modes (Stack Pointer Relative) and
the remaining six modes are either existing or extensions
to Z80 CPU addressing modes.
■Register
■Immediate
■Indirect Register
■Direct Address
■Indexed
■Program Counter Relative
■Stack Pointer Relative
All addressing modes are available on the 8-bit load,
arithmetic, and logical instructions; the 8-bit shift, rotate,
and bit manipulation instructions are limited to the regis-
ters and Indirect register addressing modes. The 16-bit
loads on the addressing registers support all addressing
modes except Index, while other 16-bit operations are
limited to the Register, Immediate, Indirect Register, In-
dex, Direct Address, and PC Relative addressing modes.
Fordetailsonthis subject,refertoChapter 4,“Addressing
Modes and Data Types.”
1.2.5. Instruction Set
The Z380 CPU instruction set is an expansion of the Z80
instruction set; the enhancements include support for
additional addressing modes for the Z80 instructions as
well as the addition of new instructions. The Z380 CPU
instruction set provides a full complement of 8-bit, 16-bit,
and32-bitoperation,includingmultiplicationanddivision.
For details on this subject, refer to Chapter 5, “Instruction
Set.”
1.2.6 Exception Conditions
TheZ380 CPU supports three types of exceptions (condi-
tions that alter the normal flow of program execution);
interrupts, traps, and resets.
Interrupts are asynchronous events typically triggered by
peripherals requiring attention. The Z380 CPU interrupt
structure has been significantly enhanced by increasing
the number of interrupt request lines and by adding an
efficient means for handling nested interrupts. The Z380
CPU has five interrupt lines. These are: Nonmaskable
Interrupt line (/NMI) and Maskable interrupt lines (/INT0,
/INT1,/INT2,and/INT3).Interruptrequestson/INT3-/INT1

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are handled by a newly added interrupt handing mode,
“Assigned Vectored Mode,” which is a fixed vectored
interrupt mode similar in interrupt handling to the Z180’s
interruptsfrom on-chipperipherals.Forhandlinginterrupt
requestson the /INT0line, there are fourmodes available:
■8080 compatible (Mode 0), in which the interrupting
device provides the first instruction of the interrupt
routine.
■Dedicated interrupts (Mode 1), in which the CPU
jumps to a dedicated address when an interrupt
occurs.
■Vectored interrupt mode (Mode 2), in which the
interruptingperipheraldevice providesa vectorintoa
table of jump address.
■Enhancedvectoredinterruptmode(Mode3),wherein
theCPUexpects16-bitvector,insteadof8-bitinterrupt
vectors in Mode 2.
The first three modes are compatible with Z80 interrupt
modes; the fourth mode provides more flexibility.
Traps are synchronous events that trigger a special CPU
response when an undefined instruction is executed. It
can be used to increase system reliability, or used as a
“software trap instruction.”
Hardware resets occur when the /RESET line is activated
andoverrideallotherconditions.A/RESETcausescertain
CPU control registers to be initialized.
For details on this subject, refer to Chapter 6, “Interrupts
and Traps.”
1.3 BENEFITS OF THE ARCHITECTURE
The Z380 CPU architecture provides several significant
benefits,includingincreasedprogramthroughputachieved
by higher bus bandwidth (16-bit wide bus), reduction to
two clocks/basic machine cycle (vs four clocks/cycle on
the Z80 CPU), prefetch cue, access to the larger linear
addressing space, enhanced instructions/new address-
ing mode, data/address manipulation in 16/32 bits, and
fastercontextswitchingbyutilizingmultipleregisterbanks.
1.3.1 High Throughput
Veryhigh throughputratescanbeachievedwiththe Z380
CPU, due to the basic machine cycle’s reduction to two
clocks/cycle from four clocks/cycle on the Z80 CPU, fine
tuned four staged pipeline with prefetch cue. This well
designed pipeline and prefetch cue are both totally trans-
parent to the user, thus maximizing the efficiency of the
pipeline all the time. The Z380 CPU implemented onto the
Z380MPUisconfiguredwitha16-bitwidedatabus,which
doubles the bus bandwidth. These architectural features
resultin two clocks/instructions executionminimum, three
clocks/instruction on average. The high clock rates (up to
40 MHz) achievable with this processor. Make the overall
performance of the Z380 CPU more than ten times that of
the Z80.
1.3.2 Linear Memory Address Space
Z380 CPU architecture has 4 Gbytes of linear memory
address space. The Z80 CPU architecture allows 64
Kbytes of memory addressing space. This was more than
sufficient when the Z80 CPU was first developed. But as
thetechnologyimprovedovertime,applicationsstartedto
demandmorecomplicatedprocessing,multitasking,faster
processing, etc., with the high level language needed to
develop software. As a result, 64 Kbytes of memory ad-
dressing space is not enough for some Z80 CPU based
applications. In order to handle more than 64 Kbytes of
memory,theZ80CPUrequiresaMemoryBankingscheme,
orMMU(MemoryManagementUnit),liketheZ180MPUor
Z280 MPU. These provide the overhead to access more
than 64 Kbytes of memory.
TheZ380CPUarchitectureallowsaccesstoafull4Gbytes
(232) of memory addressing space as well as 4 Gbytes of
I/O addressing area, without using a Memory Banking
scheme, or MMU.
1.3.3. Enhanced Instruction Set with 16-Bit
and 32-Bit Manipulation Capability
TheZ380 CPUinstruction set is100% upward compatible
to the Z80 CPU instruction set; that is all the Z80 instruc-
tionshavebeenpreservedatthebinarylevel.Newinstruc-
tions added to the Z380 CPU include:
■Less restricted operand source/destination
combinations.
■More flexible register exchange instructions.
■Stack Pointer Relative addressing mode.

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1.3.3. Enhanced Instruction Set with 16-Bit
and 32-Bit Manipulation Capability
(Continued)
■DDIR (Decoder Directive Instructions) to enhance
addressing capability to cover 4 Gbytes of memory
space, as well as data manipulation capability.
■Jump relative/Call relative instructions with 8-bit,
16-bit, or 24-bit displacement.
■Full complements of 16-bit arithmetic instructions.
■32-bitmanipulateinstructionsforaddressmanipulation.
These new instructions help to compact the code, as well
as shorten the program’s overall execution speed.
For details on this subject, refer to Chapter 5, “Instruction
Set.”
1.3.4 Faster Context Switching
TheZ380CPU architectureallowsmultiple setsof register
banks for AF/AF’, BC/DE/HL, BC’/DE’/HL’, IX/IX’, IY/IY’
registerpairs(includingeachregister'sExtendedportion).
When doing context switching, by exceptional condition
(trap or interrupts) or by subroutine/procedure calls, the
CPU has to save the contents of the registers currently in
use, along with the current CPU status.
Traditionally in the Z80 CPU architecture, this is done by
saving the contents of the register into memory, usually
using push/pop instructions or the auxiliary register file.
Register contents are then restored when the process is
finished.
With the Z380 CPU’s multiple register banks, saving the
contents of the working register set currently in use is just
a matter of an instruction to change the field in the Select
Register, which allows fast context switching.
1.4 SUMMARY
The Z380 CPU is a high-performance 16-bit Central Pro-
cessing Unit Superintegration™core. Code-compatible
with the Z80 CPU, the Z380 CPU architecture has been
expanded to include features such as multiple register
banks, 4 Gbytes of linear memory addressing space, and
efficient handling of nested interrupts. The benefits of this
architecture, including high throughput rates, code den-
sity, and compiler efficiency, greatly enhance the power
and versatility of the Z380 CPU. Thus, the Z380 CPU
provides both a growth path for existing Z80-based de-
signs and a powerful processor for applications and the
products to be developed around this CPU core.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreementpertainingtosuchintendeduseisexecutedbetween
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
providedin thelabeling,can be reasonablyexpected to resultin
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
Telex 910-338-7621
FAX [phone]
Internet: http://www.zilog.com
© 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No
part of this document may be copied or reproduced in any form
or by any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change without
notice. Devices sold by Zilog, Inc. are covered by warranty and
patentindemnificationprovisionsappearinginZilog,Inc.Terms
and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,
IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-
TIONSET FORTH HEREIN OR REGARDINGTHEFREEDOM OF
THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT.ZILOG,INC.MAKESNOWARRANTYOFMER-
CHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog,Inc.shallnotberesponsibleforanyerrorsthatmayappear
in this document. Zilog, Inc. makes no commitment to update or
keep current the information contained in this document.

2-1
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2.1 INTRODUCTION
U SER ’s M ANUAL
CHAPTER 2
ADDRESS SPACES
The Z380CPUsupportsfiveaddressspacescorrespond-
ing to the different types of locations that can be ad-
dressed and the method by which the logical addresses
are formed. These five address spaces are:
■CPU Register Space. This consists of all the register
addresses in the CPU register file.
■CPU Control Register Space. This consists of the
Select Register (SR).
■Memory Address Space. This consists of the
addresses of all locations in the main memory.
2.2 CPU REGISTER SPACE
The Z380 register file is illustrated in Figure 2-1. Note that
this figure shows the configuration of the register on the
Z380CPU,andthenumberoftheregisterfilesmayvaryon
future Superintegration devices. The Z380 CPU contains
abundant register resources. At any given time, the pro-
gramhasimmediate accesstoboth primaryand alternate
registers in the selected register set. Changing register
setsis asimple matterof anLDCTLinstruction toprogram
the Select Register (SR).
TheCPUregisterfileisdividedintofivegroupsofregisters
(an apostrophe indicates a register in the auxiliary regis-
ters).
■Four sets of Flag and Accumulator registers (F, A, F’,
A’)
■FoursetsofPrimary andWorkingregisters (B,C,D, E,
H, L, B’, C’, D’, E’, H’, L’)
■External I/O Address Space. This consists of all
externalI/Oportsaddressesthroughwhichperipheral
devices are accessed.
■On-Chip I/O Address Space. This consists of all
internal I/O port addresses through which peripheral
devices are accessed. Also, this addressing space
contains registers to control the functionality of the
device, giving status information.
■Four sets of Index registers (IX, IY, IX’, IY’)
■Stack Pointer (SP)
■Program Counter, Interrupt register, Refresh register
(PC, I, R)
Register addresses are either specified explicitly in the
instruction or are implied by the semantics of the instruc-
tion.

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2.2 CPU REGISTER SPACE (Continued)
AF
BC
DE
HL
IXU IXL
IYU IYL
A' F'
B' C'
D' E'
H' L'
IXU' IXL'
IYU' IYL'
BCz'
DEz'
HLz'
IXz'
IYz'
BCz
DEz
HLz
IXz
IYz
R
I
SPz
PCz
Iz
SP
PC
4 Sets of Registers
Figure 2-1. Register File Organization (Z380 MPU)

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2.2.1 Primary and Working Registers
The working register set is divided into two register files:
theprimary file andthe alternate file (designatedby prime
(‘)). Each file contains an 8-bit accumulator (A), a Flag
register (F), and six 8-bit general-purpose registers (B, C,
D, E, H, and L) with their Extended registers. Only one file
can be active at any given time, although data in the
inactive file can still be accessed by using EX R, R’
instructionsforthebyte-wideregisters,EXRR,RR’instruc-
tions for register pairs (either in 16-bit or 32-bit wide
dependingontheLWstatus).Exchangeinstructionsallow
the programmer to exchange the active file with the inac-
tive file. The EX AF, AF’, EXX, or EXALL instructions
changes the register files in use. Upon reset, the primary
register file in register set 0 is active. Changing register
setsis asimple matterof anLDCTLinstruction toprogram
SR.
The accumulator is the destination register for 8-bit arith-
metic and logical operations. The six general-purpose
registers can be paired (BC, DE, and HL), and are ex-
tendedto32bitsbytheextensiontotheregister(withsuffix
“z”; BCz/DEz/HLz), to form three 32-bit general-purpose
registers. The HL register serves as the 16-bit or 32-bit
accumulatorfor word operations. Access to theExtended
portionoftheregistersispossibleusingtheSWAPinstruc-
tion or word Load instructions in Long Word operation
mode.
The Flag register contains eight status flags. Four can be
individuallyusedforcontrolofprogrambranching,twoare
usedtosupport decimalarithmetic,and twoare reserved.
TheseflagsaresetorresetbyvariousCPUoperations.For
details on Flag operations, refer to Section 5.2, “Flag
Register.”
2.2.2. Index Registers
The four index registers, IX, IX’, IY, and IY’, are extended
to 32 bits by the extension to the register (with suffix “z”;
IXz/IYz), to form 32-bit index registers. To access the
ExtendedportionoftheregistersusetheSWAPinstruction
or word Load instructions in Long Word operation mode.
These Index registers hold a 32-bit base address that is
used in the Index addressing mode.
Only one register of each can be active at any given time,
although data in the inactive file can still be accessed by
usingEXIX,IX’andEXIY,IY’(eitherin16-bitor32-bitwide
depending on the LW bit status). Index registers can also
function as general-purpose registers with the upper and
lower bytes of the lower 16 bits being accessed individu-
ally.ThesebyteregistersarecalledIXU,IXU’,IXL,andIXL’
for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for
the IY and IY’ registers.
Selection of primary or auxiliary Index registers can be
made by EXXX, EXXY, or EXALL instructions, or program-
mingofSR.Uponreset,theprimaryregistersinregisterset
0 is active. Changing register sets is a simple matter of an
LDCTL instruction to program SR.
2.2.3. Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and
3 for /INT0 to generate a 32-bit indirect address to an
interrupt service routine. The I register supplies the upper
24 or 16 bits of the indirect address and the interrupting
peripheral supplies the lower eight or 16 bits. In Assigned
Vectors mode for /INT3-/INT1, the upper 16 bits of the
vectoraresuppliedbytheIregister;bits15-9aresupplied
from the Assigned Vector Base register, and bits 8-0 are
the assigned vector unique to each of /INT3-/INT1.
2.2.4. Program Counter
The Program Counter (PC) is used to sequence through
instructions in the currently executing program and to
generate relative addresses. The PC contains the 32-bit
address of the current instruction being fetched from
memory. In Native mode, the PC is effectively only 16 bits
long, since the upper word [PC31-PC16] of the PC is
forcedtozero,andwhencarriedfrombit15tobit16(Lower
word [PC15-PC0] to Upper word [PC31-PC16]) are inhib-
ited in this mode. In Extended mode, the PC is allowed to
increment across all 32 bits.
2.2.5. R Register
The R register can be used as a general-purpose 8-bit
read/write register. The R register is not associated with
therefreshcontrolleranditscontentsarechangedonlyby
the user.
2.2.6. Stack Pointer
TheStackPointer(SP)isusedforsavinginformationwhen
an interrupt or trap occurs and for supporting subroutine
callsand returns.Stack Pointerrelative addressingallows
parameterpassingusingtheSP.TheSPis16bitswide,but
is extended by the SPz register to 32 bits wide.

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2.2.6 Stack Pointer (Continued)
Increment/decrement of the Stack Pointer is affected by
modesof operation (Native or Extended). In Native mode,
the stack operates in modulo 216, and in Extended mode,
itoperatesinmodulo232.Forexample,SPholds0001FFFEH,
anddoestheWordsizePopoperation.Aftertheoperation,
SP holds 00010000H in Native mode, and 00020000H in
Extended mode. In either case, SPz can be programmed
to set Stack frame. This is done by the Load- to-Stack
pointer instructions in Long Word mode.
2.3. CPU CONTROL REGISTER SPACE
The CPU control register space consists of the 32-bit
SelectRegister(SR).TheSRmaybe accessedasawhole
or the upper three bytes of the SR may be accessed
individually as YSR, XSR, and DSR. In addition, these
upperthreebytescanbeloadedwiththesamebytevalue.
TheSRmayalsobePUSHedandPOPedandisclearedto
zerosonReset.Fordetailsonthisregister,refertoChapter
5.3, “Select Register.”
2.4 MEMORY ADDRESS SPACE
The memory address space can be viewed as a string of
4 Gbytes numbered consecutively in ascending order.
The8-bitbyteisthebasicaddressableelementintheZ380
MPU memory address space. However, there are other
addressabledataelements:bits,2-bytewords,bytestrings,
and 4-byte words.
Thesizeofthedataelementbeingaddresseddependson
the instruction being executed as well as the Word/Long
Word mode. A bit can be addressed by specifying a byte
and a bit within that byte. Bits are numbered from right to
left, with the least significant bit being 0, as illustrated in
Figure 2-2.
The address of a multiple-byte entity is the same as the
addressofthe bytewiththe lowestmemory addressinthe
entity. Multiple-byte entities can be stored beginning with
either even or odd memory addresses. A word (either 2-
byte or 4-byte entity) is aligned if its address is even;
otherwise it is unaligned. Multiple bus transactions, which
may be required to access multiple-byte entities, can be
minimized if alignment is maintained.
The format of multiple-byte data types is also shown in
Figure2-2.Notethat whenawordis storedinmemory,the
leastsignificantbyteprecedesthemoresignificantbyteof
the word, as in the Z80 CPU architecture. Also, the lower-
addressedbyteispresentontheupperbyteoftheexternal
data bus.

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Bits within a byte:
16-bit word at address n:
Least Significant Byte
Most Significant Byte
Address n
Address n+1
32-bit word at address n:
D7-0 (Least Significant Byte)
D15-8
Address n
Address n+1
Address n+2
Address n+3
D31-24 (Most Significant Byte)
D23-16
Memory addresses:
Least Significant Byte
Even address (A0=0)
Most Significant Byte
Odd address (A0=1)
1514131211109876543210
Figure 2-2. Bit/Byte Ordering Conventions

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2.5. EXTERNAL I/O ADDRESS SPACE
ExternalI/Oaddressspaceis4GbytesinsizeandExternal
I/O addresses are generated by I/O instructions except
thosereservedforon-chipI/Oaddressspaceaccesses.It
can take a variety of forms, as shown in Table 2.1. An
externalI/Oreadorwriteisalwaysonetransaction,regard-
less of the bus size and the type of I/O instruction.
Table 2-1. I/O Addressing Options
Address Bus
I/O Instruction A31-A24 A23-A16 A15-A8 A7-A0
IN A, (n) 00000000 00000000 A7-A0 n
IN dst,(C) BC31-B24 BC23-B16 BC15-B8 BC7-B0
INA(W) dst,(mn) 00000000 00000000 m n
DDIR IB INA(W) dst,(lmn) 00000000 l m n
DDIR IW INA(W) dst,(klmn) k l m n
Block Input BC31-B24 BC23-B16 BC15-B8 BC7-B0
OUT (n),A 00000000 00000000 A7-A0 n
OUT (C),dst BC31-B24 BC23-B16 BC15-B8 BC7-B0
OUTA(W) (mn),dst 00000000 00000000 m n
DDIR IB OUTA(W) (lmn),dst 00000000 l m n
DDIR IW OUTA(W) (klmn),dst k l m n
Block Output BC31-B24 BC23-B16 BC15-B8 BC7-B0
2.6. ON-CHIP I/O ADDRESS SPACE
The Z380 CPU has the on-chip I/O address space to
control on-chip peripheral functions of the Superintegra-
tion™version of the devices. A portion of its interrupt
functions are also controlled by several on-chip registers,
whichoccupyanon-chipI/Oaddressspace.Thison-chip
I/Oaddressspacecanbeaccessedonlywiththefollowing
reservedon-chipI/Oinstructions whichareidenticaltothe
Z180 original I/O instructions to access Page 0 I/O ad-
dressing area.
IN0 R,(n) OTIM
IN0 (n) OTIMR
OUT0 (n),R OTDM
TSTIO n OTDMR
When one of these I/O instructions is executed, the Z380
MPU outputs the register address being accessed in a
pseudo-transaction of two BUSCLK cycles duration, with
the address signals A31-A8 at zero. In the pseudo-trans-
actions, all bus control signals are at their inactive state.
The following four registers are assigned to this address-
ing space as a part of the Z380 CPU core:
Register Name Internal I/O Address
Interrupt Enable Register 17H
Assigned Vector Base Register 18H
Trap and Break Register 19H
Chip Version ID Register 0FFH
The Chip Version ID register returns one byte data, which
indicatestheversionoftheCPU,orthespecificimplemen-
tation of the Z380 CPU based Superintegration device.
Currently,thevalue00HisassignedtotheZ380MPU,and
other values are reserved.
Fortheotherthreeregisters,refertoChapter6,“Interrupts
and Traps.”
Also, the Z380 MPU has registers to control chip selects,
refresh, waits, and I/O clock divide to Internal I/O address
00H to 10H. For these registers, refer to the Z380 MPU
Product specification (DC-3003-01).

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when properly used in accordance with instructions for use
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2.1 INTRODUCTION
U SER ’s M ANUAL
CHAPTER 2
ADDRESS SPACES
The Z380CPUsupportsfiveaddressspacescorrespond-
ing to the different types of locations that can be ad-
dressed and the method by which the logical addresses
are formed. These five address spaces are:
■CPU Register Space. This consists of all the register
addresses in the CPU register file.
■CPU Control Register Space. This consists of the
Select Register (SR).
■Memory Address Space. This consists of the
addresses of all locations in the main memory.
2.2 CPU REGISTER SPACE
The Z380 register file is illustrated in Figure 2-1. Note that
this figure shows the configuration of the register on the
Z380CPU,andthenumberoftheregisterfilesmayvaryon
future Superintegration devices. The Z380 CPU contains
abundant register resources. At any given time, the pro-
gramhasimmediate accesstoboth primaryand alternate
registers in the selected register set. Changing register
setsis asimple matterof anLDCTLinstruction toprogram
the Select Register (SR).
TheCPUregisterfileisdividedintofivegroupsofregisters
(an apostrophe indicates a register in the auxiliary regis-
ters).
■Four sets of Flag and Accumulator registers (F, A, F’,
A’)
■FoursetsofPrimary andWorkingregisters (B,C,D, E,
H, L, B’, C’, D’, E’, H’, L’)
■External I/O Address Space. This consists of all
externalI/Oportsaddressesthroughwhichperipheral
devices are accessed.
■On-Chip I/O Address Space. This consists of all
internal I/O port addresses through which peripheral
devices are accessed. Also, this addressing space
contains registers to control the functionality of the
device, giving status information.
■Four sets of Index registers (IX, IY, IX’, IY’)
■Stack Pointer (SP)
■Program Counter, Interrupt register, Refresh register
(PC, I, R)
Register addresses are either specified explicitly in the
instruction or are implied by the semantics of the instruc-
tion.

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2.2 CPU REGISTER SPACE (Continued)
AF
BC
DE
HL
IXU IXL
IYU IYL
A' F'
B' C'
D' E'
H' L'
IXU' IXL'
IYU' IYL'
BCz'
DEz'
HLz'
IXz'
IYz'
BCz
DEz
HLz
IXz
IYz
R
I
SPz
PCz
Iz
SP
PC
4 Sets of Registers
Figure 2-1. Register File Organization (Z380 MPU)

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2.2.1 Primary and Working Registers
The working register set is divided into two register files:
theprimary file andthe alternate file (designatedby prime
(‘)). Each file contains an 8-bit accumulator (A), a Flag
register (F), and six 8-bit general-purpose registers (B, C,
D, E, H, and L) with their Extended registers. Only one file
can be active at any given time, although data in the
inactive file can still be accessed by using EX R, R’
instructionsforthebyte-wideregisters,EXRR,RR’instruc-
tions for register pairs (either in 16-bit or 32-bit wide
dependingontheLWstatus).Exchangeinstructionsallow
the programmer to exchange the active file with the inac-
tive file. The EX AF, AF’, EXX, or EXALL instructions
changes the register files in use. Upon reset, the primary
register file in register set 0 is active. Changing register
setsis asimple matterof anLDCTLinstruction toprogram
SR.
The accumulator is the destination register for 8-bit arith-
metic and logical operations. The six general-purpose
registers can be paired (BC, DE, and HL), and are ex-
tendedto32bitsbytheextensiontotheregister(withsuffix
“z”; BCz/DEz/HLz), to form three 32-bit general-purpose
registers. The HL register serves as the 16-bit or 32-bit
accumulatorfor word operations. Access to theExtended
portionoftheregistersispossibleusingtheSWAPinstruc-
tion or word Load instructions in Long Word operation
mode.
The Flag register contains eight status flags. Four can be
individuallyusedforcontrolofprogrambranching,twoare
usedtosupport decimalarithmetic,and twoare reserved.
TheseflagsaresetorresetbyvariousCPUoperations.For
details on Flag operations, refer to Section 5.2, “Flag
Register.”
2.2.2. Index Registers
The four index registers, IX, IX’, IY, and IY’, are extended
to 32 bits by the extension to the register (with suffix “z”;
IXz/IYz), to form 32-bit index registers. To access the
ExtendedportionoftheregistersusetheSWAPinstruction
or word Load instructions in Long Word operation mode.
These Index registers hold a 32-bit base address that is
used in the Index addressing mode.
Only one register of each can be active at any given time,
although data in the inactive file can still be accessed by
usingEXIX,IX’andEXIY,IY’(eitherin16-bitor32-bitwide
depending on the LW bit status). Index registers can also
function as general-purpose registers with the upper and
lower bytes of the lower 16 bits being accessed individu-
ally.ThesebyteregistersarecalledIXU,IXU’,IXL,andIXL’
for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for
the IY and IY’ registers.
Selection of primary or auxiliary Index registers can be
made by EXXX, EXXY, or EXALL instructions, or program-
mingofSR.Uponreset,theprimaryregistersinregisterset
0 is active. Changing register sets is a simple matter of an
LDCTL instruction to program SR.
2.2.3. Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and
3 for /INT0 to generate a 32-bit indirect address to an
interrupt service routine. The I register supplies the upper
24 or 16 bits of the indirect address and the interrupting
peripheral supplies the lower eight or 16 bits. In Assigned
Vectors mode for /INT3-/INT1, the upper 16 bits of the
vectoraresuppliedbytheIregister;bits15-9aresupplied
from the Assigned Vector Base register, and bits 8-0 are
the assigned vector unique to each of /INT3-/INT1.
2.2.4. Program Counter
The Program Counter (PC) is used to sequence through
instructions in the currently executing program and to
generate relative addresses. The PC contains the 32-bit
address of the current instruction being fetched from
memory. In Native mode, the PC is effectively only 16 bits
long, since the upper word [PC31-PC16] of the PC is
forcedtozero,andwhencarriedfrombit15tobit16(Lower
word [PC15-PC0] to Upper word [PC31-PC16]) are inhib-
ited in this mode. In Extended mode, the PC is allowed to
increment across all 32 bits.
2.2.5. R Register
The R register can be used as a general-purpose 8-bit
read/write register. The R register is not associated with
therefreshcontrolleranditscontentsarechangedonlyby
the user.
2.2.6. Stack Pointer
TheStackPointer(SP)isusedforsavinginformationwhen
an interrupt or trap occurs and for supporting subroutine
callsand returns.Stack Pointerrelative addressingallows
parameterpassingusingtheSP.TheSPis16bitswide,but
is extended by the SPz register to 32 bits wide.

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2.2.6 Stack Pointer (Continued)
Increment/decrement of the Stack Pointer is affected by
modesof operation (Native or Extended). In Native mode,
the stack operates in modulo 216, and in Extended mode,
itoperatesinmodulo232.Forexample,SPholds0001FFFEH,
anddoestheWordsizePopoperation.Aftertheoperation,
SP holds 00010000H in Native mode, and 00020000H in
Extended mode. In either case, SPz can be programmed
to set Stack frame. This is done by the Load- to-Stack
pointer instructions in Long Word mode.
2.3. CPU CONTROL REGISTER SPACE
The CPU control register space consists of the 32-bit
SelectRegister(SR).TheSRmaybe accessedasawhole
or the upper three bytes of the SR may be accessed
individually as YSR, XSR, and DSR. In addition, these
upperthreebytescanbeloadedwiththesamebytevalue.
TheSRmayalsobePUSHedandPOPedandisclearedto
zerosonReset.Fordetailsonthisregister,refertoChapter
5.3, “Select Register.”
2.4 MEMORY ADDRESS SPACE
The memory address space can be viewed as a string of
4 Gbytes numbered consecutively in ascending order.
The8-bitbyteisthebasicaddressableelementintheZ380
MPU memory address space. However, there are other
addressabledataelements:bits,2-bytewords,bytestrings,
and 4-byte words.
Thesizeofthedataelementbeingaddresseddependson
the instruction being executed as well as the Word/Long
Word mode. A bit can be addressed by specifying a byte
and a bit within that byte. Bits are numbered from right to
left, with the least significant bit being 0, as illustrated in
Figure 2-2.
The address of a multiple-byte entity is the same as the
addressofthe bytewiththe lowestmemory addressinthe
entity. Multiple-byte entities can be stored beginning with
either even or odd memory addresses. A word (either 2-
byte or 4-byte entity) is aligned if its address is even;
otherwise it is unaligned. Multiple bus transactions, which
may be required to access multiple-byte entities, can be
minimized if alignment is maintained.
The format of multiple-byte data types is also shown in
Figure2-2.Notethat whenawordis storedinmemory,the
leastsignificantbyteprecedesthemoresignificantbyteof
the word, as in the Z80 CPU architecture. Also, the lower-
addressedbyteispresentontheupperbyteoftheexternal
data bus.

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Bits within a byte:
16-bit word at address n:
Least Significant Byte
Most Significant Byte
Address n
Address n+1
32-bit word at address n:
D7-0 (Least Significant Byte)
D15-8
Address n
Address n+1
Address n+2
Address n+3
D31-24 (Most Significant Byte)
D23-16
Memory addresses:
Least Significant Byte
Even address (A0=0)
Most Significant Byte
Odd address (A0=1)
1514131211109876543210
Figure 2-2. Bit/Byte Ordering Conventions