abaco systems FMC168 User manual

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 1 of 28
FMC168/4/2
User Manual
FMC168 / FMC164 / FMC162
Abaco Systems
Support Portal
This document is the property of Abaco Systems and may not be copied nor communicated to a
third party without the written permission Abaco Systems.
© Abaco Systems 2017

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 2 of 28
Revision History
Document
Revision Changes Author Peer
Review Quality Approval Date
1.0 Release -- -- -- 2013/07/05
1.1 Added LPC compatibility -- -- -- 2013/07/25
1.2 Added FMC162, 2-channel
variant -- -- -- 2014/03/18
1.3
Revised some descriptions
and fixed typos. -- -- -- 2014/04/07
1.4
Correction in main
characteristics table.
Corrected I2C and CPLD
information
-- -- -- 2014/06/17
1.5
Corrected external VCO part
number -- -- -- 2014/09/08
1.6
Removed reference to cutoff
filter in section -- -- -- 2015/03/06
1.7 Update to the Abaco format
Added description about
heatsink option in the cooling
section.
EBa JHN JDS 2017/03/27

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 3 of 28
Table of Contents
1Acronyms and related documents............................................................................. 5
1.1 Acronyms................................................................................................................ 5
1.2 Related Documents................................................................................................. 5
2General description..................................................................................................... 6
3Installation ................................................................................................................... 7
3.1 Requirements and handling instructions.................................................................. 7
4Design .......................................................................................................................... 7
4.1 Physical specifications ............................................................................................ 7
4.1.1 Board Dimensions............................................................................................ 7
4.1.2 Front panel....................................................................................................... 7
4.2 Electrical specifications........................................................................................... 9
4.2.1 QDR LVDS mode............................................................................................. 9
4.2.2 DDR LVDS mode............................................................................................. 9
4.2.3 EEPROM ......................................................................................................... 9
4.2.4 Stacked FMC ................................................................................................... 9
4.2.5 JTAG...............................................................................................................10
4.3 Main characteristics................................................................................................10
4.4 Analog input channels............................................................................................11
4.4.1 AC coupling.....................................................................................................11
4.4.2 DC coupling ....................................................................................................11
4.5 External clock input................................................................................................12
4.6 External clock output..............................................................................................12
4.7 External trigger/sync input......................................................................................12
4.8 Clock tree...............................................................................................................12
4.8.1 Architecture.....................................................................................................12
4.8.2 PLL design......................................................................................................14
4.9 Power supply..........................................................................................................14
5Controlling the FMC168/4/2........................................................................................14
5.1 CPLD .....................................................................................................................15
5.2 Onboard monitoring................................................................................................16
6Environment................................................................................................................16
6.1 Temperature ..........................................................................................................16
6.2 Monitoring..............................................................................................................16
6.3 Cooling...................................................................................................................16
6.3.1 Convection cooling..........................................................................................17
6.3.2 Conduction cooling..........................................................................................17
7Safety...........................................................................................................................17
8EMC .............................................................................................................................17
9Ordering information..................................................................................................17
10 Warranty......................................................................................................................17
Appendix A FMC168/4/2 connector pin-out – QDR mode............................................19

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 4 of 28
Appendix B FMC168/4/2 connector pin-out – DDR mode............................................23
Appendix C CPLD Register map...................................................................................27

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 5 of 28
1 Acronyms and related documents
1.1 Acronyms
ADC
Analog-to-Digital Converter
DDR
Double Data Rate
DSP
Digital Signal Processing
EPROM
Erasable Programmable Read-Only Memory
FBGA
Fineline Ball Grid Array
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
JTAG
Join Test Action Group
LED
Light Emitting Diode
LVTTL
Low Voltage Transistor Logic level
LPC
Low Pin Count
LSB
Least Significant Bit(s)
LVDS
Low Voltage Differential Signaling
MGT
Multi-Gigabit Transceiver
MSB
Most Significant Bit(s)
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PCIe
PCI Express
PLL
Phase-Locked Loop
PMC
PCI Mezzanine Card
PSSR
Power Supply Rejection Ratio
QDR
Quadruple Data rate
SDRAM
Synchronous Dynamic Random Access memory
SRAM
Synchronous Random Access memory
TTL
Transistor Logic level
XMC
PCIe Mezzanine card
Table 1: Glossary
1.2 Related Documents
•FPGA Mezzanine Card (FMC) standard ANSI/VITA 57.1-2010
•Datasheet ADS42LB69 Nov 2012, Analog Devices
•Datasheet AD9517-3, Analog Devices
•Datasheet AD7291BCPZ Rev B, Analog Devices

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 6 of 28
2 General description
The FMC168 is an eight channel ADC FMC daughter card. The card provides eight 16-bit
250MSPS ADC channels which can be clocked by an internal clock source (optionally locked
to an external reference) or an externally supplied sample clock. There is one trigger input for
customized sampling control. The FMC168 daughter card is mechanically and electrically
compliant to FMC standard (ANSI/VITA 57.1). The FMC168 has a high-pin count connector,
front panel I/O, and can be used in a conduction-cooled environment. A four channel variant,
the FMC164, and a two channel variant, the FMC162, are available and offer the same
features with fewer channels.
The design is based on TI’s ADS42LB69 dual-channel 16-bit 250MSPS ADC with
programmable DDR LVDS or QDR LVDS outputs. The analog signal input can be either AC-
coupled or DC-coupled connecting to SSMC coax connectors on the front panel. In addition,
the FMC164 and FMC162 offer optional differential inputs.
The FMC168/4/2 allows flexible control of sampling frequency and analog input gain through
the I2C communication bus. Furthermore the card is equipped with power supply and
temperature monitoring and offers several power-down modes to switch off unused
functions.
Reference Clock
or
Sample Clock
Trigger
ADC A
ADS42LB69
16-bit, 250 MSPS
FMC Connector
HPC 400 Pins (LPC compatible)
Clock Tree Clock
Status & Control
Clock [2x1 pair]
Clock
Output
ADC H
………. ………. ………. ……….
Monitoring
OPTIONAL
EEPROM
I2C
BOARD
CONTROL
CPLD
Data [8x4 pair]
Clock [2x1 pair] *
Data [8x4 pair] *
* HPC connections
Figure 1: FMC168 block diagram
Note1: Although the FMC168/4/2 is equipped with a HPC connector, it can be used in LPC
carrier hardware. The LVDS interface on LPC runs at 500MHz DDR for 250Msps sampling
rate. On HPC carriers the LVDS interface can be reduced to 250MHz DDR for 250Msps
sampling.
Note2: Over-range bit and frame signals are not available when targeting the LPC connector
only.

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 7 of 28
3 Installation
3.1 Requirements and handling instructions
•Prevent electrostatic discharges by observing ESD precautions when handling the
card.
•Do not flex the card, and do not exceed the maximum torque specification on the
SSMC connectors.
•The FMC168/4/2 daughter card must be installed on a carrier card compliant to the
FMC standard.
•The FMC carrier card must support the low-pin count connector (160-pins) and may
support the high-pin count connector (400-pins).
•The FMC168/4/2 supports a VADJ voltage between +1.5V and +3.3V. The FMC
carrier must support VIO_B equal to VADJ.
4 Design
4.1 Physical specifications
4.1.1 Board Dimensions
The FMC168/4/2 card complies with the FMC standard known as ANSI/VITA 57.1. The card
is a single-width, conduction-cooled mezzanine module (with region 1 and front panel I/O).
Although the card has a front panel I/O, it is compatible with most fixed rib carrier cards. The
front area holds 10 SSMC connectors that do not conflict with a front rib on a carrier card.
The stacking height is 10mm.
4.1.2 Front panel
There are 10 SSMC connectors available from the front panel. From top to bottom; analog in
A to analog in D, clock in (CL), trigger in (TR), and analog in E to analog in H. Different front
panels are provided per variant.
Figure 2: FMC168 front panel layout
Figure 3: FMC164 front panel layout (single-ended)

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 8 of 28
Figure 4: FMC162 front panel layout (single-ended)
The tables below provide the front label to A/D converter and FMC signal mappings. For the
FMC168, the mapping is 1-to-1.For the reduced channel variants, the front panel labels don’t
always match the FMC connector signal names. For example, data sampled from FMC162
input B is present on FMC connector CHC_D[3..0] (QDR mode). Refer to Appendix A and B
for all FMC pin assignments.
Front Label FMC168 FMC connector signal
names
A Input 1st A/D CHA_*
B Input 2nd A/D CHB_*
C Input 3rd A/D CHC_*
D Input 4th A/D CHD_*
E Input 5th A/D CHE_*
F Input 6th A/D CHF_*
G Input 7th A/D CHG_*
H Input 8th A/D CHH_*
Table 2: FMC168 Connector function assignment
FMC164 Single ended FMC164 Differential
Font
Label Input FMC connector signal names Font Label Input FMC connector signal names
A Input 1st A/D CHA_* A Non-Inverted input 1st A/D CHA_*
B Inverted input 1st A/D
B Input 2nd A/D CHC_* C Non-Inverted input 2nd A/D CHC_*
D Inverted input 2nd A/D
C Input 3rd A/D CHE_* E Non-Inverted input 3rd A/D CHE_*
F Inverted input 3rd A/D
D Input 4th A/D CHG_* G Non-Inverted input 4th A/D CHG_*
H Inverted input 4th A/D
Table 3: FMC164 Connector function assignment

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 9 of 28
FMC162 Single ended FMC162 Differential
Font
Label Input FMC connector signal names Font Label Input FMC connector signal names
A Input 1st A/D CHA_* A Non-Inverted input 1st A/D CHA_*
B Inverted input 1st A/D
B Input 2nd A/D CHC_* C Non-Inverted input 2nd A/D CHC_*
D Inverted input 2nd A/D
Table 4: FMC162 Connector function assignment
4.2 Electrical specifications
The FMC168/4/2 card is designed to operate in LVDS mode. The connections on FMC bank
LA allow simultaneous sampling of eight (FMC168), four (FMC164), or two (FMC162)
channels. This is referred to as QDR LVDS mode. With the use of the connections on FMC
bank HA and HB, the digital interface rate can be reduced by a factor of two. This is referred
to as DDR LVDS mode.
4.2.1 QDR LVDS mode
In QDR LVDS mode each channel uses four LVDS pairs at 500MHz DDR, with a sampling
frequency of 250MHz. This mode can be used by both LPC and HPC carrier hardware.
4.2.2 DDR LVDS mode
In DDR LVDS mode each channel uses eight LVDS pairs at 250MHz DDR, with a sampling
frequency of 250MHz. This mode can only be used by HPC carrier hardware.
4.2.3 EEPROM
The FMC168/4/2 card carries a serial EEPROM (M24C02-WDW6) which is accessible from
the carrier card through the I2C bus. The EEPROM is powered by 3P3VAUX. The standby
current is only 0.01µA when SCL and SDA are kept at 3P3VAUX level. The EEPROM is
write-protected by default.
4.2.4 Stacked FMC
The FMC connector is referred as the top FMC connector as defined in ANSI/VITA 57.1. The
FMC168/4/2 can be used in a stacked environment when the bottom FMC connector is
mounted. The following connections are available between the top and bottom FMC
connector:
•All gigabit data signals (DP[0..9]_M2C_P/N, DP[0..9]_C2M_P/N)
•All gigabit reference clocks (GBTCLK[0..1]_M2C_P/N)
•RES0
•3P3VAUX, 3P3V, 12P0V, VADJ
•JTAG (see section 4.2.3)

UM031 FMC168/4/2 r1.7
UM031 www.abaco.com page 10 of 28
4.2.5 JTAG
The FMC168/4/2 has a CPLD device in the JTAG chain. The TDO pin of the CPLD is
normally connected to the TDO pin of the top FMC connector through a buffer to ensure
continuity of the JTAG chain.
In a stacked environment, the TDO pin of the CPLD will be decoupled from the TDO pin of
the top FMC connector by the PRST_M2C_L signal coming from the bottom connector.
TRST#, TCK, TMS, and TDO are directly connected between top and bottom connector.
There is a build option to bypass the CPLD after factory programming for customers
requiring a direct connection between TDI and TDO on the top connector. Contact Abaco for
detailed information.
TDI TDO
TDI TDO PRSNT_M2C_L
PRSNT_M2C_L
Top connector (to FMC carrier)
Bottom connector (to stacked FMC)
3P3V
OE
TMS
TMS
TCK
TCK
TRST#
TRST#
CPLD
Figure 5: JTAG connections
4.3 Main characteristics
Analog inputs
Number of channels 8 (FMC168) 4 (FMC164)
2 (FMC162)
Channel resolution 16-bit
Input voltage range 1Vp-p (4dBm) to 2Vp-p (10 dBm) programmable
Input gain Programmable from -2dB to 6dB in 0.5dB steps
Input impedance 50Ω
Analog input bandwidth 500MHz (typical)
SNR (Fs = 250MHz)
SNR (Fin=11MHz): 70.643 dB (typical)
SNR (Fin=32MHz): 70.094 dB (typical)
SNR (Fin=64MHz): 66.576 dB (typical)
SNR (Fin=124MHz) 63.472 dB (typical)
SFDR (Fs = 250MHz)
SFDR (Fin=11MHz): 62.465 dBc (typical)
SFDR (Fin=32MHz): 67.082 dBc (typical)
SFDR (Fin=64MHz): 78.212 dBc (typical)
SFDR (Fin=124MHz) 72.499 dBc (typical)
External sampling clock input
Input Level 0dBm typical (LVTTL level supported)