Alinx AX7102 User manual

ALINX FPGA BOARD
AX7102
User Manual

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Copyright Notice:
Copyright ©2018 by ALINX Technologies inc. All rights are reserved.
Development Environment:
Vivado 2015.4 is from Xilinx website
https://www.xilinx.com
Official website:
Http://www.alinx.com.cn
E-mail:
[email protected]
Tel:
[phone]
WeChat public number：
ALINX-HEIJIN

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Contents
一、 Overview .................................................................................................................6
二、 FPGA Core Board..................................................................................................8
(一)Overview .......................................................................................................... 8
(二)FPGA.................................................................................................................. 9
(三)CLOCK .............................................................................................................11
(四)DDR3 ...............................................................................................................14
(五)QSPI Flash......................................................................................................17
(六)LEDs .................................................................................................................19
(七)RESET Button................................................................................................20
(八)JTAG Interface ..............................................................................................21
(九)Power Input...................................................................................................22
(十)Board-to-Board Connector......................................................................23
(十一)POWER............................................................................................................31
(十二)Mechanical ....................................................................................................34
三、 Expansion Board.................................................................................................35
(一)Overview ........................................................................................................35
(二)Gigabit Ethernet ..........................................................................................36
(三)SFP Interface.................................................................................................38
(四)VGA Port ........................................................................................................40
(五)USB2.0.............................................................................................................42
(六)SD Socket.......................................................................................................45
(七)USB Serial Port.............................................................................................46
(八)RS232 接口.....................................................................................................48
(九)EEPROM 24LC04..........................................................................................49
(十)RTC ...................................................................................................................50
(十一)GPIO Expansion Headers .........................................................................51
(十二)JTAG Interface ..............................................................................................55
(十三)Buttons ...........................................................................................................55

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(十四)LED ...................................................................................................................56
(十五)POWER............................................................................................................57

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The AX7102 development Kit presents a robust hardware design platform built
around the XILINX Artix-7 FPGA, which optimized for lowest cost and power
with small form-factor packaging for the highest volume applications. The
AX7102 development board is equipped with high-speed DDR3 memory, SFP
networking, and USB2.0 capabilities, Ethernet networking, and much more
other resource that promise many exciting applications.
This ARTIX-7 FPGA development platform includes core board and expansion
board, so that users can reuse the core board in their own projects conveniently.
The kit contains complete reference designs and source code for each part on
board. it is a good choice for students or FPGA engineers to learn Artix-7 FPGA
and do evaluation base on it. This document provides users key information
about the kit. Figure1-1 shows a photograph of the whole board.
Figure1-1 AX7102 Overview

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一、 Overview
The AX7102 board comprises FPGA core board and expansion board, four
high-speed board-to-board connectors are used to connect between the core
board and the expansion board.
The core board is a minimal systems which mainly consists of FPGA chipset, two
DDR3 and QSPI FLASH. The expansion board extends the many peripheral
interface for core board, which contains SFP fiber interface, gigabit Ethernet
network port, USB2.0 port, VGA port and etc.
Figure 1-2 provides a quick overview of the block diagram of AX7102 board.
VGA Port
LED*4
CP2102
USB
UART
40-Pin Header
RTL8211E
Etherne
t
SFP Module
SFP Module
Button*4
40-Pin Header
ADV7123 MAX3232
RS232 USB2.0
CY7C68013
SD Card
JTAG
XILINX
ARTIX-7
FPGA
200Mhz
148.5Mhz
DDR3
DDR3
QSPI
FLASH
Core
Board
Figure 1-2 AX7102 Block Diagram

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The following hardware resources are provided on the AX7102 board:
Features of FPGA Core Board:
FPGA Device
XILINX ARTIX-7 FPGA XC7A100T ;
101,440 Logic Cells;
240 DSP48 Slices include 18 x 18 multiplier, an adder, and accumulator;
4860Kb Block RAM Blocks;
Memory
2pcs 4Gbit(256M x 16bit) DDR3 memory make up to 8Gbit size in total.
128 Mb QSPI FLASH.
CLOCK
200Mhz differential crystal oscillator for system clock.
148.5MHz differential crystal oscillator for GTP transceiver.
Features of FPGA Expansion Board:
Communication
10/100/1000 Ethernet;
Two Port of SFP Interface.
USB2.0 Port;
USB-to-Serial port;
RS232 Serial Port;
Real-Time Clock;
EEPROM with I2C interface;
Micro SD Socket;
Connectors
Two 40pin Expansion Headers(it can connect 4.3' LCD module, ADDA
module, Audio module etc.);
10pin 2.54mm JTAG connector;
Display

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24-bit DAC of VGA output ;
Buttons and Indicators
5 User LEDs and (one is on core board);
5 user Buttons (one button acts as reset button on core board);
二、 FPGA Core Board
(一)Overview
AC7100 (P/N of Core Board) is a high performance core board using XILINX
Artix-7 XC7A100T-2FGG484I chipset. Two DDR3 memory is connected to FPGA
with 32bit data width and one 128Mbit QSPI FLASH is used for storage of FPGA
bitstreams or application code.
About 180 IOs (include 86 pairs LVDS signals) and signals of GTP transceivers
are extended to expansion board using board-on-board connector. The core
board is very small of 45*55 (mm) size, it will be a good choice to use this core
board in project which need a lot of IOs and space limitation.
Figure 2-1-1 and Figure 2-1-2 shows the top view and bottom view of the FPGA
Core board.

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Figure2-1-1 AC7100 TOP View
Figure 2-1-2 AC7100 Bottom View
(二)FPGA
AC7100 Core board uses Xilinx Artix-7 FPGA device, the detail part number is

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XC7A100T-2FGG484I. The Xilinx Artix-7 FPGA ordering information is shown in
Figure 2-2-1.
Figure 2-2-1 Artix-7 Ordering Information
Figure 2-2-2 shows the FPGA chipset on AC7100 core board.
Figure 2-2-2 FPGA Chipset
The feature summary of XC7A100T is listed as following:
Items
Parameters
Logic Cells
101440
Slices
15850
Max Distributed RAM(Kb)
1188
Block RAM（kb）
4860
DSP48E1 Slices
240

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CMTs
6
PCIe Gen2
1
XADC
1个12bit, 1Mbps AD
GTP Transceiver
4个，6.6Gb/s max
Speed
-2
Operation Temperate
-40 ~ 85degree
FPGA Power Supply
Artix-7 FPGA has six power supplies including VCCINT, VCCBRAM, VCCAUX, VCCO,
VMGTAVCC and VMGTAVTT. VCCINT is the core power supply of FPGA and should be
connected to +1.0V. VCCBRAM is power supply of FPGA Block RAM and also
should be connected to +1.0V. VCCAUX is FPGA auxiliary power supply and should
be connected to +1.8V. VCCO is each BANK power supply, because the IOs of
FPGA bank35 is connected to the DDR3, the VCCO voltage of bank35 should be
+1.5V. VCCO of Bank15 and Bank16 is power from a LDO chipset, so the voltage
of these two bank can be changed if we use different LDO chipset. VMGTAVCC is
the power supply of GTP transceiver, it should be connected to +1.0V. VMGTAVTT is
terminal power supply of the GTP transceiver, and should be connected to the
+1.2V.
The Artix-7 FPGA has the Power-On/Off Power supply sequencing, the
recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve
minimum current draw and ensure that the I/Os are 3-stated at power-on. The
recommended power-off sequence is the reverse of the power-on.
(三)CLOCK
AC7100 core board is equipped with two Sitime differential crystal oscillators ,
one is 200Mhz differential crystal oscillator for FPGA system clock, another is
148.5Mhz differential crystal oscillator for GTP transceiver.
1). 200Mhz Differential Crystal Oscillator
The Figure 2-3-1 is the circuit of 200Mhz system clock, the output of differential
crystal oscillator is connected to global clock pin MRCC (R4 and T4) of FPGA.

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This 200Mhz system clock can produce different frequency clock to drive the
user logic thought PLLs and DCMs inside FPGA.
Figure 2-3-1 200Mhz System Clock
Figure 2-3-2 shows the onboard 200Mhz differential crystal oscillator
Figure 2-3-2 Onboard 200Mhz Crystal Oscillator
Clock Pin Assignment.
Net Name
FPGA PIN
SYS_CLK_P
R4
SYS_CLK_N
T4

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2). 148.5Mhz Differential Crystal Oscillator
The Figure 2-3-3 is the circuit of 148.5Mhz clock for GPT transceiver. The output
of differential crystal oscillator is connected to MGTREFCLK0P pin(F6) and
MGTREFCLK0N pin(E6) of FPGA bank216.
Figure 2-3-3 148.5Mhz Differential Crystal Oscillators
Figure 2-3-4 shows the onboard 148.5Mhz differential crystal oscillator.
图2-3-4 Onboard 148.5Mhz Crystal Oscillator
Clock Pin Assignment.
Net Name
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6

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(四)DDR3
The core board features 1GB of DDR3 memory, implemented using two 512MB
DDR3 devices. The data bandwidth is in 32-bit, comprised of two x16 devices
with a single address/command bus. the target clock speed for FPGA and DDR3
is 800 MHz(Data rate is 1600M). The part number of equipped two DDR3
devices is Micron MT41J256M16HA-125 which is compatible with
MT41K256M16HA-125. Detail information of DDR3 SDRAM is shown in table
2-4-1 below.
Table 2-4-1 DDR3 SDRAM Information
Part
P/N
Capacity
Vender
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
Connections between FPGA and DDR3 are shown in Figure 2-4-1.
FPGA
DDR3
(MT41J256M16
HA)
Data[31:16]
U5
U1
BANK
34/35
DDR3
(MT41J256M16
HA)
U6
Data[15:0]
Addr/control
Figure 2-4-1 Connections between FPGA and DDR3
Figure 2-4-2 shows onboard two DDR3 SDRAM.

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Figure 2-4-2 DDR3 SDRAM Onboard
DDR3 SDRAM PIN Assignment：
Net Name
FPGA PIN Name
FPGA P/N
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
E1
DDR3_DQS0_N
IO_L3N_T0_DQS_AD5N_35
D1
DDR3_DQS1_P
IO_L9P_T1_DQS_AD7P_35
K2
DDR3_DQS1_N
IO_L9N_T1_DQS_AD7N_35
J2
DDR3_DQS2_P
IO_L15P_T2_DQS_35
M1
DDR3_DQS2_N
IO_L15N_T2_DQS_35
L1
DDR3_DQS3_P
IO_L21P_T3_DQS_35
P5
DDR3_DQS3_N
IO_L21N_T3_DQS_35
P4
DDR3_DQ[0]
IO_L2P_T0_AD12P_35
C2
DDR3_DQ [1]
IO_L5P_T0_AD13P_35
G1
DDR3_DQ [2]
IO_L1N_T0_AD4N_35
A1
DDR3_DQ [3]
IO_L6P_T0_35
F3

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DDR3_DQ [4]
IO_L2N_T0_AD12N_35
B2
DDR3_DQ [5]
IO_L5N_T0_AD13N_35
F1
DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2

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DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3
DDR3_A[6]
IO_L5P_T0_34
W1
DDR3_A[7]
IO_L1P_T0_34
T1
DDR3_A[8]
IO_L2N_T0_34
V2
DDR3_A[9]
IO_L2P_T0_34
U2
DDR3_A[10]
IO_L5N_T0_34
Y1
DDR3_A[11]
IO_L4P_T0_34
W2
DDR3_A[12]
IO_L4N_T0_34
Y2
DDR3_A[13]
IO_L1N_T0_34
U1
DDR3_A[14]
IO_L6N_T0_VREF_34
V3
DDR3_BA[0]
IO_L9N_T1_DQS_34
AA3
DDR3_BA[1]
IO_L9P_T1_DQS_34
Y3
DDR3_BA[2]
IO_L11P_T1_SRCC_34
Y4
DDR3_S0
IO_L8P_T1_34
AB3
DDR3_RAS
IO_L12P_T1_MRCC_34
V4
DDR3_CAS
IO_L12N_T1_MRCC_34
W4
DDR3_WE
IO_L7P_T1_34
AA1
DDR3_ODT
IO_L14N_T2_SRCC_34
U5
DDR3_RESET
IO_L15P_T2_DQS_34
W6
DDR3_CLK_P
IO_L3P_T0_DQS_34
R3
DDR3_CLK_N
IO_L3N_T0_DQS_34
R2
DDR3_CKE
IO_L14P_T2_SRCC_34
T5
(五)QSPI Flash
The board is assembled with 128Mbit of QSPI flash memory using an 4-bit data

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bus. The flash device is N25Q128 which uses 3.3V CMOS signaling standard.
Because of its non-volatile property, it is usually used for storing software
binaries, images, sounds or other media. Detail information of QSPI FLASH is
shown in table 2-5-1 below.
Part
P/N
Capacity
Vender
U8
N25Q128
128M Bit
Numonyx
Table 2-5-1 QSPI Flash Information
Connections between FPGA and Flash are shown in Figure 2-5-1.
Figure 2-5-1 Connections between FPGA and Flash
Pin Assignment of FLASH：
Net Name
FPGA PIN Name
FPGA P/N
QSPI_CLK
CCLK_0
L12
QSPI_CS
IO_L6P_T0_FCS_B_14
T19
QSPI_DQ0
IO_L1P_T0_D00_MOSI_14
P22
QSPI_DQ1
IO_L1N_T0_D01_DIN_14
R22
QSPI_DQ2
IO_L2P_T0_D02_14
P21
QSPI_DQ3
IO_L2N_T0_D03_14
R21

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Figure 2-5-2 shows onboard QSPI FLASH.
Figure 2-5-2 QSPI FLASH Onboard
(六)LEDs
There are three RED LEDs on the FPGA, it includes power indicator LED, done
indicator LED and user LED. When the core board is power on, the power
indicator LED turns on. when the FPGA configuration is configured, the done
LED will be on. The user LED is driven directly by a pin of FPGA, driving its
associated pin to a high logic level turns the LED on, and driving the pin low
turns it off.
The schematic diagram of the hardware connection of the LED is shown in
Figure 2-6-1:
Figure 2-6-1 Connections between the LEDs and FPGA
Figure 2-6-2 is the LEDs on AC7100 board.

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Figure 2-6-2 LEDs on AC7100 board
Pin Assignment of User LED
Net Name
FPGAPIN Name
FPGA P/N
Comment
LED1
IO_L15N_T2_DQS_34
W5
User LED
(七)RESET Button
AC7100 core board has a reset button, it is connected to the bank34 IO of FPGA.
User can use this button to initialize the FPGA program. when reset button is
pressed, the reset signal to FPGA is low and the reset is valid. When the button
is not pressed, the reset signal is high.
The schematic diagram of the reset button connection is shown in Figure 2-7-1
Figure 2-7-1 Connections between the button and FPGA
Figure 2-7-2 is the reset button on AC7100 board