abaco systems PPC11A Quick user guide

Hardware Reference Manual
PPC11A 6U VME Single Board Computer
Edition 1
Publication No. PPC11A-HRM/1

2 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Document History
Edition Date Comments
1 March 2018 Board artwork revision 2
Waste Electrical and Electronic Equipment (WEEE) Returns
Abaco Systems Limited is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of Directive 2012/19/EU of the European Parliament of
4 July 2012 on Waste Electrical and Electronic Equipment.
Abaco Systems Limited will evaluate requests to take back products purchased by our customers
before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. PPC11A-HRM/1 About This Manual 3
About This Manual
This manual contains hardware information for the Abaco Systems PPC11A SBC.
The information contained in this manual must be read in conjunction with the
PowerX Family Hardware Product Manual.
LINK
PowerX Range of SBCs Hardware Reference Manual, publication number PPC-0HH.
NOTES
Cross-document links are intended for use where the document files are saved under their original file
names in the same directory on a server, PC hard drive, or similar. If you are accessing this document via
the Abaco website, cross-document links will not work.
If you are accessing this document in hard copy or downloaded form, check the Abaco website to ensure
that you have the latest version.
Further Information
Abaco Website
You can find information on Abaco products on the following website:
LINK
https://www.abaco.com
Abaco Documents
You may register for access to manuals via the website whose link is given above.
LINKS
PMC/XMC Installation Application Note, publication number HN4/5-16.
P0P2X605 Product Manual, publication number P0P2X605-HRM.
I/O Modules Hardware Reference Manual, publication number RT5154-0HH.
FBIT for PPC11A Software Reference Manual, publication number FBIT-PPC11A-SRM.
NOTE
Cross-document links are intended for use where the document files are saved under their original file
names in the same directory on a server, PC hard drive, or similar. If you are accessing this document via
the Abaco website, cross-document links will not work.
If you are accessing this document in hard copy or downloaded form, check the Abaco website to ensure
that you have the latest version.

4 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Third Party Websites
Manufacturers of many of the devices used on the PPC11A maintain FTP sites or
websites. Some useful sites are:
http://www.vita.com
For VITA and ANSI/VITA standards.
http://www.ieee.com
For IEEE standards.
http://www.pcisig.org
For PCI Bus standards.
http://www.freescale.com/
For Processor information.
http://www.idt.com/
For PCIe Switch and VME Bridge information.
NOTE
You may need to register to access standards.
Third Party Documents
Due to the complexity of some of the parts used on the PPC11A, it is not possible to
include the data on all such devices in this manual. A list of the specifications and
data sheets that provide any additional information required follows:
Specifications
IEEE 1101.1-1998 IEEE Standard for Mechanical Core Specifications for
Microcomputers.
IEEE 1101.2-1992
Conduction cooled VME mechanics.
IEEE 1101.10-1996
Additional Mechanical Specifications.
ANSI/VITA 20-2001
Conduction Cooled PMC.
ANSI/VITA 32-2003
Processor PMC.
ANSI/VITA 39-2003
PCI-X for PMC and Processor PMC.
ANSI/VITA42.0-2008
XMC.
ANSI/VITA 42.3-2006
XMC PCIe Protocol Layer Standard.
ANSI/VITA 1.0-1994
VME64 Standard.
ANSI/VITA 1.1-1997
VME64x Extensions.
ANSI/VITA 31.1-2003
Gigabit Ethernet on VME64x Backplanes.
PCI Local Bus Specification Revision 2.1, PCI Special Interest Group.
These are the latest versions at time of writing; check associated web sites for later
updates.
NOTE
You may need to register to access these specifications.

Publication No. PPC11A-HRM/1 About This Manual 5
Component
Information QorIQ T1042, T1022 Data Sheet, NXP
T1040 QorIQ Advanced Multiprocessing Processor Reference Manual, NXP
QorIQ T2080 Reference Manual, NXP
T2081 QorIQ Integrated Multicore Communications Processor Reference Manual,
NXP
Universe IID User Manual, IDT
PCI Total-ACE Data Sheet, DDC
XR17V358 High Performance Octal PCIe UART, EXAR
PEX8619 BA Data Book, Broadcom (PLX)
MachXO2 FPGA Datasheet, Lattice
Safety Notices
Cooling
CAUTION
The PPC11A requires air-flow of at least 300 lfm for build levels 1 and 2, and at least 600 lfm for build
level 3. If a conduction-cooled (level 4 or 5) PPC11A is operating on an extender card, it requires air-flow of
at least 300 lfm across it.
Handling
CAUTION
Only handle the PPC11A by the edges or front panel
ESD Label (Present on Board Packaging)
Heatsink
CAUTIONS
Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so users
should have no reason to remove it.
Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws
attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage
components beneath it. Removal and re-attachment of the heatsink should only be carried out by Abaco.

6 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Contents
1 • Unpacking............................................................................................................................... 16
1.1 Box Contents Checklist....................................................................................................................................... 16
1.2 Identifying Your Board ........................................................................................................................................ 16
2 • Configuration.......................................................................................................................... 18
2.1 Link Configuration ............................................................................................................................................... 18
2.2 Inspection ............................................................................................................................................................ 19
2.3 Configuration Link Descriptions......................................................................................................................... 19
2.3.1 Boot Area Selection Link (P15 Pins 1 to 4)....................................................................................................................19
2.3.2 NVRAM Write Enable Link (P15 Pins 5 and 6)...............................................................................................................20
2.3.3 Flash Protection Unlock Link (P15 Pins 7 and 8)..........................................................................................................20
2.3.4 Configuration Write Enable Link (P15 Pins 9 and 10)...................................................................................................20
2.3.5 PMC1 & PMC2 5V VIO Selection Links (P15 Pins 13 to 16) .........................................................................................21
2.3.6 Reserved Links (P17 and P18) .......................................................................................................................................21
2.4 Software Board Configuration............................................................................................................................ 21
2.5 Mezzanine Installation........................................................................................................................................ 22
3 • Installation and Power Up/Reset........................................................................................... 24
3.1 Power Supply Requirements .............................................................................................................................. 24
3.2 Board Installation Notes..................................................................................................................................... 24
3.3 Connecting to PPC11A ....................................................................................................................................... 25
3.3.1 Rear Transition Module ..................................................................................................................................................25
3.4 Reset and Power-up Sequence .......................................................................................................................... 25
4 • Functional Description ........................................................................................................... 26
4.1 Introduction ......................................................................................................................................................... 26
4.2 Features ............................................................................................................................................................... 29
4.3 Integrated Host Processor ................................................................................................................................. 30
4.3.1 Processor Features.........................................................................................................................................................30
4.3.2 PowerPC Processing Cores............................................................................................................................................30
4.3.3 Trust Architecture ...........................................................................................................................................................30
4.3.4 Memory Map....................................................................................................................................................................31
4.3.5 Reset Configuration Word ..............................................................................................................................................31
4.3.6 Processor Power Management......................................................................................................................................31
4.3.7 Local Bus .........................................................................................................................................................................32
4.4 SDRAM ................................................................................................................................................................. 33
4.4.1 Capacity ...........................................................................................................................................................................33
4.4.2 Serial Presence Detect....................................................................................................................................................33
4.5 NOR Flash ............................................................................................................................................................ 33
4.5.1 Boot Flash........................................................................................................................................................................34
4.5.2 User Flash........................................................................................................................................................................34
4.5.3 Paged Flash Mode ..........................................................................................................................................................34
4.5.4 Flash Sector Protection ..................................................................................................................................................34
4.6 SPI Serial Recovery Flash................................................................................................................................... 35
4.7 NAND Flash Solid State Drive ............................................................................................................................ 35
4.8 NVSRAM .............................................................................................................................................................. 35
continued overleaf

Publication No. PPC11A-HRM/1 Contents 7
4 • Functional Description (continued)
4.9 VME Interface ...................................................................................................................................................... 36
4.9.1 VMEbus Compliance.......................................................................................................................................................36
4.9.2 VMEbus Master Access..................................................................................................................................................37
4.9.3 VMEbus Slave Access ....................................................................................................................................................37
4.9.4 Indivisible cycles on VME ...............................................................................................................................................37
4.9.5 VMEbus Arbitration and Slot 1 functions......................................................................................................................37
4.9.6 VMEbus Master Block Transfers (DMA)........................................................................................................................38
4.9.7 VMEbus Slave Block Transfers ......................................................................................................................................38
4.9.8 VMEbus Interrupts ..........................................................................................................................................................38
4.9.9 VMEbus Errors.................................................................................................................................................................38
4.9.10 VMEbus Retries.............................................................................................................................................................39
4.10 I/O....................................................................................................................................................................... 39
4.11 Ethernet.............................................................................................................................................................. 40
4.12 Serial Communication Ports ............................................................................................................................ 41
4.12.1 COM1 and COM2 ...........................................................................................................................................................41
4.12.2 COM3 to COM6..............................................................................................................................................................42
4.12.3 Host-to-BMM Serial Port...............................................................................................................................................43
4.13 USB..................................................................................................................................................................... 43
4.14 SATA................................................................................................................................................................... 44
4.15 GPIO ................................................................................................................................................................... 44
4.16 MIL-STD-1553.................................................................................................................................................... 46
4.17 Graphics............................................................................................................................................................. 47
4.17.1 VGA ................................................................................................................................................................................47
4.17.2 DVI..................................................................................................................................................................................47
4.18 Mezzanines........................................................................................................................................................ 48
4.18.1 PMC/XMC Sites.............................................................................................................................................................48
4.18.2 PMCs..............................................................................................................................................................................48
4.18.3 XMCs..............................................................................................................................................................................49
4.18.4 I/O Routing ....................................................................................................................................................................49
4.18.5 PMC/XMC Site 1 Configuration....................................................................................................................................49
4.18.6 PMC/XMC Site 2 Configuration....................................................................................................................................51
4.19 PCIe Infrastructure............................................................................................................................................ 52
4.19.1 Processor.......................................................................................................................................................................52
4.19.2 PCIe Switches................................................................................................................................................................53
4.20 I2C Buses............................................................................................................................................................ 55
4.20.1 Main Bus........................................................................................................................................................................55
4.20.2 Sensor and Backplane Buses.......................................................................................................................................56
4.20.3 I2C Bus 3 ........................................................................................................................................................................57
4.20.4 I2C Reset ........................................................................................................................................................................57
4.20.5 Processor Config EEPROM...........................................................................................................................................57
4.20.6 Elapsed Time Indicator .................................................................................................................................................57
4.20.7 DIP Switches .................................................................................................................................................................58
4.20.8 Real-Time Clock.............................................................................................................................................................59
4.20.9 Temperature Sensor .....................................................................................................................................................59
4.20.10 Motion Sensor.............................................................................................................................................................59
4.20.11 Power Manager ...........................................................................................................................................................59
4.21 Timers ................................................................................................................................................................ 60
4.21.1 Watchdog Timer............................................................................................................................................................60
4.21.2 AXIS Timer.....................................................................................................................................................................61
4.22 Baseboard Management Microcontroller ....................................................................................................... 61
4.23 Resets and Interrupts ....................................................................................................................................... 62
4.23.1 Hard Reset.....................................................................................................................................................................62
4.23.2 External Interrupt ..........................................................................................................................................................63

8 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
4 • Functional Description (continued)
4.24 FPGA .................................................................................................................................................................. 64
4.24.1 Reset Configuration Word ............................................................................................................................................64
4.24.2 Timings ..........................................................................................................................................................................64
4.24.3 Serial Presence Detect..................................................................................................................................................64
4.24.4 AXIS Support .................................................................................................................................................................64
4.25 JTAG................................................................................................................................................................... 65
4.26 LEDs ................................................................................................................................................................... 66
4.26.1 DS10 and DS43 to DS45 (BIT) ......................................................................................................................................67
4.26.2 DS3 and DS4 (ETH0 Status) .........................................................................................................................................68
4.26.3 DS46 and DS47 (ETH1 Status).....................................................................................................................................68
4.27 Conduction-cooled Front Panel (Build Levels 4 and 5).................................................................................. 68
4.28 Air-cooled Front Panel (Build Levels 1 to 3).................................................................................................... 69
5 • Control and Status Registers................................................................................................. 70
5.1 Board ID Register (Offset 0x600) ....................................................................................................................... 72
5.2 Board Revision Register (Offset 0x601)............................................................................................................ 72
5.3 Master FPGA Revision Register (Offset 0x60B) ............................................................................................... 72
5.4 Slave FPGA Revision Register (Offset 0x60B).................................................................................................. 73
5.5 Board ID String Register 1 (Offset 0x610) to Board ID String Register 11 (Offset 0x61A)............................ 73
5.6 Reset Cause Register 1 (Offset 0x61B)............................................................................................................. 73
5.7 Reset Cause Register 2 (Offset 0x61C) ............................................................................................................. 74
5.8 BMM Control Register (Offset 0x620) ............................................................................................................... 74
5.9 LED Control Register 1 (Offset 0x622)............................................................................................................... 75
5.10 SPI Control Register (Offset 0x625) ................................................................................................................ 75
5.11 PCIe SATA SPI Control Register (Offset 0x626) ............................................................................................. 76
5.12 BIT Control/Status Register (Offset 0x629).................................................................................................... 76
5.13 NOR Flash Page Register (Offset 0x636)........................................................................................................ 77
5.14 AXIS Registers................................................................................................................................................... 77
5.14.1 AXIS Timestamp Registers 0 to 5 ................................................................................................................................77
5.14.2 AXIS Clock Frequency Register (Offset 0x64E) ..........................................................................................................77
5.14.3 AXIS Clock Control Register (Offset 0x64F)................................................................................................................78
5.15 Timer Registers ................................................................................................................................................. 78
5.15.1 Timer 0 Control/Status Register 1 (Offset 0x650), Timer 1 Control/Status Register 1 (Offset 0x658),
Timer 2 Control/Status Register 1 (Offset 0x660) and Timer 3 Control/Status Register 1 (Offset 0x668) ...........78
5.15.2 Timer 0 Control/Status Register 2 (Offset 0x651), Timer 1 Control/Status Register 2 (Offset 0x659),
Timer 2 Control/Status Register 2 (Offset 0x661) and Timer 3 Control/Status Register 2 (Offset 0x669) ...........79
5.15.3 Timer 0 Interrupt Clear Register (Offset 0x652), Timer 1 Interrupt Clear Register (Offset 0x65A),
Timer 2 Interrupt Clear Register (Offset 0x662) and Timer 3 Interrupt Clear Register (Offset 0x66A)...................79
5.15.4 Timer Data Byte Registers............................................................................................................................................80
5.16 GPIO (7-0) Registers.......................................................................................................................................... 81
5.16.1 GPIO (7-0) Out Register (Offset 0x670) .......................................................................................................................81
5.16.2 GPIO (7-0) In Register (Offset 0x671) ..........................................................................................................................81
5.16.3 GPIO (7-0) Direction Register (Offset 0x672) ..............................................................................................................81
5.16.4 GPIO (7-0) Interrupt Enable Register (Offset 0x673) ..................................................................................................81
5.16.5 GPIO (7-0) Interrupt Level/Edge Register (Offset 0x674) ...........................................................................................81
5.16.6 GPIO (7-0) Interrupt Polarity Register (Offset 0x675).................................................................................................81
5.16.7 GPIO (7-0) Interrupt Both Edges Register (Offset 0x676)...........................................................................................82
5.16.8 GPIO (7-0) Interrupt Status/Clear Register (Offset 0x677).........................................................................................82
5.16.9 GPIO (7-0) Availability Register (Offset 0x678) ...........................................................................................................82
5.16.10 GPIO (7-0) Interrupt Select Register (Offset 0x679) .................................................................................................82
5.16.11 GPIO (7-0) Interrupt Non-Maskable Register (Offset 0x67A) ...................................................................................82
5.16.12 GPIO (7-0) Test Mode Register (Offset 0x67B) .........................................................................................................83

Publication No. PPC11A-HRM/1 Contents 9
5 • Control and Status Registers (continued)
5.17 GPIO (15-8) Registers ....................................................................................................................................... 83
5.17.1 GPIO (15-8) Out Register (Offset 0x67C) .....................................................................................................................83
5.17.2 GPIO (15-8) In Register (Offset 0x67D)........................................................................................................................83
5.17.3 GPIO (15-8) Direction Register (Offset 0x67E) ............................................................................................................83
5.17.4 GPIO (15-8) Interrupt Enable Register (Offset 0x67F) ................................................................................................83
5.17.5 GPIO (15-8) Interrupt Level/Edge Register (Offset 0x680) .........................................................................................83
5.17.6 GPIO (15-8) Interrupt Polarity Register (Offset 0x681)...............................................................................................84
5.17.7 GPIO (15-8) Interrupt Both Edges Register (Offset 0x682).........................................................................................84
5.17.8 GPIO (15-8) Interrupt Status/Clear Register (Offset 0x683).......................................................................................84
5.17.9 GPIO (15-8) Availability Register (Offset 0x684).........................................................................................................84
5.17.10 GPIO (15-8) Interrupt Select Register (Offset 0x685) ...............................................................................................84
5.17.11 GPIO (15-8) Interrupt Non-Maskable Register (Offset 0x686) .................................................................................85
5.17.12 GPIO (15-8) Test Mode Register (Offset 0x687) .......................................................................................................85
5.18 GPIO (23-16) Registers ..................................................................................................................................... 85
5.18.1 GPIO (23-16) Out Register (Offset 0x688) ...................................................................................................................85
5.18.2 GPIO (23-16) In Register (Offset 0x689) ......................................................................................................................85
5.18.3 GPIO (23-16) Direction Register (Offset 0x68A)..........................................................................................................85
5.18.4 GPIO (23-16) Interrupt Enable Register (Offset 0x68B)..............................................................................................86
5.18.5 GPIO (23-16) Interrupt Level/Edge Register (Offset 0x68C).......................................................................................86
5.18.6 GPIO (23-16) Interrupt Polarity Register (Offset 0x68D) ............................................................................................86
5.18.7 GPIO (23-16) Interrupt Both Edges Register (Offset 0x68E) ......................................................................................86
5.18.8 GPIO (23-16) Interrupt Status/Clear Register (Offset 0x68F) ....................................................................................86
5.18.9 GPIO (23-16) Availability Register (Offset 0x690).......................................................................................................87
5.18.10 GPIO (23-16) Interrupt Select Register (Offset 0x691) .............................................................................................87
5.18.11 GPIO (23-16) Interrupt Non-Maskable Register (Offset 0x692) ...............................................................................87
5.18.12 GPIO (23-16) Test Mode Register (Offset 0x693) .....................................................................................................87
5.19 GPIO Availability Debug Register (Offset 0x694) ........................................................................................... 87
5.20 Availability Registers ........................................................................................................................................ 88
5.20.1 Ethernet Availability Register (Offset 0x6A0)..............................................................................................................88
5.20.2 COM Port Availability Register (Offset 0x6A1)............................................................................................................88
5.20.3 COM Port 4-Wire Configuration Register (Offset 0x6A2)............................................................................................89
5.20.4 COM Port Modem Configuration Register (Offset 0x6A3) .........................................................................................89
5.20.5 SATA Port Availability Register (Offset 0x6A4)...........................................................................................................89
5.20.6 USB2.0 Ports 7–0 Availability Register (Offset 0x6A5)..............................................................................................90
5.20.7 USB3.0 Ports 7–0 Availability Register (Offset 0x6A6)..............................................................................................90
5.20.8 USB2.0 Ports 15-8 Availability Register (Offset 0x6A7) .............................................................................................90
5.20.9 USB3.0 Ports 15-8 Availability Register (Offset 0x6A8) .............................................................................................90
5.20.10 Display Availability Register (Offset 0x6A9) .............................................................................................................90
5.20.11 VGA Availability Register (Offset 0x6AA) ..................................................................................................................91
5.20.12 DVI/HDMI Availability Register (Offset 0x6AB).........................................................................................................91
5.20.13 Display-Port Availability Register (Offset 0x6AC) .....................................................................................................91
5.20.14 Ancillary/Audio Availability Register (Offset 0x6AD)................................................................................................91
5.20.15 Front Panel Configuration Register (Offset 0x6AE)..................................................................................................92
5.20.16 XMC/PMC Site 1 I/O Configuration Register (Offset 0x6AF)...................................................................................92
5.20.17 XMC/PMC Site 2 I/O Configuration Register (Offset 0x6B0) ...................................................................................92
5.20.18 SSD Availability Register (Offset 0x6B1)...................................................................................................................93
5.21 SSD Secure Hardware Erase Capability Register (Offset 0x6B2) ................................................................. 93
5.22 COM Port Enable Register (Offset 0x6BB) ...................................................................................................... 93
5.23 COM Port Mode Register (Offset 0x6BC)........................................................................................................ 94
5.24 COM Port RS485 Auto-Direction Control Enable Register (Offset 0x6BD).................................................................... 94
5.25 COM Port Loopback Enable Register (Offset 0x6BE)..................................................................................... 94
5.26 SSD Erase Control Register (Offset 0x6BF) .................................................................................................... 95
5.27 SSD Cache Flush Control Register (Offset 0x6C0)......................................................................................... 95
5.28 Scratch Pad Register 1 (Offset 0x6C6) ........................................................................................................... 95

10 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
5 • Control and Status Registers (continued)
5.29 Test Register (Offset 0x6C7)............................................................................................................................ 96
5.30 XMC/PMC Site 1 Status Register (Offset 0x6C8)........................................................................................... 97
5.31 XMC/PMC Site 2 Status Register (Offset 0x6C9)........................................................................................... 98
5.32 Backplane Status Register (Offset 0x6CA) ..................................................................................................... 98
5.33 SSD Status Register (Offset 0x6CB)................................................................................................................ 99
5.34 Write Protection Status Register (Offset 0x6CC) ........................................................................................... 99
5.35 Jumper Link Status Register (Offset 0x6CD)................................................................................................ 100
5.36 Boot Location Status Register (Offset 0x6CE) ............................................................................................. 101
5.37 Thermal Status Register (Offset 0x6D0) ....................................................................................................... 101
5.38 Alarm Status Register (Offset 0x6D1)........................................................................................................... 102
5.39 Interrupt Controller Registers......................................................................................................................... 102
5.39.1 Interrupt Status Register (Low) (Offset 0x6E0)........................................................................................................ 103
5.39.2 Interrupt Status Register (High) (Offset 0x6E1)....................................................................................................... 103
5.39.3 Interrupt Enable Register (Low) (Offset 0x6E2) ....................................................................................................... 103
5.39.4 Interrupt Enable Register (High) (Offset 0x6E3) ...................................................................................................... 103
5.39.5 Interrupt Select Register (Low) (Offset 0x6E4) ........................................................................................................ 103
5.39.6 Interrupt Select Register (High) (Offset 0x6E5) ....................................................................................................... 103
5.39.7 Interrupt Non-Maskable Register (Low) (Offset 0x6E6) .......................................................................................... 103
5.39.8 Interrupt Non-Maskable Register (High) (Offset 0x6E7) ......................................................................................... 103
5.40 Availability/Configuration Register (Offset 0x6E8) ...................................................................................... 104
5.41 Reset Control Register (Offset 0x6E9) .......................................................................................................... 104
5.42 EEPROM DIP Switch 1 Configuration Register 0 (Offset 0x6EA) ................................................................ 105
5.43 EEPROM DIP Switch 1 Configuration Register 1 (Offset 0x6EB) ................................................................ 105
5.44 Configuration Unlock Password Register (Offset 0x6EC) ........................................................................... 106
5.45 Control Register (Offset 0x6ED)..................................................................................................................... 106
5.46 Scratch Pad Register 2 (Offset 0x6EE).......................................................................................................... 106
5.47 LED Control Register 2 (Offset 0x6EF) .......................................................................................................... 106
5.48 Flash Password Registers (Offsets 0x6F0 to 0x6F7) .................................................................................. 107
5.49 EEPROM DIP Switch 2 Configuration Register 1 (Offset 0x6FA) ................................................................ 107
5.50 EEPROM DIP Switch 2 Configuration Register 2 (Offset 0x6FB) ................................................................ 107
5.51 Watchdog Registers........................................................................................................................................ 107
5.51.1 Watchdog Configuration Register (Offset 0x700).................................................................................................... 107
5.51.2 Watchdog Prescaler (Low Byte) Register (Offset 0x701)........................................................................................ 108
5.51.3 Watchdog Enable Register (Offset 0x702) ............................................................................................................... 108
5.51.4 Watchdog Status Register (Offset 0x703) ............................................................................................................... 108
5.51.5 Watchdog Kick Register (Offset 0x704) ................................................................................................................... 109
5.51.6 Watchdog Interrupt Acknowledge Register (Offset 0x705) .................................................................................... 109
5.51.7 Watchdog Main Counter Low Byte Register (Offset 0x706) ................................................................................... 109
5.51.8 Watchdog Main Counter High Byte Register (Offset 0x707)................................................................................... 109
5.51.9 Watchdog Warning Timer Bits 8:1 Register (Offset 0x708) .................................................................................... 109
5.51.10 Watchdog Warning Timer Bits 16:9 Register (Offset 0x709) ................................................................................ 109
5.51.11 Watchdog Minimum Threshold Low Byte Register (Offset 0x70A)...................................................................... 110
5.51.12 Watchdog Minimum Threshold High Byte Register (Offset 0x70B)..................................................................... 110
5.51.13 Watchdog Warning Threshold Low Byte Register (Offset 0x70C)........................................................................ 110
5.51.14 Watchdog Warning Threshold High Byte Register (Offset 0x70D)....................................................................... 110
5.51.15 Watchdog Maximum Threshold Low Byte Register (Offset 0x70E) ..................................................................... 110
5.51.16 Watchdog Maximum Threshold High Byte Register (Offset 0x70F) .................................................................... 110
5.52 Scratchpad Memory Registers (Offset 0x720 to 0x72F) ............................................................................. 111
5.53 BMM UART Registers (Offsets 0x0 to 0x7)................................................................................................... 111