abaco systems PPC11A Quick user guide

Hardware Reference Manual
PPC11A 6U VME Single Board Computer
Edition 1
Publication No. PPC11A-HRM/1

2 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Document History
Edition Date Comments
1 March 2018 Board artwork revision 2
Waste Electrical and Electronic Equipment (WEEE) Returns
Abaco Systems Limited is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of Directive 2012/19/EU of the European Parliament of
4 July 2012 on Waste Electrical and Electronic Equipment.
Abaco Systems Limited will evaluate requests to take back products purchased by our customers
before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. PPC11A-HRM/1 About This Manual 3
About This Manual
This manual contains hardware information for the Abaco Systems PPC11A SBC.
The information contained in this manual must be read in conjunction with the
PowerX Family Hardware Product Manual.
LINK
PowerX Range of SBCs Hardware Reference Manual, publication number PPC-0HH.
NOTES
Cross-document links are intended for use where the document files are saved under their original file
names in the same directory on a server, PC hard drive, or similar. If you are accessing this document via
the Abaco website, cross-document links will not work.
If you are accessing this document in hard copy or downloaded form, check the Abaco website to ensure
that you have the latest version.
Further Information
Abaco Website
You can find information on Abaco products on the following website:
LINK
https://www.abaco.com
Abaco Documents
You may register for access to manuals via the website whose link is given above.
LINKS
PMC/XMC Installation Application Note, publication number HN4/5-16.
P0P2X605 Product Manual, publication number P0P2X605-HRM.
I/O Modules Hardware Reference Manual, publication number RT5154-0HH.
FBIT for PPC11A Software Reference Manual, publication number FBIT-PPC11A-SRM.
NOTE
Cross-document links are intended for use where the document files are saved under their original file
names in the same directory on a server, PC hard drive, or similar. If you are accessing this document via
the Abaco website, cross-document links will not work.
If you are accessing this document in hard copy or downloaded form, check the Abaco website to ensure
that you have the latest version.

4 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Third Party Websites
Manufacturers of many of the devices used on the PPC11A maintain FTP sites or
websites. Some useful sites are:
http://www.vita.com
For VITA and ANSI/VITA standards.
http://www.ieee.com
For IEEE standards.
http://www.pcisig.org
For PCI Bus standards.
http://www.freescale.com/
For Processor information.
http://www.idt.com/
For PCIe Switch and VME Bridge information.
NOTE
You may need to register to access standards.
Third Party Documents
Due to the complexity of some of the parts used on the PPC11A, it is not possible to
include the data on all such devices in this manual. A list of the specifications and
data sheets that provide any additional information required follows:
Specifications
IEEE 1101.1-1998 IEEE Standard for Mechanical Core Specifications for
Microcomputers.
IEEE 1101.2-1992
Conduction cooled VME mechanics.
IEEE 1101.10-1996
Additional Mechanical Specifications.
ANSI/VITA 20-2001
Conduction Cooled PMC.
ANSI/VITA 32-2003
Processor PMC.
ANSI/VITA 39-2003
PCI-X for PMC and Processor PMC.
ANSI/VITA42.0-2008
XMC.
ANSI/VITA 42.3-2006
XMC PCIe Protocol Layer Standard.
ANSI/VITA 1.0-1994
VME64 Standard.
ANSI/VITA 1.1-1997
VME64x Extensions.
ANSI/VITA 31.1-2003
Gigabit Ethernet on VME64x Backplanes.
PCI Local Bus Specification Revision 2.1, PCI Special Interest Group.
These are the latest versions at time of writing; check associated web sites for later
updates.
NOTE
You may need to register to access these specifications.

Publication No. PPC11A-HRM/1 About This Manual 5
Component
Information QorIQ T1042, T1022 Data Sheet, NXP
T1040 QorIQ Advanced Multiprocessing Processor Reference Manual, NXP
QorIQ T2080 Reference Manual, NXP
T2081 QorIQ Integrated Multicore Communications Processor Reference Manual,
NXP
Universe IID User Manual, IDT
PCI Total-ACE Data Sheet, DDC
XR17V358 High Performance Octal PCIe UART, EXAR
PEX8619 BA Data Book, Broadcom (PLX)
MachXO2 FPGA Datasheet, Lattice
Safety Notices
Cooling
CAUTION
The PPC11A requires air-flow of at least 300 lfm for build levels 1 and 2, and at least 600 lfm for build
level 3. If a conduction-cooled (level 4 or 5) PPC11A is operating on an extender card, it requires air-flow of
at least 300 lfm across it.
Handling
CAUTION
Only handle the PPC11A by the edges or front panel
ESD Label (Present on Board Packaging)
Heatsink
CAUTIONS
Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so users
should have no reason to remove it.
Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws
attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage
components beneath it. Removal and re-attachment of the heatsink should only be carried out by Abaco.

6 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Contents
1 • Unpacking............................................................................................................................... 16
1.1 Box Contents Checklist....................................................................................................................................... 16
1.2 Identifying Your Board ........................................................................................................................................ 16
2 • Configuration.......................................................................................................................... 18
2.1 Link Configuration ............................................................................................................................................... 18
2.2 Inspection ............................................................................................................................................................ 19
2.3 Configuration Link Descriptions......................................................................................................................... 19
2.3.1 Boot Area Selection Link (P15 Pins 1 to 4)....................................................................................................................19
2.3.2 NVRAM Write Enable Link (P15 Pins 5 and 6)...............................................................................................................20
2.3.3 Flash Protection Unlock Link (P15 Pins 7 and 8)..........................................................................................................20
2.3.4 Configuration Write Enable Link (P15 Pins 9 and 10)...................................................................................................20
2.3.5 PMC1 & PMC2 5V VIO Selection Links (P15 Pins 13 to 16) .........................................................................................21
2.3.6 Reserved Links (P17 and P18) .......................................................................................................................................21
2.4 Software Board Configuration............................................................................................................................ 21
2.5 Mezzanine Installation........................................................................................................................................ 22
3 • Installation and Power Up/Reset........................................................................................... 24
3.1 Power Supply Requirements .............................................................................................................................. 24
3.2 Board Installation Notes..................................................................................................................................... 24
3.3 Connecting to PPC11A ....................................................................................................................................... 25
3.3.1 Rear Transition Module ..................................................................................................................................................25
3.4 Reset and Power-up Sequence .......................................................................................................................... 25
4 • Functional Description ........................................................................................................... 26
4.1 Introduction ......................................................................................................................................................... 26
4.2 Features ............................................................................................................................................................... 29
4.3 Integrated Host Processor ................................................................................................................................. 30
4.3.1 Processor Features.........................................................................................................................................................30
4.3.2 PowerPC Processing Cores............................................................................................................................................30
4.3.3 Trust Architecture ...........................................................................................................................................................30
4.3.4 Memory Map....................................................................................................................................................................31
4.3.5 Reset Configuration Word ..............................................................................................................................................31
4.3.6 Processor Power Management......................................................................................................................................31
4.3.7 Local Bus .........................................................................................................................................................................32
4.4 SDRAM ................................................................................................................................................................. 33
4.4.1 Capacity ...........................................................................................................................................................................33
4.4.2 Serial Presence Detect....................................................................................................................................................33
4.5 NOR Flash ............................................................................................................................................................ 33
4.5.1 Boot Flash........................................................................................................................................................................34
4.5.2 User Flash........................................................................................................................................................................34
4.5.3 Paged Flash Mode ..........................................................................................................................................................34
4.5.4 Flash Sector Protection ..................................................................................................................................................34
4.6 SPI Serial Recovery Flash................................................................................................................................... 35
4.7 NAND Flash Solid State Drive ............................................................................................................................ 35
4.8 NVSRAM .............................................................................................................................................................. 35
continued overleaf

Publication No. PPC11A-HRM/1 Contents 7
4 • Functional Description (continued)
4.9 VME Interface ...................................................................................................................................................... 36
4.9.1 VMEbus Compliance.......................................................................................................................................................36
4.9.2 VMEbus Master Access..................................................................................................................................................37
4.9.3 VMEbus Slave Access ....................................................................................................................................................37
4.9.4 Indivisible cycles on VME ...............................................................................................................................................37
4.9.5 VMEbus Arbitration and Slot 1 functions......................................................................................................................37
4.9.6 VMEbus Master Block Transfers (DMA)........................................................................................................................38
4.9.7 VMEbus Slave Block Transfers ......................................................................................................................................38
4.9.8 VMEbus Interrupts ..........................................................................................................................................................38
4.9.9 VMEbus Errors.................................................................................................................................................................38
4.9.10 VMEbus Retries.............................................................................................................................................................39
4.10 I/O....................................................................................................................................................................... 39
4.11 Ethernet.............................................................................................................................................................. 40
4.12 Serial Communication Ports ............................................................................................................................ 41
4.12.1 COM1 and COM2 ...........................................................................................................................................................41
4.12.2 COM3 to COM6..............................................................................................................................................................42
4.12.3 Host-to-BMM Serial Port...............................................................................................................................................43
4.13 USB..................................................................................................................................................................... 43
4.14 SATA................................................................................................................................................................... 44
4.15 GPIO ................................................................................................................................................................... 44
4.16 MIL-STD-1553.................................................................................................................................................... 46
4.17 Graphics............................................................................................................................................................. 47
4.17.1 VGA ................................................................................................................................................................................47
4.17.2 DVI..................................................................................................................................................................................47
4.18 Mezzanines........................................................................................................................................................ 48
4.18.1 PMC/XMC Sites.............................................................................................................................................................48
4.18.2 PMCs..............................................................................................................................................................................48
4.18.3 XMCs..............................................................................................................................................................................49
4.18.4 I/O Routing ....................................................................................................................................................................49
4.18.5 PMC/XMC Site 1 Configuration....................................................................................................................................49
4.18.6 PMC/XMC Site 2 Configuration....................................................................................................................................51
4.19 PCIe Infrastructure............................................................................................................................................ 52
4.19.1 Processor.......................................................................................................................................................................52
4.19.2 PCIe Switches................................................................................................................................................................53
4.20 I2C Buses............................................................................................................................................................ 55
4.20.1 Main Bus........................................................................................................................................................................55
4.20.2 Sensor and Backplane Buses.......................................................................................................................................56
4.20.3 I2C Bus 3 ........................................................................................................................................................................57
4.20.4 I2C Reset ........................................................................................................................................................................57
4.20.5 Processor Config EEPROM...........................................................................................................................................57
4.20.6 Elapsed Time Indicator .................................................................................................................................................57
4.20.7 DIP Switches .................................................................................................................................................................58
4.20.8 Real-Time Clock.............................................................................................................................................................59
4.20.9 Temperature Sensor .....................................................................................................................................................59
4.20.10 Motion Sensor.............................................................................................................................................................59
4.20.11 Power Manager ...........................................................................................................................................................59
4.21 Timers ................................................................................................................................................................ 60
4.21.1 Watchdog Timer............................................................................................................................................................60
4.21.2 AXIS Timer.....................................................................................................................................................................61
4.22 Baseboard Management Microcontroller ....................................................................................................... 61
4.23 Resets and Interrupts ....................................................................................................................................... 62
4.23.1 Hard Reset.....................................................................................................................................................................62
4.23.2 External Interrupt ..........................................................................................................................................................63

8 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
4 • Functional Description (continued)
4.24 FPGA .................................................................................................................................................................. 64
4.24.1 Reset Configuration Word ............................................................................................................................................64
4.24.2 Timings ..........................................................................................................................................................................64
4.24.3 Serial Presence Detect..................................................................................................................................................64
4.24.4 AXIS Support .................................................................................................................................................................64
4.25 JTAG................................................................................................................................................................... 65
4.26 LEDs ................................................................................................................................................................... 66
4.26.1 DS10 and DS43 to DS45 (BIT) ......................................................................................................................................67
4.26.2 DS3 and DS4 (ETH0 Status) .........................................................................................................................................68
4.26.3 DS46 and DS47 (ETH1 Status).....................................................................................................................................68
4.27 Conduction-cooled Front Panel (Build Levels 4 and 5).................................................................................. 68
4.28 Air-cooled Front Panel (Build Levels 1 to 3).................................................................................................... 69
5 • Control and Status Registers................................................................................................. 70
5.1 Board ID Register (Offset 0x600) ....................................................................................................................... 72
5.2 Board Revision Register (Offset 0x601)............................................................................................................ 72
5.3 Master FPGA Revision Register (Offset 0x60B) ............................................................................................... 72
5.4 Slave FPGA Revision Register (Offset 0x60B).................................................................................................. 73
5.5 Board ID String Register 1 (Offset 0x610) to Board ID String Register 11 (Offset 0x61A)............................ 73
5.6 Reset Cause Register 1 (Offset 0x61B)............................................................................................................. 73
5.7 Reset Cause Register 2 (Offset 0x61C) ............................................................................................................. 74
5.8 BMM Control Register (Offset 0x620) ............................................................................................................... 74
5.9 LED Control Register 1 (Offset 0x622)............................................................................................................... 75
5.10 SPI Control Register (Offset 0x625) ................................................................................................................ 75
5.11 PCIe SATA SPI Control Register (Offset 0x626) ............................................................................................. 76
5.12 BIT Control/Status Register (Offset 0x629).................................................................................................... 76
5.13 NOR Flash Page Register (Offset 0x636)........................................................................................................ 77
5.14 AXIS Registers................................................................................................................................................... 77
5.14.1 AXIS Timestamp Registers 0 to 5 ................................................................................................................................77
5.14.2 AXIS Clock Frequency Register (Offset 0x64E) ..........................................................................................................77
5.14.3 AXIS Clock Control Register (Offset 0x64F)................................................................................................................78
5.15 Timer Registers ................................................................................................................................................. 78
5.15.1 Timer 0 Control/Status Register 1 (Offset 0x650), Timer 1 Control/Status Register 1 (Offset 0x658),
Timer 2 Control/Status Register 1 (Offset 0x660) and Timer 3 Control/Status Register 1 (Offset 0x668) ...........78
5.15.2 Timer 0 Control/Status Register 2 (Offset 0x651), Timer 1 Control/Status Register 2 (Offset 0x659),
Timer 2 Control/Status Register 2 (Offset 0x661) and Timer 3 Control/Status Register 2 (Offset 0x669) ...........79
5.15.3 Timer 0 Interrupt Clear Register (Offset 0x652), Timer 1 Interrupt Clear Register (Offset 0x65A),
Timer 2 Interrupt Clear Register (Offset 0x662) and Timer 3 Interrupt Clear Register (Offset 0x66A)...................79
5.15.4 Timer Data Byte Registers............................................................................................................................................80
5.16 GPIO (7-0) Registers.......................................................................................................................................... 81
5.16.1 GPIO (7-0) Out Register (Offset 0x670) .......................................................................................................................81
5.16.2 GPIO (7-0) In Register (Offset 0x671) ..........................................................................................................................81
5.16.3 GPIO (7-0) Direction Register (Offset 0x672) ..............................................................................................................81
5.16.4 GPIO (7-0) Interrupt Enable Register (Offset 0x673) ..................................................................................................81
5.16.5 GPIO (7-0) Interrupt Level/Edge Register (Offset 0x674) ...........................................................................................81
5.16.6 GPIO (7-0) Interrupt Polarity Register (Offset 0x675).................................................................................................81
5.16.7 GPIO (7-0) Interrupt Both Edges Register (Offset 0x676)...........................................................................................82
5.16.8 GPIO (7-0) Interrupt Status/Clear Register (Offset 0x677).........................................................................................82
5.16.9 GPIO (7-0) Availability Register (Offset 0x678) ...........................................................................................................82
5.16.10 GPIO (7-0) Interrupt Select Register (Offset 0x679) .................................................................................................82
5.16.11 GPIO (7-0) Interrupt Non-Maskable Register (Offset 0x67A) ...................................................................................82
5.16.12 GPIO (7-0) Test Mode Register (Offset 0x67B) .........................................................................................................83

Publication No. PPC11A-HRM/1 Contents 9
5 • Control and Status Registers (continued)
5.17 GPIO (15-8) Registers ....................................................................................................................................... 83
5.17.1 GPIO (15-8) Out Register (Offset 0x67C) .....................................................................................................................83
5.17.2 GPIO (15-8) In Register (Offset 0x67D)........................................................................................................................83
5.17.3 GPIO (15-8) Direction Register (Offset 0x67E) ............................................................................................................83
5.17.4 GPIO (15-8) Interrupt Enable Register (Offset 0x67F) ................................................................................................83
5.17.5 GPIO (15-8) Interrupt Level/Edge Register (Offset 0x680) .........................................................................................83
5.17.6 GPIO (15-8) Interrupt Polarity Register (Offset 0x681)...............................................................................................84
5.17.7 GPIO (15-8) Interrupt Both Edges Register (Offset 0x682).........................................................................................84
5.17.8 GPIO (15-8) Interrupt Status/Clear Register (Offset 0x683).......................................................................................84
5.17.9 GPIO (15-8) Availability Register (Offset 0x684).........................................................................................................84
5.17.10 GPIO (15-8) Interrupt Select Register (Offset 0x685) ...............................................................................................84
5.17.11 GPIO (15-8) Interrupt Non-Maskable Register (Offset 0x686) .................................................................................85
5.17.12 GPIO (15-8) Test Mode Register (Offset 0x687) .......................................................................................................85
5.18 GPIO (23-16) Registers ..................................................................................................................................... 85
5.18.1 GPIO (23-16) Out Register (Offset 0x688) ...................................................................................................................85
5.18.2 GPIO (23-16) In Register (Offset 0x689) ......................................................................................................................85
5.18.3 GPIO (23-16) Direction Register (Offset 0x68A)..........................................................................................................85
5.18.4 GPIO (23-16) Interrupt Enable Register (Offset 0x68B)..............................................................................................86
5.18.5 GPIO (23-16) Interrupt Level/Edge Register (Offset 0x68C).......................................................................................86
5.18.6 GPIO (23-16) Interrupt Polarity Register (Offset 0x68D) ............................................................................................86
5.18.7 GPIO (23-16) Interrupt Both Edges Register (Offset 0x68E) ......................................................................................86
5.18.8 GPIO (23-16) Interrupt Status/Clear Register (Offset 0x68F) ....................................................................................86
5.18.9 GPIO (23-16) Availability Register (Offset 0x690).......................................................................................................87
5.18.10 GPIO (23-16) Interrupt Select Register (Offset 0x691) .............................................................................................87
5.18.11 GPIO (23-16) Interrupt Non-Maskable Register (Offset 0x692) ...............................................................................87
5.18.12 GPIO (23-16) Test Mode Register (Offset 0x693) .....................................................................................................87
5.19 GPIO Availability Debug Register (Offset 0x694) ........................................................................................... 87
5.20 Availability Registers ........................................................................................................................................ 88
5.20.1 Ethernet Availability Register (Offset 0x6A0)..............................................................................................................88
5.20.2 COM Port Availability Register (Offset 0x6A1)............................................................................................................88
5.20.3 COM Port 4-Wire Configuration Register (Offset 0x6A2)............................................................................................89
5.20.4 COM Port Modem Configuration Register (Offset 0x6A3) .........................................................................................89
5.20.5 SATA Port Availability Register (Offset 0x6A4)...........................................................................................................89
5.20.6 USB2.0 Ports 7–0 Availability Register (Offset 0x6A5)..............................................................................................90
5.20.7 USB3.0 Ports 7–0 Availability Register (Offset 0x6A6)..............................................................................................90
5.20.8 USB2.0 Ports 15-8 Availability Register (Offset 0x6A7) .............................................................................................90
5.20.9 USB3.0 Ports 15-8 Availability Register (Offset 0x6A8) .............................................................................................90
5.20.10 Display Availability Register (Offset 0x6A9) .............................................................................................................90
5.20.11 VGA Availability Register (Offset 0x6AA) ..................................................................................................................91
5.20.12 DVI/HDMI Availability Register (Offset 0x6AB).........................................................................................................91
5.20.13 Display-Port Availability Register (Offset 0x6AC) .....................................................................................................91
5.20.14 Ancillary/Audio Availability Register (Offset 0x6AD)................................................................................................91
5.20.15 Front Panel Configuration Register (Offset 0x6AE)..................................................................................................92
5.20.16 XMC/PMC Site 1 I/O Configuration Register (Offset 0x6AF)...................................................................................92
5.20.17 XMC/PMC Site 2 I/O Configuration Register (Offset 0x6B0) ...................................................................................92
5.20.18 SSD Availability Register (Offset 0x6B1)...................................................................................................................93
5.21 SSD Secure Hardware Erase Capability Register (Offset 0x6B2) ................................................................. 93
5.22 COM Port Enable Register (Offset 0x6BB) ...................................................................................................... 93
5.23 COM Port Mode Register (Offset 0x6BC)........................................................................................................ 94
5.24 COM Port RS485 Auto-Direction Control Enable Register (Offset 0x6BD).................................................................... 94
5.25 COM Port Loopback Enable Register (Offset 0x6BE)..................................................................................... 94
5.26 SSD Erase Control Register (Offset 0x6BF) .................................................................................................... 95
5.27 SSD Cache Flush Control Register (Offset 0x6C0)......................................................................................... 95
5.28 Scratch Pad Register 1 (Offset 0x6C6) ........................................................................................................... 95

10 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
5 • Control and Status Registers (continued)
5.29 Test Register (Offset 0x6C7)............................................................................................................................ 96
5.30 XMC/PMC Site 1 Status Register (Offset 0x6C8)........................................................................................... 97
5.31 XMC/PMC Site 2 Status Register (Offset 0x6C9)........................................................................................... 98
5.32 Backplane Status Register (Offset 0x6CA) ..................................................................................................... 98
5.33 SSD Status Register (Offset 0x6CB)................................................................................................................ 99
5.34 Write Protection Status Register (Offset 0x6CC) ........................................................................................... 99
5.35 Jumper Link Status Register (Offset 0x6CD)................................................................................................ 100
5.36 Boot Location Status Register (Offset 0x6CE) ............................................................................................. 101
5.37 Thermal Status Register (Offset 0x6D0) ....................................................................................................... 101
5.38 Alarm Status Register (Offset 0x6D1)........................................................................................................... 102
5.39 Interrupt Controller Registers......................................................................................................................... 102
5.39.1 Interrupt Status Register (Low) (Offset 0x6E0)........................................................................................................ 103
5.39.2 Interrupt Status Register (High) (Offset 0x6E1)....................................................................................................... 103
5.39.3 Interrupt Enable Register (Low) (Offset 0x6E2) ....................................................................................................... 103
5.39.4 Interrupt Enable Register (High) (Offset 0x6E3) ...................................................................................................... 103
5.39.5 Interrupt Select Register (Low) (Offset 0x6E4) ........................................................................................................ 103
5.39.6 Interrupt Select Register (High) (Offset 0x6E5) ....................................................................................................... 103
5.39.7 Interrupt Non-Maskable Register (Low) (Offset 0x6E6) .......................................................................................... 103
5.39.8 Interrupt Non-Maskable Register (High) (Offset 0x6E7) ......................................................................................... 103
5.40 Availability/Configuration Register (Offset 0x6E8) ...................................................................................... 104
5.41 Reset Control Register (Offset 0x6E9) .......................................................................................................... 104
5.42 EEPROM DIP Switch 1 Configuration Register 0 (Offset 0x6EA) ................................................................ 105
5.43 EEPROM DIP Switch 1 Configuration Register 1 (Offset 0x6EB) ................................................................ 105
5.44 Configuration Unlock Password Register (Offset 0x6EC) ........................................................................... 106
5.45 Control Register (Offset 0x6ED)..................................................................................................................... 106
5.46 Scratch Pad Register 2 (Offset 0x6EE).......................................................................................................... 106
5.47 LED Control Register 2 (Offset 0x6EF) .......................................................................................................... 106
5.48 Flash Password Registers (Offsets 0x6F0 to 0x6F7) .................................................................................. 107
5.49 EEPROM DIP Switch 2 Configuration Register 1 (Offset 0x6FA) ................................................................ 107
5.50 EEPROM DIP Switch 2 Configuration Register 2 (Offset 0x6FB) ................................................................ 107
5.51 Watchdog Registers........................................................................................................................................ 107
5.51.1 Watchdog Configuration Register (Offset 0x700).................................................................................................... 107
5.51.2 Watchdog Prescaler (Low Byte) Register (Offset 0x701)........................................................................................ 108
5.51.3 Watchdog Enable Register (Offset 0x702) ............................................................................................................... 108
5.51.4 Watchdog Status Register (Offset 0x703) ............................................................................................................... 108
5.51.5 Watchdog Kick Register (Offset 0x704) ................................................................................................................... 109
5.51.6 Watchdog Interrupt Acknowledge Register (Offset 0x705) .................................................................................... 109
5.51.7 Watchdog Main Counter Low Byte Register (Offset 0x706) ................................................................................... 109
5.51.8 Watchdog Main Counter High Byte Register (Offset 0x707)................................................................................... 109
5.51.9 Watchdog Warning Timer Bits 8:1 Register (Offset 0x708) .................................................................................... 109
5.51.10 Watchdog Warning Timer Bits 16:9 Register (Offset 0x709) ................................................................................ 109
5.51.11 Watchdog Minimum Threshold Low Byte Register (Offset 0x70A)...................................................................... 110
5.51.12 Watchdog Minimum Threshold High Byte Register (Offset 0x70B)..................................................................... 110
5.51.13 Watchdog Warning Threshold Low Byte Register (Offset 0x70C)........................................................................ 110
5.51.14 Watchdog Warning Threshold High Byte Register (Offset 0x70D)....................................................................... 110
5.51.15 Watchdog Maximum Threshold Low Byte Register (Offset 0x70E) ..................................................................... 110
5.51.16 Watchdog Maximum Threshold High Byte Register (Offset 0x70F) .................................................................... 110
5.52 Scratchpad Memory Registers (Offset 0x720 to 0x72F) ............................................................................. 111
5.53 BMM UART Registers (Offsets 0x0 to 0x7)................................................................................................... 111

Publication No. PPC11A-HRM/1 Contents 11
6 • Connectors ........................................................................................................................... 112
6.1 Backplane Connectors...................................................................................................................................... 114
6.1.1 P0 Connector................................................................................................................................................................ 114
6.1.2 P1 Connector................................................................................................................................................................ 115
6.1.3 P2 Connector................................................................................................................................................................ 116
6.1.4 Backplane Signal Definitions....................................................................................................................................... 117
6.2 PMC Connectors................................................................................................................................................ 119
6.2.1 J11/J21 and J12/J22 Connectors.............................................................................................................................. 119
6.2.2 J13/J23 Connector ...................................................................................................................................................... 120
6.2.3 J14/J24 Connector ...................................................................................................................................................... 121
6.2.4 PMC Signal Descriptions ............................................................................................................................................. 122
6.3 XMC Connectors................................................................................................................................................ 123
6.3.1 J15/J25 Connector ...................................................................................................................................................... 123
6.3.2 J16 Connector .............................................................................................................................................................. 124
6.3.3 XMC Signal Descriptions ............................................................................................................................................. 125
6.4 Test and Programming Headers ...................................................................................................................... 126
6.4.1 P16 (Reserved) ............................................................................................................................................................. 126
6.4.2 P14 (Test Access Card Connector)............................................................................................................................. 126
A • Specifications....................................................................................................................... 127
A.1 Technical Specification .................................................................................................................................... 127
A.2 Electrical Specification..................................................................................................................................... 128
A.3 Reliability (MTBF).............................................................................................................................................. 129
A.4 Mechanical Specification................................................................................................................................. 129
A.5 Product Codes................................................................................................................................................... 130
A.6 Software Support .............................................................................................................................................. 131
A.6.1 Boot Firmware.............................................................................................................................................................. 131
A.6.2 Built In Test .................................................................................................................................................................. 131
A.6.3 Background Condition Screening ............................................................................................................................... 132
A.7 I/O Modules ....................................................................................................................................................... 132
A.8 Test Access Card .............................................................................................................................................. 132
A.9 Development Systems...................................................................................................................................... 132
B • Statement of Volatility......................................................................................................... 133
B.1 Volatile Memory ................................................................................................................................................ 133
B.2 Non-Volatile Memory ........................................................................................................................................ 133
C • PPCx Compatibility .............................................................................................................. 135
C.1 PPC4A ................................................................................................................................................................ 135
C.1.1 P0 Connector................................................................................................................................................................ 135
C.1.2 P1 Connector................................................................................................................................................................ 136
C.1.3 P2 Connector................................................................................................................................................................ 137
C.1.4 P2 Connector Alternative ............................................................................................................................................ 138
C.2 PPC7A ................................................................................................................................................................ 139
C.2.1 P0 Connector................................................................................................................................................................ 139
C.2.2 P1 Connector................................................................................................................................................................ 140
C.2.3 P2 Connector................................................................................................................................................................ 141
C.2.1 P2 Connector Alternative ............................................................................................................................................ 142
C.3 PPC7D ................................................................................................................................................................ 143
C.3.1 P0 Connector................................................................................................................................................................ 143
C.3.2 P0 Connector Alternative ............................................................................................................................................ 144
C.3.3 P1 Connector................................................................................................................................................................ 145
C.3.4 P2 Connector................................................................................................................................................................ 146
C.3.1 P2 Connector Alternative ............................................................................................................................................ 147

12 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
C • PPCx Compatibility (continued)
C.4 PPC10A .............................................................................................................................................................. 148
C.4.1 P0 Connector................................................................................................................................................................ 148
C.4.1 P0 Connector Alternative ............................................................................................................................................ 149
C.4.2 P1 Connector................................................................................................................................................................ 150
C.4.3 P2 Connector................................................................................................................................................................ 151
C.4.1 P2 Connector Alternative 1 ......................................................................................................................................... 152
C.4.1 P2 Connector Alternative 2 ......................................................................................................................................... 153
Glossary ..................................................................................................................................... 154
Index........................................................................................................................................... 155

Publication No. PPC11A-HRM/1 List of Tables 13
List of Tables
Table 2-1 P15 Pins 1 to 4 Jumper Functions............................................................................................................... 19
Table 2-2 P15 Pins 5 and 6 Jumper Function.............................................................................................................. 20
Table 2-3 P15 Pins 7 and 8 Jumper Function.............................................................................................................. 20
Table 2-4 P15 Pins 9 and 10 Jumper Function............................................................................................................ 20
Table 2-5 P15 Pins 13 and 14 Jumper Functions........................................................................................................ 21
Table 2-6 P15 Pins 15 and 16 Jumper Functions........................................................................................................ 21
Table 4-1 Processor Features ....................................................................................................................................... 30
Table 4-2 Processor Frequencies ................................................................................................................................. 30
Table 4-3 Local Bus Chip Select Targets...................................................................................................................... 32
Table 4-4 SDRAM Configuration ................................................................................................................................... 33
Table 4-5 Flash Details .................................................................................................................................................. 33
Table 4-6 VMEbus Compliance ..................................................................................................................................... 36
Table 4-7 Processor Network Interface Mapping........................................................................................................ 40
Table 4-8 ETH0/ETH1 Pin Mapping .............................................................................................................................. 40
Table 4-9 ETH2/ETH3 10/100/1000BASE-T Pin Mapping .......................................................................................... 41
Table 4-10 COM1/COM2 Signal Routing ...................................................................................................................... 41
Table 4-11 COM3 and COM4 Signal Routing ............................................................................................................... 42
Table 4-12 COM5 Signal Routing .................................................................................................................................. 43
Table 4-13 COM6 Signal Routing .................................................................................................................................. 43
Table 4-14 USB0/USB1 Signal Routing........................................................................................................................ 43
Table 4-15 SATA Signal Routing................................................................................................................................... 44
Table 4-16 GPIO Line Routing ....................................................................................................................................... 45
Table 4-17 MIL-STD-1553 Routing................................................................................................................................ 46
Table 4-18 VGA Routing................................................................................................................................................. 47
Table 4-19 DVI Routing .................................................................................................................................................. 47
Table 4-20 PMC/XMC Site 1 Signal Availability........................................................................................................... 50
Table 4-21 PMC Site 2 (1:46) Signal Availability.......................................................................................................... 51
Table 4-22 PMC Site 2 (47:64) Signal Availability ....................................................................................................... 51
Table 4-23 PCI and PCIe Bandwidths ........................................................................................................................... 52
Table 4-24 PCIe Switch 1 Connections ........................................................................................................................ 53
Table 4-25 PCIe Switch 1 Connections ........................................................................................................................ 53
Table 4-26 I2C Main Bus Addresses.............................................................................................................................. 55
Table 4-27 I2C Sensor Bus Addresses .......................................................................................................................... 56
Table 4-28 I2C Bus 3 Addresses .................................................................................................................................... 57
Table 4-29 PCA9560 Bit Meanings ............................................................................................................................... 58
Table 4-30 Power Manager Monitor Points ................................................................................................................. 59
Table 4-31 External Interrupt Inputs to Processor ...................................................................................................... 62
Table 4-32 Processor PCI INTx and External IRQ Sharing .......................................................................................... 63
Table 4-33 LED Functions.............................................................................................................................................. 67
Table 5-1 Control and Status Registers ....................................................................................................................... 70
Table 6-1 Connector Functions................................................................................................................................... 112

14 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
Table 6-2 P0 Pin Assignments .................................................................................................................................... 114
Table 6-3 P1 Pin Assignments .................................................................................................................................... 115
Table 6-4 P2 Pin Assignments .................................................................................................................................... 116
Table 6-5 Backplane Connector Signal Definitions ................................................................................................... 117
Table 6-6 J11/J21 Pin Assignments .......................................................................................................................... 119
Table 6-7 J12/J22 Pin Assignments .......................................................................................................................... 119
Table 6-8 J13/J23 Pin Assignments .......................................................................................................................... 120
Table 6-9 J14 Pin Assignments .................................................................................................................................. 121
Table 6-10 J24 Pin Assignments ................................................................................................................................ 121
Table 6-11 PMC Signal Descriptions .......................................................................................................................... 122
Table 6-12 J15/J25 Pin Assignments ........................................................................................................................ 123
Table 6-13 J16 Pin Assignments ................................................................................................................................ 124
Table 6-14 XMC Signal Descriptions .......................................................................................................................... 125
Table A-1 Technical Data............................................................................................................................................. 127
Table A-2 Voltage Supply Requirements.................................................................................................................... 128
Table A-3 Current Consumption.................................................................................................................................. 128
Table A-4 Reliability (MTBF)........................................................................................................................................ 129
Table A-5 Mechanical Construction ........................................................................................................................... 129
Table A-6 Product Options .......................................................................................................................................... 130
Table B-1 Volatile Memory .......................................................................................................................................... 133
Table B-2 Non-Volatile Memory .................................................................................................................................. 133

Publication No. PPC11A-HRM/1 List of Figures 15
List of Figures
Figure 1-1 Product Label (Packaging) .......................................................................................................................... 16
Figure 1-2 Product Label (Product) .............................................................................................................................. 16
Figure 1-3 Product Label (Conduction-cooled Product) ............................................................................................. 17
Figure 2-1 Link Positions ............................................................................................................................................... 18
Figure 2-2 PMC/XMC Site Locations............................................................................................................................ 22
Figure 4-1 PPC11A General View.................................................................................................................................. 26
Figure 4-2 Block Diagram (T2081) ................................................................................................................................ 27
Figure 4-3 Block Diagram (T1042) ................................................................................................................................ 28
Figure 4-4 Ethernet PHY Block Diagram....................................................................................................................... 40
Figure 4-5 RS422/485 Signal Definition....................................................................................................................... 41
Figure 4-6 I2C Main Bus Structure ................................................................................................................................ 55
Figure 4-7 I2C Sensor/Backplane Bus Structure.......................................................................................................... 56
Figure 4-8 I2C Bus 3 Structure....................................................................................................................................... 57
Figure 4-9 JTAG Chains ................................................................................................................................................. 65
Figure 4-10 LED Positions ............................................................................................................................................. 66
Figure 4-11 Conduction-cooled Front Panel ................................................................................................................ 68
Figure 4-12 0.8” Air-cooled Front Panel........................................................................................................................ 69
Figure 6-1 Front Connector Positions ........................................................................................................................ 112
Figure 6-2 Rear Connector Position............................................................................................................................ 113
Figure 6-3 RS422/485 Signal Waveforms.................................................................................................................. 118

16 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
1 • Unpacking
On receipt of the shipping container, if there is any evidence of physical damage, the
Terms and Conditions of Sale (provided with your delivery) give information on
what to do. If you need to return the product, contact Abaco.
The PPC11A is sealed into an antistatic bag and housed in a padded cardboard box.
Failure to use the correct packaging when storing or shipping the PPC11A may
invalidate the warranty.
1.1 Box Contents Checklist
•PPC11A in antistatic packaging.
•Embedded Software License Agreement (ABACO-SLA-001-01).
1.2 Identifying Your Board
The PPC11A is identified by labels at strategic positions. These can be cross-checked
against the Advice Note provided with your delivery.
Identification labels, like the example shown in Figure 1-1, attached to the shipping
box and the antistatic bag give identical information: product code, product
description, equipment number and board revision.
Figure 1-1 Product Label (Packaging)
On the board within the antistatic bag, there is an identifying label, like the example
shown in Figure 1-2, attached to the PCB.
Figure 1-2 Product Label (Product)
PPC11A-18C111B4
6U VME Single Board Computer (Level 1)
Equipment No:
Internal Ref:
Rev: 1A 1
Made in the U.K. Cage: K7034
10233351
10233351
1005065 5118
MADE IN UK
REV 1A1
CAG K7034
SER 10233351
PNR PPC11A-18C111B4

Publication No. PPC11A-HRM/1 Unpacking 17
On conduction-cooled versions of the board (build levels 4 and 5), there is also a
label, like the example shown in Figure 1-3, attached to the front of the heatsink.
Figure 1-3 Product Label (Conduction-cooled Product)
See the Product Codes section in Appendix A for more details on the product code
(PPC11A-xxxxxxxx).
PPC11A
CAGE CODE K7034
MADE IN UK
-48C111B4

18 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
2 • Configuration
2.1 Link Configuration
The PPC11A has push-on jumpers included in the standard kit of parts; additional
jumpers may be obtained on request. These are suitable for level 1 to 3 low vibration
applications.
TIP
For Level 4 and 5 products, make links by wire-wrapping between the pin posts and then cover these wire-
wrapped links with the same conformal coating as that used on the board (usually Acrylic 1B73AP - contact
Technical Support for details if needed). This will provide a reliable connection under heavy shock and
vibration conditions and further prevent oxidation of the connection due to moisture ingress.
Figure 2-1 Link Positions
The above diagram shows standard 2.54 mm pitch headers for general use.
This manual refers to jumper settings as In or Out. Meanings are as follows:
In = jumper fitted -
Out = jumper not fitted -

Publication No. PPC11A-HRM/1 Configuration 19
2.2 Inspection
The PPC11A is shipped from Abaco with no jumpers fitted.
2.3 Configuration Link Descriptions
NOTES
1. Ordinary operation does not require any jumpers to be fitted.
2. Software can read the states of most of the links from the Jumper Link Status Register (offset 0x6CD).
TIP
If you are about to install your PPC11A and power-up for the first time, leaving it in the default configuration
will enable board operation to be proven before tackling any further configuration issues.
2.3.1 Boot Area Selection Link (P15 Pins 1 to 4)
The Boot Flash (for all processing cores) is divided into two sections, allowing for
three different boot images to be loaded into the Flash. There is also an Abaco-
programmed Recovery boot image, which is stored in a separate SPI Flash. These
links are used to select which image is used at boot time.
Table 2-1 P15 Pins 1 to 4 Jumper Functions
Pins 1 and 2
Pins 3 and 4
Active Boot Image
Out Out Main
In Out Alternate
Out In Recovery
In
In
Reserved
In normal operation, jumpers are not fitted on these links and the PPC11A boots
from the Main boot image.
NOTES
When selected, using EEPROM DIP Switch 1 Register 1, GPIO6 has the same effect, when asserted high, as
fitting a jumper on pins 1 and 2 (Boot Alternate) and/or GPIO7 has the same effect, when asserted high, as
fitting a jumper on pins 3 and 4 (Boot Recovery).
The Alternate boot image can also be selected directly using the EEPROM DIP Switch 1 Register 1.

20 PPC11A 6U VME Single Board Computer Publication No. PPC11A-HRM/1
2.3.2 NVRAM Write Enable Link (P15 Pins 5 and 6)
This link controls the write protection for the NVRAM device on the PPC11A. This
device holds firmware boot parameters as well as user data.
Table 2-2 P15 Pins 5 and 6 Jumper Function
Setting Meaning
Out The NVRAM is write protected
In The NVRAM is write enabled
NOTES
The EEPROM DIP switch also plays a part in configuring the NVRAM write protection.
See the NVRAM section for details.
The backplane NVM_WE~ signal has the same effect, when asserted low, as fitting a jumper on this link.
The signals are ORed in the FPGA, so either may be used.
2.3.3 Flash Protection Unlock Link (P15 Pins 7 and 8)
Fitting a jumper on this link allows software to access the password to enable the
Flash persistent sector protection (which remains unchanged following a reset or a
power-cycle) to be altered. See the Flash Sector Protection section for more details.
Not fitting a jumper on this link prevents software from altering any previously
configured sector protection.
Table 2-3 P15 Pins 7 and 8 Jumper Function
Setting Meaning
Out Persistent sector protection cannot be altered
In Persistent sector protection can be altered
NOTE
When selected, using EEPROM DIP Switch 1 Register 1, GPIO5 has the same effect, when asserted high, as
fitting a jumper on this link. The backplane FLASH_PW_UL~ signal has the same effect, when asserted low.
The signals are ORed in the FPGA, so any may be used.
2.3.4 Configuration Write Enable Link (P15 Pins 9 and 10)
This link controls the write protection of the on-board non-volatile configuration
EEPROM devices. These are used to configure the initial state of the processor and
PCIe switches or board configuration options controlled by software.
Table 2-4 P15 Pins 9 and 10 Jumper Function
Setting Meaning
Out Configuration memory write-disabled
In Configuration memory write-enabled