abaco systems SBC329 3U VPX Quick user guide

Hardware Reference Manual
SBC329 3U VPX Single Board Computer
Edition 1
Publication No. SBC329-HRM/1

2SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
Document History
Edition
Date
Board Artwork Revision
1
August 2017
Rev 1
Waste Electrical and Electronic Equipment (WEEE) Returns
Abaco Systems Limited is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of Directive 2012/19/EU of the European Parliament of 4 July
2012 on Waste Electrical and Electronic Equipment.
Abaco Systems Limited will evaluate requests to take back products purchased by our customers
before August 13, 2005 on a case by case basis. A WEEE management fee may apply.

Publication No. SBC329-HRM/1 About This Manual 3
About This Manual
Conventions
Notices
This manual may use the following types of notice:
WARNING
Warnings alert you to the risk of severe personal injury.
CAUTION
Cautions alert you to system danger or loss of data.
NOTE
Notes call attention to important features or instructions.
TIP
Tips give guidance on procedures that may be tackled in several ways.
LINK
Links take you to other documents or websites. The purple link color may also be used within a
body of text or paragraph to indicate a link (or hyperlink) to a different part of the same
document.
Numbers
All numbers are expressed in decimal, except addresses and memory or register
data, which are expressed in hexadecimal. Where confusion may occur, decimal
numbers have a “D” subscript and binary numbers have a “b” subscript. The prefix
“0x” shows a hexadecimal number, following the ‘C’ programming language
convention. Thus:
One dozen = 12D= 0x0C = 1100b
The multipliers “k”, “M” and “G” have their conventional scientific and engineering
meanings of *103, *106and *109respectively. The only exception to this is in the
description of the size of memory areas, when “K”, “M” and “G” mean *210, *220 and
*230 respectively.
NOTE
When describing transfer rates, “k”, “M” and “G” mean *103, *106and *109not *210, *220 and *230.
Multiple bit fields are numbered from 0 to n, where 0 is the LSB and n is the MSB.

4SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
Text
Signal names ending with a tilde (“~”) denote active low signals; all other signals are
active high. “N” and “P” denote the low and high components of a differential signal
respectively.
Further Information
Abaco Systems Website
You can find information regarding Abaco products on the following website:
LINK
https://www.abaco.com
Abaco Documents
You may register for access to manuals via the website whose link is given above.
LINKS
XMC Installation Application Note, publication number HN4/5-16.
VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.
BIT for SBC329 Software Reference Manual, publication number FBIT-SBC329-SRM.
NOTES
Cross-document links are intended for use where the document files are saved under their
original file names in the same directory on a server, PC hard drive, or similar. If you are
accessing this document via the Abaco website, cross-document links will not work.
If you are accessing this document in hard copy or downloaded form, check the Abaco website
to ensure that you have the latest version.
Third Party Documents
Due to the complexity of some of the parts used on the SBC329, it is not possible to
include all the detailed data on all such devices in this manual. A list of the
specifications and data sheets that provide additional information follows:
IEEE 1101.1-1998
IEEE Standard for Mechanical Core Specifications for
Microcomputers.
IEEE 1101.2-1992
Conduction cooled VME mechanics.
IEEE 1101.10-1996
Additional Mechanical Specifications.
ANSI/VITA 42.0-2008
XMC.
ANSI/VITA 42.3-2006
XMC PCI Express Protocol Layer Standard.
ANSI/VITA 46.0-2007
VPX Baseline Standard.
VITA46.3-2012
Serial RapidIO on VPX.
VITA46.4-2012
PCI Express on VPX.

Publication No. SBC329-HRM/1 About This Manual 5
ANSI/VITA46.9-2010
XMC and PMC User I/O Mapping for VPX.
VITA 46.11 (Draft)
System Management on VPX.
ANSI/VITA65-2010
OpenVPX System Specification.
PCI Local Bus Specification Revision 2.1, PCI Special Interest Group.
These are the latest versions at time of writing; check associated web sites for later
updates.
NOTE
You may need to register to access these specifications.
Third Party Websites
Manufacturers of many of the devices used on the SBC329 maintain FTP or websites.
Some useful sites are:
http://www.vita.com
For VPX (VITA 46) and XMC (VITA 42) standards.
http://www.ieee.com
For IEEE standards.
http://www.pcisig.org
For PCI Bus standards.
http://www.intel.com
For processor, chip set and Ethernet controller
information.
http://www.plxtech.com
For PCIe switch device information.
http://www.latticesemi.com
For FPGA and PSU Monitor device information.
http://www.national.com
For LM92 temperature sensor device information.
http://www.maxim-ic.com
For Elapsed Time Indicator device information.
http://www.siliconmotion.com
For Solid State Drive information.
http://www.nxp.com
For DIP Switch and I2C buffer information.
http://www.molex.com
For connector information.
http://www.samtec.com
For connector information.
NOTE
You may need to register to access standards.

6SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
Technical Support
You can find technical assistance contact details on the web site Embedded Support
page.
LINK
https://www.abaco.com/embedded-support
Abaco will log your query on the Technical Support database and allocate it a
unique Case number for use in any future correspondence.
Alternatively, you may also contact Abaco’s Technical Support via:
LINK
Returns
If you need to return a product, there is a Return Materials Authorization (RMA)
tool available via the web site Embedded Support page.
LINK
https://www.abaco.com/embedded-support
Do not return products without first contacting the Abaco Repairs facility.

Publication No. SBC329-HRM/1 Contents 7
Contents
1 • Introduction ........................................................................................................ 15
1.1 Safety Notices ................................................................................................................................ 16
1.1.1 Flammability ................................................................................................................................................ 16
1.1.2 EMI/EMC Regulatory Compliance .............................................................................................................. 16
1.1.3 Cooling.......................................................................................................................................................... 17
1.1.4 Handling ....................................................................................................................................................... 17
1.1.5 Heatsink ....................................................................................................................................................... 17
2 • Unpacking........................................................................................................... 18
2.1 Box Contents Checklist .................................................................................................................. 18
2.2 Identifying Your Board.................................................................................................................... 18
3 • Configuration...................................................................................................... 20
3.1 Link Configuration .......................................................................................................................... 20
3.2 Inspection ....................................................................................................................................... 21
3.3 Link Descriptions............................................................................................................................ 21
3.3.1 Recovery Boot Link (P3).............................................................................................................................. 21
3.3.2 Configuration EEPROM Write Enable Link (P6)......................................................................................... 22
3.4 Mezzanine Installation ................................................................................................................... 23
4 • Installation and Power Up/Reset...................................................................... 25
4.1 Power Supply Requirements.......................................................................................................... 25
4.2 Board Keying .................................................................................................................................. 26
4.3 Board Installation Notes ................................................................................................................ 26
4.4 Connecting to SBC329 ................................................................................................................... 27
4.5 Reset and Power-up Sequence ...................................................................................................... 28
4.6 BIOS Setup Utility ........................................................................................................................... 28
4.7 First Boot Menu.............................................................................................................................. 29
4.8 About the Setup Menus.................................................................................................................. 30
4.9 Main Menu...................................................................................................................................... 31
4.10 Advanced Menu............................................................................................................................ 32
4.11 Chipset Menu................................................................................................................................ 33
4.12 Abaco Menu.................................................................................................................................. 34
4.12.1 Board Build Information ............................................................................................................................ 35
4.12.2 DIP Switch Setup ....................................................................................................................................... 36
4.12.3 FPGA Setup/Status ................................................................................................................................... 37
4.12.4 PLX Switch Setup/Status ......................................................................................................................... 38
4.12.5 Hardware Protection ................................................................................................................................. 40
4.12.6 CPU Speed Locking Configuration ........................................................................................................... 41
4.12.7 Enabling Booting Over a Network ............................................................................................................ 42
4.13 Security Menu............................................................................................................................... 43
4.14 Boot Menu .................................................................................................................................... 44
4.15 Save & Exit Menu.......................................................................................................................... 45

8SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
5 • Functional Description ...................................................................................... 46
5.1 Features.......................................................................................................................................... 47
5.2 Microprocessor Subsystem ........................................................................................................... 48
5.2.1 E3-1505M/L v6 Processor........................................................................................................................... 48
5.2.2 Mobile Intel CM238 Chipset (PCH)............................................................................................................. 49
5.2.3 Processor Debug Port ................................................................................................................................. 49
5.3 Memory........................................................................................................................................... 49
5.3.1 SDRAM ......................................................................................................................................................... 49
5.3.2 Boot Flash .................................................................................................................................................... 50
5.3.3 Flash Hard Drive .......................................................................................................................................... 50
5.3.4 NVRAM ......................................................................................................................................................... 51
5.4 VPX Interface.................................................................................................................................. 52
5.4.1 OpenVPX Compatibility............................................................................................................................... 52
5.4.2 REFCLK......................................................................................................................................................... 53
5.4.3 Module Maskable Reset.............................................................................................................................. 53
5.4.4 Global Discrete............................................................................................................................................. 53
5.5 I/O ................................................................................................................................................... 54
5.6 Data Plane Fabric ........................................................................................................................... 54
5.6.1 PCIe Gen3 Operation ................................................................................................................................... 55
5.7 Control Plane Fabric/Gigabit Ethernet........................................................................................... 55
5.7.1 BASE-T + BASE-BX Variant (SBC329-xxx1xxxxx)...................................................................................... 56
5.7.2 Dual BASE-T Variant (SBC329-xxx2xxxxx)................................................................................................. 57
5.8 GPIO ................................................................................................................................................ 57
5.9 PCIe Switch..................................................................................................................................... 58
5.9.1 Switch Configuration EEPROM................................................................................................................... 58
5.10 USB ............................................................................................................................................... 59
5.11 Serial Ports ................................................................................................................................... 60
5.11.1 RS422/RS485 Mode.................................................................................................................................. 61
5.12 SATA ............................................................................................................................................. 61
5.13 Video............................................................................................................................................. 62
5.14 LPC Bus ........................................................................................................................................ 63
5.14.1 FPGA........................................................................................................................................................... 63
5.14.2 Trusted Platform Monitor ......................................................................................................................... 63
5.15 Mezzanine Site ............................................................................................................................. 64
5.15.1 XMC Connectors........................................................................................................................................ 64
5.15.2 I/O Routing ................................................................................................................................................. 64
5.16 Real Time Clock............................................................................................................................ 66
5.17 I2C Bus .......................................................................................................................................... 66
5.17.1 EEPROM DIP Switch.................................................................................................................................. 67
5.17.2 SDRAM SPD EEPROM............................................................................................................................... 68
5.17.3 Elapsed Time Indicator ............................................................................................................................. 68
5.17.4 Accelerometer............................................................................................................................................ 68
5.18 Baseboard Management Microcontroller.................................................................................... 69
5.18.1 Board Temperature Sensor....................................................................................................................... 70
5.18.2 PMBus Devices .......................................................................................................................................... 71
5.19 Timers........................................................................................................................................... 72
5.19.1 General Purpose Timers............................................................................................................................ 72
5.19.2 Watchdog Timers ...................................................................................................................................... 72

Publication No. SBC329-HRM/1 Contents 9
5 • Functional Description (continued)
5.20 LEDs.............................................................................................................................................. 73
5.20.1 BIT LEDs (DS402 to DS404 and DS437) .................................................................................................. 74
5.20.2 Board Reset LED (DS405) ......................................................................................................................... 75
5.20.3 SSD Activity LED (DS408) ......................................................................................................................... 75
5.20.4 PCIe Link Status LEDs (DS409 to DS412) ............................................................................................... 75
5.20.5 POST Code LEDs (DS414 to DS421) ........................................................................................................ 76
5.20.6 Ethernet Link Status LEDs (DS422 and DS432 to DS436) ..................................................................... 76
5.20.7 SATA Activity LED (DS429)....................................................................................................................... 76
5.20.8 Board Power Good LED (DS430) .............................................................................................................. 76
5.20.9 Sleep Status LED (DS431) ........................................................................................................................ 76
5.20.10 BMM Status LED (DS438)....................................................................................................................... 76
5.21 Resets and Interrupts................................................................................................................... 77
5.21.1 Interrupt Controllers .................................................................................................................................. 77
5.21.2 Hardware Reset ......................................................................................................................................... 77
5.22 FPGA ............................................................................................................................................. 78
5.22.1 Registers .................................................................................................................................................... 78
5.22.2 AXIS Support.............................................................................................................................................. 78
5.23 Front Panel ................................................................................................................................... 79
6 • FPGA Registers .................................................................................................. 80
6.1 Board ID Register (0x600) .............................................................................................................. 81
6.2 Board Revision Register (0x601) ................................................................................................... 81
6.3 FPGA Revision Register (0x60B).................................................................................................... 81
6.4 Watchdog Timer Registers............................................................................................................. 82
6.5 Board ID String Registers (0x610 to 0x61A).................................................................................. 83
6.6 LED Control Register (0x622)......................................................................................................... 83
6.7 BIOS/SPI Control Register (0x625) ................................................................................................ 83
6.8 BIT Control and Status Register (0x629)....................................................................................... 84
6.9 NVRAM Memory Space Page Register (0x635) ............................................................................ 84
6.10 AXIS Registers.............................................................................................................................. 85
6.11 Timer Registers ............................................................................................................................ 86
6.11.1 Timer 0 Control and Status Register 1 (0x650) & Timer 1 Control and Status Register 1 (0x658)..... 86
6.11.2 Timer 0 Control and Status Register 2 (0x651) & Timer 1 Control and Status Register 2 (0x659)..... 86
6.11.3 Timer 0 IRQ Clear Register (0x652) and Timer 1 IRQ Clear Register (0x65A) ...................................... 86
6.12 Timer 0 Data Bytes 0 to 3 Registers (0x654 to 0x657)................................................................ 87
6.13 Timer 1 Data Bytes 0 to 3 Registers (0x65C to 0x65F) ............................................................... 88
6.14 GPIO Registers ............................................................................................................................. 89
6.14.1 GPIO Out Register (0x670)........................................................................................................................ 89
6.14.2 GPIO In Register (0x671)........................................................................................................................... 89
6.14.3 GPIO Direction Register (0x672) .............................................................................................................. 89
6.14.4 GPIO Interrupt Enable Register (0x673)................................................................................................... 89
6.14.5 GPIO Level/Edge Register (0x674)........................................................................................................... 89
6.14.6 GPIO Active Low/High Register (0x675).................................................................................................. 89
6.14.7 GPIO Both Edges Register (0x676) .......................................................................................................... 90
6.14.8 GPIO Interrupt Status Register (0x677) ................................................................................................... 90
6.14.9 GPIO7 to GPIO0 Availability Register (0x678)......................................................................................... 90
6.14.10 GPIO15 to GPIO8 Availability Register (0x684)..................................................................................... 90

10 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
6 • FPGA Registers (continued)
6.15 VPX GDISC1 Registers ................................................................................................................. 91
6.15.1 VPX GDISC1 Out Register (0x688) ........................................................................................................... 91
6.15.2 VPX GDISC1 In Register (0x689) .............................................................................................................. 91
6.15.3 VPX GDISC1 Direction Register (0x68A).................................................................................................. 91
6.15.4 VPX GDISC1 Interrupt Enable Register (0x68B)...................................................................................... 91
6.15.5 VPX GDISC1 Level/Edge Register (0x68C) .............................................................................................. 91
6.15.6 VPX GDISC1 Active Low/High Register (0x68D)..................................................................................... 91
6.15.7 VPX GDISC1 Both Edges Register (0x68E).............................................................................................. 92
6.15.8 VPX GDISC1 Interrupt Status Register (0x68F) ...................................................................................... 92
6.15.9 VPX GDISC1 Availability Register (0x690)............................................................................................... 92
6.16 Ethernet Port Availability Register (0x6A0) ................................................................................. 92
6.17 COM Port Availability Register (0x6A1) ....................................................................................... 93
6.18 COM Port 4-Wire Configuration Register (0x6A2) ....................................................................... 93
6.19 COM Port Modem Configuration Register (0x6A3) ..................................................................... 93
6.20 SATA Port Availability Register (0x6A4)...................................................................................... 94
6.21 USB2.0 Port 7 to 0 Availability Register (0x6A5)......................................................................... 94
6.22 USB3.0 Port 7 to 0 Availability Register (0x6A6)......................................................................... 95
6.23 USB2.0 Port 15 to 8 Availability Register (0x6A7)....................................................................... 95
6.24 USB3.0 Port 15 to 8 Availability Register (0x6A8)....................................................................... 95
6.25 Display Availability Register (0x6A9)........................................................................................... 95
6.26 VGA Display Availability Register (0x6AA) .................................................................................. 96
6.27 DVI/HDMI Display Availability Register (0x6AB) ......................................................................... 96
6.28 Display-Port Display Availability Register (0x6AC)...................................................................... 96
6.29 Ancillary/Audio Availability Register (0x6AD) ............................................................................. 96
6.30 Front Panel Configuration Register (0x6AE) ............................................................................... 97
6.31 XMC I/O Configuration Register (0x6AF)..................................................................................... 97
6.32 SSD Availability Register (0x6B1) ................................................................................................ 98
6.33 SSD Secure Hardware Erase Capability Register (0x6B2) .......................................................... 98
6.34 UART Enable Register (0x6B8) .................................................................................................... 98
6.35 COM Port Enable Register (0x6BB).............................................................................................. 99
6.36 COM Port Mode Register (0x6BC)................................................................................................ 99
6.37 COM Port RS485 Auto Direction Control Register (0x6BD) ...................................................... 100
6.38 COM Port Loopback Enable Register (0x6BE)........................................................................... 100
6.39 SSD Erase Control Register (0x6BF).......................................................................................... 101
6.40 SSD Cache Flush Control Register (0x6C0)............................................................................... 101
6.41 VPX Control Register (0x6C1) .................................................................................................... 101
6.42 Scratchpad Register (0x6C6) ..................................................................................................... 102
6.43 Test Register (0x6C7)................................................................................................................. 102
6.44 XMC Status Register (0x6C8) .................................................................................................... 102
6.45 Backplane Status Register (0x6CA)........................................................................................... 102
6.46 SSD Status Register (0x6CB)..................................................................................................... 103
6.47 Write Protection Status Register (0x6CC) ................................................................................. 103
6.48 Board Jumper Link Status Register (0x6CD)............................................................................. 104
6.49 Boot Location Status Register (0x6CE) ..................................................................................... 104

Publication No. SBC329-HRM/1 Contents 11
7 • Connectors ....................................................................................................... 105
7.1 Backplane Connectors ................................................................................................................. 107
7.1.1 P0 ................................................................................................................................................................ 107
7.1.2 Backplane J0.............................................................................................................................................. 107
7.1.3 P1 ................................................................................................................................................................ 108
7.1.4 Backplane J1.............................................................................................................................................. 108
7.1.5 P2 ................................................................................................................................................................ 109
7.1.6 Backplane J2.............................................................................................................................................. 110
7.1.7 Signal Descriptions.................................................................................................................................... 111
7.2 XMC Connectors........................................................................................................................... 113
7.2.1 J15 .............................................................................................................................................................. 113
7.2.2 J16 .............................................................................................................................................................. 114
7.2.3 Signal Descriptions.................................................................................................................................... 115
7.3 P5 Connector (TAC)...................................................................................................................... 115
A • Specifications .................................................................................................. 116
A.1 Technical Specification................................................................................................................ 116
A.2 Electrical Specification ................................................................................................................ 117
A.2.1 Voltage Supply Requirements.................................................................................................................. 117
A.2.2 Power Consumption.................................................................................................................................. 118
A.2.3 Current Consumption (SBC329-xxxxxx1xx Variant) ............................................................................... 118
A.2.4 Current Consumption (SBC329-xxxxxx2xx Variant) ............................................................................... 120
A.2.5 XMC Site Current Provision ...................................................................................................................... 120
A.2.6 Power Supply Sequencing........................................................................................................................ 120
A.3 Mechanical Specification ............................................................................................................ 121
A.4 Reliability (MTBF)......................................................................................................................... 121
A.5 Environmental Specifications...................................................................................................... 122
A.6 Product Codes.............................................................................................................................. 124
A.7 Software Support ......................................................................................................................... 125
A.8 I/O Modules.................................................................................................................................. 126
A.9 Test Access Card ......................................................................................................................... 127
A.10 Development Systems ............................................................................................................... 127
B • Thermal Derating ............................................................................................. 128
B.1 Processor Option 4: Standard...................................................................................................... 128
B.2 Processor Option 3: Low Power................................................................................................... 129
C • Statement of Volatility..................................................................................... 130
C.1 Volatile Memory ........................................................................................................................... 130
C.2 Non-Volatile Memory.................................................................................................................... 131
Glossary ................................................................................................................. 132
Index....................................................................................................................... 133

12 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
List of Tables
Table 3-1 P3 Link Setting ......................................................................................................................... 21
Table 3-2 P6 Link Setting ......................................................................................................................... 22
Table 4-1 Power Supply Requirements.................................................................................................... 25
Table 5-1 Supported Processor SKUs...................................................................................................... 48
Table 5-2 SDRAM Configuration .............................................................................................................. 49
Table 5-3 Data Plane Pin Mapping........................................................................................................... 54
Table 5-4 ETH0/ETH1/ETH2 Pin Mapping - BASE-T + BASE-BX Variant ................................................ 56
Table 5-5 ETH0/ETH1 Pin Mapping - Dual BASE-T Variant..................................................................... 57
Table 5-6 GPIO Line Signal Availability.................................................................................................... 57
Table 5-7 PCIe Switch Port Configuration ............................................................................................... 58
Table 5-8 USB Signal Availability ............................................................................................................. 59
Table 5-9 COM Port Connections............................................................................................................. 60
Table 5-10 COM1/COM2 Signal Availability ............................................................................................ 60
Table 5-11 SATA Signal Availability ......................................................................................................... 61
Table 5-12 Video Port Summary .............................................................................................................. 62
Table 5-13 DVI Signal Mapping................................................................................................................ 62
Table 5-14 XMC I/O Routing Availability.................................................................................................. 64
Table 5-15 Mezzanine Site Signal Mapping............................................................................................. 65
Table 5-16 I2C Bus Addresses .................................................................................................................. 66
Table 5-17 DIP Switch Options................................................................................................................. 67
Table 5-18 BMM I2C Bus Devices............................................................................................................. 70
Table 5-19 Temperature Sensor Monitor Locations................................................................................ 70
Table 5-20 PMBus Device Data Monitored .............................................................................................. 71
Table 5-21 LED Summary ......................................................................................................................... 73
Table 5-22 BIT LED Meanings .................................................................................................................. 74
Table 5-23 BIT Status LED Meanings ...................................................................................................... 75
Table 5-24 PCIe Link Status LED Meanings............................................................................................. 75
Table 5-25 Ethernet Link Status LED Meanings ...................................................................................... 76
Table 5-26 Reset Sources ........................................................................................................................ 77
Table 6-1 FPGA Registers......................................................................................................................... 80
Table 6-2 GPIO Register Bit Mapping....................................................................................................... 89
Table 7-1 Connector Functions.............................................................................................................. 105
Table 7-2 P0 Pin Assignments ............................................................................................................... 107
Table 7-3 J0 Pin Assignments ............................................................................................................... 107
Table 7-4 P1 Pin Assignments ............................................................................................................... 108
Table 7-5 J1 Pin Assignments ............................................................................................................... 108
Table 7-6 P2 Pin Assignments ............................................................................................................... 109

Publication No. SBC329-HRM/1 List of Tables 13
Table 7-7 J2 Pin Assignments ............................................................................................................... 110
Table 7-8 Backplane Connector Signal Descriptions ............................................................................ 111
Table 7-9 J15 Pin Assignments ............................................................................................................. 113
Table 7-10 J16 Pin Assignments ........................................................................................................... 114
Table 7-11 XMC Signal Descriptions...................................................................................................... 115
Table A-1 Technical Data........................................................................................................................ 116
Table A-2 Voltage Supply Requirements ............................................................................................... 117
Table A-3 Power Consumption (SBC329-xxxxxx1xx Variant)................................................................ 118
Table A-4 Power Consumption (SBC329-xxxxxx2xx Variant)................................................................ 118
Table A-5 Current Consumption –SBC329-xxxxxx1xx Variant –12V (VS1) Rail................................. 118
Table A-6 Current Consumption –3.3V Rail (Vs2) ................................................................................ 118
Table A-7 Current Consumption –5V Rail (Vs3) ................................................................................... 119
Table A-8 Current Consumption –P3V3_AUX....................................................................................... 119
Table A-9 Current Consumption - VBAT................................................................................................. 119
Table A-10 Power Measurement Conditions ......................................................................................... 119
Table A-11 Current Consumption –SBC329-xxxxxx2xx Variant –5V (VS3) Rail................................. 120
Table A-12 XMC Site Current Provision ................................................................................................. 120
Table A-13 Mechanical Construction..................................................................................................... 121
Table A-14 Reliability (MTBF)................................................................................................................. 121
Table A-15 Convection-cooled Environmental Specifications .............................................................. 122
Table A-16 Conduction-cooled Environmental Specifications.............................................................. 122
Table A-17 Product Options ................................................................................................................... 124
Table A-18 RTM Compatibility................................................................................................................ 126
Table B-1 Maximum Processor Speed versus Maximum Temperature for Processor Option 4 ......... 128
Table B-2 Maximum Processor Speed versus Maximum Temperature for Processor Option 3 ......... 129
Table C-1 Volatile Memory ..................................................................................................................... 130
Table C-2 Non-Volatile Memory.............................................................................................................. 131

14 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
List of Figures
Figure 1-1 SBC329.................................................................................................................................... 15
Figure 1-2 ESD Label (Present on Board Packaging) .............................................................................. 17
Figure 2-1 Product Label (Packaging) ..................................................................................................... 18
Figure 2-2 Product Label (Product).......................................................................................................... 18
Figure 2-3 Product Label (Conduction-cooled Product).......................................................................... 19
Figure 3-1 Link Positions.......................................................................................................................... 20
Figure 3-2 Keepout Area........................................................................................................................... 23
Figure 3-3 Mezzanine Position................................................................................................................. 24
Figure 4-1 First Boot Menu....................................................................................................................... 29
Figure 4-2 Main Menu............................................................................................................................... 31
Figure 4-3 Advanced Menu....................................................................................................................... 32
Figure 4-4 Chipset Menu .......................................................................................................................... 33
Figure 4-5 Abaco Menu ............................................................................................................................ 34
Figure 4-6 Board Build Information Sub-menu ........................................................................................ 35
Figure 4-7 DIP Switch Sub-menu ............................................................................................................. 36
Figure 4-8 FPGA Setup/Status Sub-menu ............................................................................................... 37
Figure 4-9 PLX Switch Sub-menu............................................................................................................. 38
Figure 4-10 Hardware Protection Sub-menu ........................................................................................... 40
Figure 4-11 CPU Speed Locking Configuration Sub-menu...................................................................... 41
Figure 4-12 Network Boot Configuration Sub-menu................................................................................ 42
Figure 4-13 Security Menu ....................................................................................................................... 43
Figure 4-14 Boot Menu ............................................................................................................................. 44
Figure 4-15 Save & Exit Menu .................................................................................................................. 45
Figure 5-1 Block Diagram ......................................................................................................................... 46
Figure 5-2 SLT3-PAY-2F2T-14.2.5 Port Layouts ...................................................................................... 52
Figure 5-3 SLT3-PAY-2F2U-14.2.3 Port Layouts...................................................................................... 52
Figure 5-4 Gigabit Ethernet Channel Configurations............................................................................... 56
Figure 5-5 RS422/485 Signal Definition .................................................................................................. 60
Figure 5-6 I2C Bus Structure..................................................................................................................... 66
Figure 5-7 On-board Sensor and System Management Bus Architecture.............................................. 69
Figure 5-8 Local and Remote PCB Sensor Locations.............................................................................. 70
Figure 5-9 Rear LED Positions.................................................................................................................. 73
Figure 5-10 Air-cooled Front Panel........................................................................................................... 79
Figure 5-11 Conduction-cooled Front Panel ............................................................................................ 79
Figure 7-1 Front Connector Positions and Numbering.......................................................................... 105
Figure 7-2 Rear Connector Position and Numbering............................................................................. 106
Figure 7-3 RS422/485 Signal Definition ................................................................................................ 112

Publication No. SBC329-HRM/1 Introduction 15
1 • Introduction
The Abaco Systems SBC329 is a member of the VPXcel3 family of 3U VPX Intel
processor-based Single Board Computers. This family is aimed at processing,
communications and display applications in the military and aerospace market.
The PC-like SBC329 implements the Intel Kaby Lake Mobile (+ECC) architecture at
up to 3.0 GHz, and has I/O interfaces including Gigabit Ethernet, USB 3.0, SATA and
GPIO. The Xeon E3-1505M v6 processor also provides a DDR4 SDRAM interface
with ECC. For more exacting SWaP requirements, the SBC329 is also available with
the E3-1505L v6 lower-power processor.
The Intel CM238 PCH provides three SATA interfaces, three USB ports, an LPC
interface and a Serial Peripheral Interface (supporting SPI boot Flash). The XMC site
connects 24S+X8d+X12d I/O signals to the VPX backplane, and has a x8 PCIe
interface supporting Gen2 operation.
The SBC329 supports eight PCIe lanes with various configurations to the backplane
for connection to other cards in the system.
The SBC329 is supplied with a BIOS, supporting operating systems such as Microsoft
Windows 10, Windows 10 IoT, Linux and VxWorks.
Figure 1-1 SBC329

16 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
1.1 Safety Notices
The following general safety precautions represent warnings of certain dangers of
which Abaco Systems is aware. Failure to comply with these or with specific
Warnings and/or Cautions elsewhere in this manual violates safety standards of
design, manufacture and intended use of the equipment. Abaco assumes no liability
for the user’s failure to comply with these requirements.
Also follow all warning instructions contained in associated system equipment
manuals.
The SBC329 complies with BS-EN60950-1:2006 (product safety).
WARNINGS
Use extreme caution when handling, testing and adjusting this equipment. This device may
operate in an environment containing potentially dangerous voltages.
Ensure that all power to the system is removed before installing any device.
To minimize electric shock hazard, connect the equipment chassis and rack/enclosure to an
electrical ground. If AC power is supplied to the rack/enclosure, the power jack and mating plug
of the power cable must meet IEC safety standards.
1.1.1 Flammability
The SBC329 circuit board is made by a UL-recognized manufacturer and has a
flammability rating of UL94V-1.
1.1.2 EMI/EMC Regulatory Compliance
CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to EMI if not installed and used in a cabinet with adequate EMI protection.
The SBC329 is designed using good EMC practices and, when used in a suitably
EMC-compliant chassis, should maintain the compliance of the total system.
Air-cooled build levels of the SBC329 are designed for use in systems meeting VDE
class B, EN and FCC regulations for EMC emissions and susceptibility.
Conduction-cooled build levels of the SBC329 are intended for integration into EMC
hardened cabinets/boxes.

Publication No. SBC329-HRM/1 Introduction 17
1.1.3 Cooling
CAUTION
The SBC329 requires air-flow of at least 300 lfm for build levels 1 and 2, and at least 600 lfm for
build level 3. If a conduction-cooled (level 4 or 5) SBC329 is operating on an extender card, it
requires air-flow of at least 300 lfm across it.
1.1.4 Handling
CAUTION
Only handle the SBC329 by the edges or front panel.
Figure 1-2 ESD Label (Present on Board Packaging)
1.1.5 Heatsink
CAUTIONS
Do not remove the heatsink. There are no user-alterable components underneath the heatsink,
so users should have no reason to remove it.
Users should not attempt reattachment of the heatsink, as this requires precise torque on the
screws attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink
to damage components beneath it. Removal and re-attachment of the heatsink should only be
carried out by Abaco.

18 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
2 • Unpacking
On receipt of the shipping container, if there is any evidence of physical damage, the
Terms and Conditions of Sale (provided with your delivery) give information on
what to do. If you need to return the product, contact Abaco.
The SBC329 is sealed into an antistatic bag and housed in a padded cardboard box.
Failure to use the correct packaging when storing or shipping the board may
invalidate the warranty.
2.1 Box Contents Checklist
1. SBC329 in antistatic packaging.
2. Embedded Software License Agreement (ABACO-SLA-001-01).
2.2 Identifying Your Board
The SBC329 is identified by labels at strategic positions. These can be cross-checked
against the Advice Note provided with your delivery.
Identification labels, like the example shown in Figure 2-1, attached to the shipping
box and the antistatic bag give identical information: product code, product
description, equipment number and board revision.
Figure 2-1 Product Label (Packaging)
On the board within the antistatic bag, there is an identifying label, like the example
shown in Figure 2-2, attached to the PCB.
Figure 2-2 Product Label (Product)

Publication No. SBC329-HRM/1 Unpacking 19
On conduction-cooled versions of the board (build levels 4 and 5), there is also a
label, like the example shown in Figure 2-3, attached to the front panel.
Figure 2-3 Product Label (Conduction-cooled Product)
See the Product Codes section in Appendix A for more details on the product code
(SBC329-xxxxxxxxx).

20 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
3 • Configuration
3.1 Link Configuration
The SBC329 has push-on jumpers included in the standard kit of parts; additional
jumpers may be obtained on request. These are suitable for level 1 to 3 low vibration
applications.
TIP
For Level 4 and 5 products, make links by wire-wrapping between the pin posts and then cover
these wire-wrapped links with the same conformal coating as that used on the board (usually
ACRYLIC 1B73AP –contact Technical Support for details if needed). This will provide a reliable
connection under heavy shock and vibration conditions and further prevent oxidation of the
connection due to moisture ingress.
Figure 3-1 Link Positions
The diagram above shows standard 2.54 mm pitch headers for general use.
This manual refers to jumper settings as In or Out. Meanings are as follows:
In = jumper fitted -
Out = jumper not fitted -
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