Abov A31G22x User manual

Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
A31G22x
Clock Setting Guide
Application Note
Version 1.01

Contents A31G22x Clock Setting Guide
2
Contents
1. Glossary .........................................................................................................................................4
2. Introduction ....................................................................................................................................5
3. Clock System .................................................................................................................................6
3.1. SCU Block Diagram ............................................................................................................6
3.2. Clock Sources for Peripherals.............................................................................................8
4. Clock Sources ..............................................................................................................................11
4.1. LSI Clock ...........................................................................................................................12
4.1.1. F/W Configuration.................................................................................................12
4.2. HSI Clock ..........................................................................................................................12
4.2.1. F/W Configuration.................................................................................................12
4.3. LSE Clock..........................................................................................................................13
4.3.1. H/W Configuration ................................................................................................13
4.3.2. F/W Configuration.................................................................................................14
4.4. HSE Clock .........................................................................................................................15
4.4.1. H/W Configuration ................................................................................................15
4.4.2. F/W Configuration.................................................................................................16
4.5. PLL Clock ..........................................................................................................................17
4.5.1. PLL Block Diagram ...............................................................................................17
4.5.2. Calculating PLL Output Frequency.......................................................................18
4.5.3. F/W Configuration.................................................................................................19
5. Flash Access Timing ....................................................................................................................23
5.1. Wait Time Configuration ....................................................................................................23
5.2. F/W Configuration .............................................................................................................23
6. Output of System Main Clock ......................................................................................................24
7. Examples .....................................................................................................................................26
8. References...................................................................................................................................27
Revision History ....................................................................................................................................28

A31G22x Clock Setting Guide List of Figures/ List of Tables
3
List of Figures
Figure 1. Clock Tree Configuration .........................................................................................................7
Figure 2. Peripheral Clock Selection (n = 1, 2, 3, 4, 5, 6 and 7) .............................................................8
Figure 3. LSI Clock F/W Configuration .................................................................................................12
Figure 4. HSI Clock F/W Configuration .................................................................................................12
Figure 5. SXTAL Oscillator Circuit.........................................................................................................13
Figure 6. LSE Clock F/W Configuration ................................................................................................14
Figure 7. XTAL Oscillator Circuit ...........................................................................................................15
Figure 8. HSE Clock F/W Configuration ...............................................................................................16
Figure 9. PLL Block Diagram of A31G22x Series .................................................................................17
Figure 10. PLL Clock F/W Configuration Example 1 ............................................................................19
Figure 11. PLL Clock F/W Configuration Example 2.............................................................................21
Figure 12. Flash Access Timing F/W Configuration ..............................................................................23
Figure 13. System Main Clock Output ..................................................................................................24
Figure 14. Oscilloscope Measurement of CLKO Pin Output ................................................................25
Figure 15. Example Project Changing System Clock ...........................................................................26
Figure 16. Example Code Initializing Clock Source ..............................................................................26
List of Tables
Table 1. Definition of Terms.....................................................................................................................4
Table 2. Main Clock Branches.................................................................................................................6
Table 3. Clock Sources of Peripherals ....................................................................................................9
Table 4. Definition of Clock Sources .....................................................................................................11
Table 5. LSE External Capacitive Load.................................................................................................13
Table 6. HSE Frequency by VDDEXT and HSE External Capacitive Load ..........................................15
Table 7. Flash Wait Time Values ...........................................................................................................23

1. Glossary A31G22x Clock Setting Guide
4
1. Glossary
Table 1. Definition of Terms
Term
Description
HCLK
AHB Clock
PCLK
APB Clock
MCLK
Main Clock
LSI
Low Speed Internal Clock
HSI
High Speed Internal Clock
LSE
Low Speed External Clock
HSE
High Speed External Clock
PLL
Phase Locked Loop Clock
XTAL
External Crystal
SXTAL
Sub External Crystal
AHB
Advanced High-Performance Bus
APB
Advanced Peripheral Bus
SCU
System Control Unit

A31G22x Clock Setting Guide 2. Introduction
5
2. Introduction
A31G22x has an SCU (System Control Unit) that can control the system settings flexibly to meet the
requirements of an application.
Specifically the SCU allows users to configure a main system clock by selecting and setting a clock
source for the user system.
In this application note, users can learn a method to select a corresponding clock source and configure
a system clock for A31G22x. Examples using API presented in this document will help users understand
and develop application prototypes quickly.

3. Clock System A31G22x Clock Setting Guide
6
3. Clock System
3.1. SCU Block Diagram
A31G22x series has two main operating clocks. One is HCLK which produces a clock signal both for
CPU and AHB bus. The other is PCLK using APB bus which produces a clock signal for peripheral
systems.
Table 2. Main Clock Branches
Clock Source
Clock Bus
Description
Modules
MCLK
HCLK
High Speed Clock Bus
Core
Flash Memory
SRAM
PCLK
Peripheral Clock Bus
Peripherals
Users can change the clock system under the software control. In 4. Clock Sources, users can learn
more about the clock system and clock sources of A31G22x.

A31G22x Clock Setting Guide 3. Clock System
7
SXIN
XIN
LSI
500kHz
LSE
32.768kHz
HSE
2 ~ 16MHz
HSI
32MHz
000
011
100
101
110
111
Clock
N
Divider
WDTRC
32.250k
[7:0][2:0]
1/N
(N=16)
1/N
(N=1,2,4) 00
01
10
11
MCLKSEL
[1:0]
0
1
PLLINCLKSEL
PLL
Up to 48MHz
1/N
(N=1,2,4)
1/N
(N=1,2,4,8,6,32)
1/N
(N=1,2,4)
Divider
1/N
(N= 1 to 255) CLKO
Cortex M0+
Memory
FCLK
APB Bus
Interface
PCLK
HCLK
SCU_PCER1,2
MCLK
LSI
LSE
MCLK
HSI
HSE
PLL SCU_MCCR5 LCD Driver
LSE
TEMP
SENSOR
M
U
X
SYSTICK
SCU_MCCR1
M
U
X
SCU_MCCR2
PCLK TIMER20
M
U
X
SCU_MCCR1
PCLK TIMER1n
M
U
X
SCU_MCCR3
WDTRC WDT
M
U
X
SCU_MCCR2
PCLK TIMER30
SCU_MCCR4 DEBOUNCE
CLOCK
SCU_MCCR3
WDTRC WT
LSE M
U
X
HSE
HSI
M
U
X
LSI
MCLK
HSI
LSI_TS
SCU_MCCR7
ADC
TSSENSECLK
TSREFCLK
M
U
X
MCLK
M
U
X
PCLK
PLLBYPASS
PLLOUTPUT
NOTES:
1. In the block diagram above, peripheral blocks not specified in the SCU_MCCRx register use PCLK as a
reference clock by default.
2. If you want to use a peripheral clock based on LSI/ LSE/ HSI/ HSE in your application, it is recommended
to enable the clock source before enabling the peripheral.
Figure 1. Clock Tree Configuration
Each multiplexer that switches clock sources has an internal glitch-free circuit. So a clock can be
switched without glitch risks.
When changing the system's main clock from low to high, the flash wait-time must be set so that the
flash access time does not exceed the maximum flash access timing.
When a user tries to change a clock mux control, all clock sources must be alive. If one of them is not
alive, the clock change operation is stopped and system will be halted and not be recovered.

3. Clock System A31G22x Clock Setting Guide
8
3.2. Clock Sources for Peripherals
Figure 2 shows how to set the peripheral clock. Selecting a peripheral clock is a typical method of
MCCRn and PCLK. Exceptionally WT, WDT, LCD use other clocks besides MCCRn and PCLK. (n = 1,
2, 3, 4, 5, 6 and 7).
Enable Clock for MCCRn
&
Enable Clock for PCLK
END
Peripheral clock : MCCRn ?
Select clock for Peripheral
In SCU_PPCLKSR
Select MCCRn for the
Peripheral to use
Y
Peripheral clock : PCLK
(Exception : WT, WDT, LCD)
N
* WT : LSE, WDTRC
* WDT : WDTRC
* LCD : LSE, WDTRC
* SCU_PPCLKSR : PCLK, MCCRn
(Exception : WT, WDT, LCD)
NOTES:
1. The WDTRC clock outputs 31.250KHz frequency generated by dividing the Typ. 500kHz (± 20%) LSI
clock by 16 in the internal logic.
2. This WDTRC clock can be the source clock of the WDT, WT, LCD and TIMER20 capture signals.
Figure 2. Peripheral Clock Selection (n = 1, 2, 3, 4, 5, 6 and 7)

A31G22x Clock Setting Guide 3. Clock System
9
Table 3 shows the Clock Buses and Clock Sources that A31G22x supports for each peripheral.
Table 3. Clock Sources of Peripherals
Peripheral Clock
Clock Bus
Clock Source
Core
HCLK
-
CFMC
HCLK / PCLK
-
DFMC
HCLK / PCLK
-
DMAC
HCLK / PCLK
-
CRC
PCLK
SysTick
HCLK
-
SCU_MCCR1
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER1n
PCLK
-
SCU_MCCR1
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER2n
PCLK
-
SCU_MCCR2
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER21
PCLK
-
TIMER30
PCLK
-
SCU_MCCR2
LSI
HSI
LSE
HSE
MCLK
PLL
WDT
PCLK
-
WDTRC
LSI/16
SCU_MCCR3
LSI
HSI
LSE
HSE
MCLK
PLL

3. Clock System A31G22x Clock Setting Guide
10
Table 3. Clock Sources of Peripherals (continued)
Peripheral Clock
Clock Bus
Clock Source
WT
PCLK
-
WDTRC
LSI/16
SCU_MCCR3
LSI
HSI
LSE
HSE
MCLK
PLL
PCU
PCLK
-
PCU Debounce Clock
SCU_MCCR4
LSI
HSI
LSE
HSE
MCLK
PLL
USART
PCLK
-
UART
PCLK
-
SPI
PCLK
-
I2C
PCLK
-
LCD
PCLK
-
WDTRC
LSI/16
SCU_MCCR5
LSI
HSI
LSE
HSE
MCLK
PLL
TS
SCU_MCCR5
Sensing clock: LSITS
LSI
HSI
Reference clock: HSI
LSE
HSE
MCLK
ADC
PCLK
-
SCU_MCCR7
LSI
HSI
LSE
HSE
MCLK
PLL
DAC
PCLK
-
CMP
PCLK
-

A31G22x Clock Setting Guide 4. Clock Sources
11
4. Clock Sources
A31G22x allows users to configure the main clock and peripheral clock by using the clock sources listed
in Table 4 . Various functions of user application can be implemented using these clock sources.
Table 4. Definition of Clock Sources
Clock source
Frequency Range
Clock Bus
Supply Voltage [V]
LSI
500kHz (±20%)
Main clock
Peripheral clock
WDTRC (Divided by 16)
1.8 to 5.5
HSI
32MHz (±1%)
Main clock
Peripheral clock
PLL Input clock
1.8 to 5.5
LSE
32.768kHz
Main clock
Peripheral clock
2.7 to 5.5
HSE
1MHz to 16MHz
Main clock
Peripheral clock
PLL Input clock
1.8 to 5.5
PLL
1MHz to 48MHz
Main clock
Peripheral clock
1.8 to 5.5

4. Clock Sources A31G22x Clock Setting Guide
12
4.1. LSI Clock
LSI is an internal oscillator operating at a low speed of 500kHz, and begins to oscillate when power is
first applied to the initialized MCU. It is used as a clock source in Low Power mode too.
If the LSI clock is always on after the system is powered on, but the default system clock is changed to
another clock source (LSE, HSI, HSE), you can disable the LSI clock. When the LSI clock is disabled,
the peripheral based on LSI clock source also stops working.
The LSI clock can be used as a main clock or peripheral clock. Since the LSI enables internal oscillation
in an MCU without external crystal, users can implement user application system with a low cost and
effective solution.
4.1.1. F/W Configuration
Right after applying power, although the LSI clock is in Always On but explicitly, the “LSI clock source”
is enabled. In the state the LSI clock is enabled, the LSI clock is set as a system clock, and the global
variables representing HCLK and PCLK are updated to have system operation frequency value.
Figure 3. LSI Clock F/W Configuration
4.2. HSI Clock
HSI is an internal oscillator operating at a high speed of 32MHz. The HSI clock can be used as an input
source that configure the main clock and PLL clock or a peripheral clock. Since the HSI enables internal
oscillation in an MCU without external crystal, users can implement user application system with a low
cost and effective solution.
4.2.1. F/W Configuration
Figure 4. HSI Clock F/W Configuration

A31G22x Clock Setting Guide 4. Clock Sources
13
4.3. LSE Clock
The LSE is an auxiliary external crystal (SXTAL) that operates at a low speed of 32.768kHz. The LSE
clock can be used as a system clock or peripheral clock. It is used as a clock source in Low Power
mode too.
LSE clock that can be enabled by software performs RTC (Real Time Clock) operations that makes
accurate time measurement, and performs RTC (Real Time Clock) operations that makes accurate time
measurement. The RTC is realized by dividing the clock using the pre-scaler and usually required for
Time Critical System.
Tolerance of the LSE clock reflects the characteristics of the SXTAL element, so users must refer to
Datasheet of the corresponding Crystal.
4.3.1. H/W Configuration
To use the LSE clock, users must configure the oscillator circuit using the auxiliary external crystal
(SXTAL) as shown in Figure 5.
SXIN SXOUT
C1 C2
Figure 5. SXTAL Oscillator Circuit
Table 5. LSE External Capacitive Load
Oscillator
Parameter
Conditions
Min
Typ.
Max
Units
External load cap
C1,C2
―
7
12
24
pF

4. Clock Sources A31G22x Clock Setting Guide
14
4.3.2. F/W Configuration
SXIN and SXOUT pins of the LSE clock must be set before enabling the LSE clock. After enabling the
LSE clock, stabilization time for the SXTAL is required.
Next, users must set the LSE clock source as the system clock and update the global variables
representing HCLK and PCLK to have the system operation frequency value.
Figure 6. LSE Clock F/W Configuration

A31G22x Clock Setting Guide 4. Clock Sources
15
4.4. HSE Clock
HSE clock is a main external crystal (XTAL) that operates at the high speed ranging from 1MHz to
16MHz. It can be used as an input source setting the main clock and PLL clock or a peripheral clock.
HSE clock can be enabled by software, and can set the accurate frequency dividing the clock using the
pre-scaler. Tolerance of the HSE clock reflects the characteristics of the XTAL element, so users must
refer to Datasheet of the corresponding Crystal.
4.4.1. H/W Configuration
To use the HSE clock, users must configure the oscillator circuit using the main external crystal (XTAL)
as shown in Figure 7. Please remember that the External Load Caps (C1 and C2) in the figure are
varied by the value of minimum operation voltage and XTAL frequency of the application system.
XIN XOUT
C1 C2
Figure 7. XTAL Oscillator Circuit
Table 6. HSE Frequency by VDDEXT and HSE External Capacitive Load
Oscillator
Parameter
Conditions
Min
Typ.
Max
Units
Output
frequency
fOUT
VDDEXT ≥1.8V
SCU_EOSCR<ISEL[1:0]>=2’b11
SCU_EOSCR<NCOPT[1:0]>=2’b00
1.0
―
4.0
MHz
VDDEXT ≥2.0V
SCU_EOSCR<ISEL[1:0]>=2’b10
SCU_EOSCR<NCOPT[1:0]>=2’b01
1.0
―
8.0
MHz
VDDEXT ≥2.2V
SCU_EOSCR<ISEL[1:0]>=2’b01
SCU_EOSCR<NCOPT[1:0]>=2’b10
1.0
―
12.0
MHz
VDDEXT ≥2.4V
SCU_EOSCR<ISEL[1:0]>=2’b00
SCU_EOSCR<NCOPT[1:0]>=2’b11
1.0
―
16.0
MHz
External load
cap
C1,C2
1M< fOUT <4M
18
30
35
pF
4M< fOUT <12M
10
22
30
pF
12M< fOUT <16M
7
18
22
pF

4. Clock Sources A31G22x Clock Setting Guide
16
4.4.2. F/W Configuration
XIN and XOUT pins of the HSE clock must be set before enabling the HSE clock. After enabling the
HSE clock, stabilization time for the XTAL is required.
Next, users must set the HSE clock source as the system clock and update the global variables
representing HCLK and PCLK to have the system operation frequency value.
Figure 8. HSE Clock F/W Configuration

A31G22x Clock Setting Guide 4. Clock Sources
17
4.5. PLL Clock
PLL clock is used to set the high speed clock frequency as a main clock of the system. The two clock
sources HSI and HSE are used as Input clocks of the PLL.
Tolerance of PLL reflects the characteristics of the input clock sources. Based on the PLL input clocks,
PLL Frequency Divider can be used to output more accurate frequency, and the main clock of the
system can be set up to 48MHz using PLL Output Frequency.
4.5.1. PLL Block Diagram
RPFD CP VCO
LPF
N1
D N2 P
POR
LOCK
DETECT
PLLEN
PLLRSTB
fPLLINCLK
PLLLOCK
RST_I
fDOUBLE (fVCO x 2)
fVCO
EN
PORST
VCTRL
PLLRSTB
BYPASSB
PLLINCLK fPLLOUT
0
1
fIN
NOTES:
1. Set PLLRSTB to ‘1’ after at least 1us when PLLEN is set to ‘1’.
2. (Option) Wait at least 100 us after PLLLOCK is occurred.
3. Output calculation formula is as followings:

    
  󰇛 󰇜
󰇛  󰇜 󰇛 󰇜  󰇛  󰇜  󰇛  󰇜
Name
Symbol
Description
Setting Range
PREDIV
R
PLLINCLK Pre-Divider Value
0 to 7
POSTDIV1
N1
Post Multiplier Value
0 to 255
POSTDIV2
N2
Post Divider Value
0 to 15
OUTDIV
P
Output Divider Value
0 to 15
PLLMODE
D
Frequency Doubler Value
0 to 11
Figure 9. PLL Block Diagram of A31G22x Series

4. Clock Sources A31G22x Clock Setting Guide
18
4.5.2. Calculating PLL Output Frequency
PLL of A31G22x series can set the output frequency, fOUT, in 1MHz increments accurately. The formula
for the fIN is introduced below. Input range of the fIN frequency can be ranging from 1MHz to 3MHz,
however, it is recommended to be up to 2MHz:

 

󰇛  󰇜   
  󰇛   󰇜
At this time, the range of fVCO output frequency should be set to 200MHz or less, and the calculation
formula is shown below:

    󰇛 󰇜   
The SCU_PLLCON register also supports the Doubler function which can double the fVCO output through
the bit setting of VCOMODE. When using this doubler function, the output of fVCOx2 should be set to
250MHz or less:

    󰇛  󰇜         
As a result, the final frequency of PLL, fPLLOUT, can be obtained from the formula below using the formula
above:

    
 󰇛 󰇜
󰇛  󰇜󰇛 󰇜󰇛  󰇜󰇛  󰇜   
  󰇛 󰇜
󰇛 󰇜  󰇛  󰇜 󰇛  󰇜
 

󰇛 󰇜  󰇛  󰇜   

A31G22x Clock Setting Guide 4. Clock Sources
19
4.5.3. F/W Configuration
Example 1
Figure 10 and the procedure listed below show an example code that outputs PLL 48MHz frequency
using the HSI clock source.
Figure 10. PLL Clock F/W Configuration Example 1
1. Enable the HSI clock source. If fPLLINCLK (32MHz) is used without change, since the fIN ranges
from 1MHz to 3MHz and the value of PREDIV (R) can be between 0 and 7 at this time, the
fPLLINCLK clock that is HSI clock is divided by 2 in the SCU_CSCR<HSICON[7:4]> register to
result in 16MHz frequency.
fPLLINCLK = 32MHz / 2 = 16MHz (SCU_CSCR<HSICON[7:4]> = 0x09)
2. Configure the SCU_SCCR register:
①Set PLLINCLKSEL bit to 0 (0x00).
②Set MCLKSEL bits to 10 (0x10).
3. Set R to 7. This allows the fIN value to be between 1MHz and 3MHz.
fIN / (R + 1) = 16MHz / (7 + 1) = 2MHz

4. Clock Sources A31G22x Clock Setting Guide
20
4. Set N1 to the value that allows fVCO to be less than 200MHz.
fVCO = fIN * (N1 + 1) = 2MHz * (47 + 1) = 96MHz
5. Set D to the value that allows fVCO*2 to be less than 250MHz.
fVCO*2 = fVCO * (D + 1) = fVCO * (0 + 1) = 96MHz
6. By adjusting values of N2 and P, set fPLLOUT to be 48MHz.
fPLLOUT = fVCO / {(N2 + 1) * (P + 1)} = 96MHz / {(1 + 1)*(0 + 1)} = 48MHz
7. Configure the SCU_PLLCON register:
①Set BYPASSB bit to enable PLL Output Bypass mode.
②Set PLLEN and PLLRSTB bits to enable PLL and PLL Reset.
③Set PREDIV to the value that you defined for the PLL Divider in the step3.
④(Option) Update the SCU_PLLCON register. After applying stabilization time, check
PLLLOCK bit to confirm whether PLL is locked.
8. If PLLLOCK bit is set, configure the SCU_SCCR register so that the system main clock
becomes the HSI PLL mode:
①Set PLLINCLKSEL bit to 0 (0x00).
②Set MCLKSEL bits to 10 (0x10).
9. Update each global variable representing HCLK and PCLK to have the system operation
frequency value.