Abov A31G22x User manual

Global Top Smart MCU Innovator, ABOV Semiconductor
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A31G22x
Clock Setting Guide
Application Note
Version 1.01

Contents A31G22x Clock Setting Guide
2
Contents
1. Glossary .........................................................................................................................................4
2. Introduction ....................................................................................................................................5
3. Clock System .................................................................................................................................6
3.1. SCU Block Diagram ............................................................................................................6
3.2. Clock Sources for Peripherals.............................................................................................8
4. Clock Sources ..............................................................................................................................11
4.1. LSI Clock ...........................................................................................................................12
4.1.1. F/W Configuration.................................................................................................12
4.2. HSI Clock ..........................................................................................................................12
4.2.1. F/W Configuration.................................................................................................12
4.3. LSE Clock..........................................................................................................................13
4.3.1. H/W Configuration ................................................................................................13
4.3.2. F/W Configuration.................................................................................................14
4.4. HSE Clock .........................................................................................................................15
4.4.1. H/W Configuration ................................................................................................15
4.4.2. F/W Configuration.................................................................................................16
4.5. PLL Clock ..........................................................................................................................17
4.5.1. PLL Block Diagram ...............................................................................................17
4.5.2. Calculating PLL Output Frequency.......................................................................18
4.5.3. F/W Configuration.................................................................................................19
5. Flash Access Timing ....................................................................................................................23
5.1. Wait Time Configuration ....................................................................................................23
5.2. F/W Configuration .............................................................................................................23
6. Output of System Main Clock ......................................................................................................24
7. Examples .....................................................................................................................................26
8. References...................................................................................................................................27
Revision History ....................................................................................................................................28

A31G22x Clock Setting Guide List of Figures/ List of Tables
3
List of Figures
Figure 1. Clock Tree Configuration .........................................................................................................7
Figure 2. Peripheral Clock Selection (n = 1, 2, 3, 4, 5, 6 and 7) .............................................................8
Figure 3. LSI Clock F/W Configuration .................................................................................................12
Figure 4. HSI Clock F/W Configuration .................................................................................................12
Figure 5. SXTAL Oscillator Circuit.........................................................................................................13
Figure 6. LSE Clock F/W Configuration ................................................................................................14
Figure 7. XTAL Oscillator Circuit ...........................................................................................................15
Figure 8. HSE Clock F/W Configuration ...............................................................................................16
Figure 9. PLL Block Diagram of A31G22x Series .................................................................................17
Figure 10. PLL Clock F/W Configuration Example 1 ............................................................................19
Figure 11. PLL Clock F/W Configuration Example 2.............................................................................21
Figure 12. Flash Access Timing F/W Configuration ..............................................................................23
Figure 13. System Main Clock Output ..................................................................................................24
Figure 14. Oscilloscope Measurement of CLKO Pin Output ................................................................25
Figure 15. Example Project Changing System Clock ...........................................................................26
Figure 16. Example Code Initializing Clock Source ..............................................................................26
List of Tables
Table 1. Definition of Terms.....................................................................................................................4
Table 2. Main Clock Branches.................................................................................................................6
Table 3. Clock Sources of Peripherals ....................................................................................................9
Table 4. Definition of Clock Sources .....................................................................................................11
Table 5. LSE External Capacitive Load.................................................................................................13
Table 6. HSE Frequency by VDDEXT and HSE External Capacitive Load ..........................................15
Table 7. Flash Wait Time Values ...........................................................................................................23

1. Glossary A31G22x Clock Setting Guide
4
1. Glossary
Table 1. Definition of Terms
Term
Description
HCLK
AHB Clock
PCLK
APB Clock
MCLK
Main Clock
LSI
Low Speed Internal Clock
HSI
High Speed Internal Clock
LSE
Low Speed External Clock
HSE
High Speed External Clock
PLL
Phase Locked Loop Clock
XTAL
External Crystal
SXTAL
Sub External Crystal
AHB
Advanced High-Performance Bus
APB
Advanced Peripheral Bus
SCU
System Control Unit

A31G22x Clock Setting Guide 2. Introduction
5
2. Introduction
A31G22x has an SCU (System Control Unit) that can control the system settings flexibly to meet the
requirements of an application.
Specifically the SCU allows users to configure a main system clock by selecting and setting a clock
source for the user system.
In this application note, users can learn a method to select a corresponding clock source and configure
a system clock for A31G22x. Examples using API presented in this document will help users understand
and develop application prototypes quickly.

3. Clock System A31G22x Clock Setting Guide
6
3. Clock System
3.1. SCU Block Diagram
A31G22x series has two main operating clocks. One is HCLK which produces a clock signal both for
CPU and AHB bus. The other is PCLK using APB bus which produces a clock signal for peripheral
systems.
Table 2. Main Clock Branches
Clock Source
Clock Bus
Description
Modules
MCLK
HCLK
High Speed Clock Bus
Core
Flash Memory
SRAM
PCLK
Peripheral Clock Bus
Peripherals
Users can change the clock system under the software control. In 4. Clock Sources, users can learn
more about the clock system and clock sources of A31G22x.

A31G22x Clock Setting Guide 3. Clock System
7
SXIN
XIN
LSI
500kHz
LSE
32.768kHz
HSE
2 ~ 16MHz
HSI
32MHz
000
011
100
101
110
111
Clock
N
Divider
WDTRC
32.250k
[7:0][2:0]
1/N
(N=16)
1/N
(N=1,2,4) 00
01
10
11
MCLKSEL
[1:0]
0
1
PLLINCLKSEL
PLL
Up to 48MHz
1/N
(N=1,2,4)
1/N
(N=1,2,4,8,6,32)
1/N
(N=1,2,4)
Divider
1/N
(N= 1 to 255) CLKO
Cortex M0+
Memory
FCLK
APB Bus
Interface
PCLK
HCLK
SCU_PCER1,2
MCLK
LSI
LSE
MCLK
HSI
HSE
PLL SCU_MCCR5 LCD Driver
LSE
TEMP
SENSOR
M
U
X
SYSTICK
SCU_MCCR1
M
U
X
SCU_MCCR2
PCLK TIMER20
M
U
X
SCU_MCCR1
PCLK TIMER1n
M
U
X
SCU_MCCR3
WDTRC WDT
M
U
X
SCU_MCCR2
PCLK TIMER30
SCU_MCCR4 DEBOUNCE
CLOCK
SCU_MCCR3
WDTRC WT
LSE M
U
X
HSE
HSI
M
U
X
LSI
MCLK
HSI
LSI_TS
SCU_MCCR7
ADC
TSSENSECLK
TSREFCLK
M
U
X
MCLK
M
U
X
PCLK
PLLBYPASS
PLLOUTPUT
NOTES:
1. In the block diagram above, peripheral blocks not specified in the SCU_MCCRx register use PCLK as a
reference clock by default.
2. If you want to use a peripheral clock based on LSI/ LSE/ HSI/ HSE in your application, it is recommended
to enable the clock source before enabling the peripheral.
Figure 1. Clock Tree Configuration
Each multiplexer that switches clock sources has an internal glitch-free circuit. So a clock can be
switched without glitch risks.
When changing the system's main clock from low to high, the flash wait-time must be set so that the
flash access time does not exceed the maximum flash access timing.
When a user tries to change a clock mux control, all clock sources must be alive. If one of them is not
alive, the clock change operation is stopped and system will be halted and not be recovered.

3. Clock System A31G22x Clock Setting Guide
8
3.2. Clock Sources for Peripherals
Figure 2 shows how to set the peripheral clock. Selecting a peripheral clock is a typical method of
MCCRn and PCLK. Exceptionally WT, WDT, LCD use other clocks besides MCCRn and PCLK. (n = 1,
2, 3, 4, 5, 6 and 7).
Enable Clock for MCCRn
&
Enable Clock for PCLK
END
Peripheral clock : MCCRn ?
Select clock for Peripheral
In SCU_PPCLKSR
Select MCCRn for the
Peripheral to use
Y
Peripheral clock : PCLK
(Exception : WT, WDT, LCD)
N
* WT : LSE, WDTRC
* WDT : WDTRC
* LCD : LSE, WDTRC
* SCU_PPCLKSR : PCLK, MCCRn
(Exception : WT, WDT, LCD)
NOTES:
1. The WDTRC clock outputs 31.250KHz frequency generated by dividing the Typ. 500kHz (± 20%) LSI
clock by 16 in the internal logic.
2. This WDTRC clock can be the source clock of the WDT, WT, LCD and TIMER20 capture signals.
Figure 2. Peripheral Clock Selection (n = 1, 2, 3, 4, 5, 6 and 7)

A31G22x Clock Setting Guide 3. Clock System
9
Table 3 shows the Clock Buses and Clock Sources that A31G22x supports for each peripheral.
Table 3. Clock Sources of Peripherals
Peripheral Clock
Clock Bus
Clock Source
Core
HCLK
-
CFMC
HCLK / PCLK
-
DFMC
HCLK / PCLK
-
DMAC
HCLK / PCLK
-
CRC
PCLK
SysTick
HCLK
-
SCU_MCCR1
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER1n
PCLK
-
SCU_MCCR1
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER2n
PCLK
-
SCU_MCCR2
LSI
HSI
LSE
HSE
MCLK
PLL
TIMER21
PCLK
-
TIMER30
PCLK
-
SCU_MCCR2
LSI
HSI
LSE
HSE
MCLK
PLL
WDT
PCLK
-
WDTRC
LSI/16
SCU_MCCR3
LSI
HSI
LSE
HSE
MCLK
PLL

3. Clock System A31G22x Clock Setting Guide
10
Table 3. Clock Sources of Peripherals (continued)
Peripheral Clock
Clock Bus
Clock Source
WT
PCLK
-
WDTRC
LSI/16
SCU_MCCR3
LSI
HSI
LSE
HSE
MCLK
PLL
PCU
PCLK
-
PCU Debounce Clock
SCU_MCCR4
LSI
HSI
LSE
HSE
MCLK
PLL
USART
PCLK
-
UART
PCLK
-
SPI
PCLK
-
I2C
PCLK
-
LCD
PCLK
-
WDTRC
LSI/16
SCU_MCCR5
LSI
HSI
LSE
HSE
MCLK
PLL
TS
SCU_MCCR5
Sensing clock: LSITS
LSI
HSI
Reference clock: HSI
LSE
HSE
MCLK
ADC
PCLK
-
SCU_MCCR7
LSI
HSI
LSE
HSE
MCLK
PLL
DAC
PCLK
-
CMP
PCLK
-