Acromag Acropack AP440 Series User manual

Series AP440 AcroPack
32-Channel Isolated Digital Input Module
With Interrupts
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 2016, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501051D

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Table of Contents
1.0 GENERAL INFORMATION..........................................................................................4
1.1 Intended Audience .......................................................................................................4
1.2 Preface.........................................................................................................................4
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 4
1.2.2 Class A Product Warning............................................................................................................. 4
1.2.3 Environmental Protection Statement ......................................................................................... 4
1.3 AcroPack Information –All Models...............................................................................5
1.3.1 Ordering Information ................................................................................................................. 5
1.3.2Key Features............................................................................................................................... 5
1.3.3 Key Features PCIe Interface ........................................................................................................ 6
1.4 Signal Interface Products ..............................................................................................7
1.5 Software Support .........................................................................................................7
Windows............................................................................................................................................ 7
VxWorks............................................................................................................................................ 7
Linux.................................................................................................................................................. 7
1.6 References ...................................................................................................................8
2.0 PREPARATION FOR USE..............................................................................................9
2.1 Unpacking and Inspecting.............................................................................................9
2.2 Installation Considerations .........................................................................................10
2.3 Board Configuration ...................................................................................................10
2.4 Field I/O Connector ....................................................................................................10
Table 2.1 Field I/O Connector Pin Assignments ....................................................................................11
2.5 Noise and Earth Grounding Considerations .................................................................14
2.6 Logic Interface Connector ...........................................................................................15
Table 2.2: Logic Interface Connections........................................................................................ 15
3.0 PROGRAMMING INFORMATION........................................................................... 17
CONFIGURATION REGISTERS................................................................................................................17

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Table 3.1 Configuration Registers................................................................................................ 18
Standard (Default) Mode Memory Map...............................................................................................19
Enhanced Mode Memory Map.............................................................................................................19
Table 3.2: Standard Mode Memory Map .................................................................................... 20
Table 3.3: Registers in Standard and Enhanced Mode Memory Map ......................................... 20
Table 3.4: Enhanced Mode Bank 0 Memory Map ....................................................................... 21
Table 3.5: Enhanced Mode Bank 1 Memory Map ....................................................................... 21
Table 3.6: Enhanced Mode Bank 2 Memory Map ....................................................................... 22
Interrupt Enable Status Register (Read/Write) - (BAR0 + 0x0000 0000) ...............................................23
Table 3.7 Interrupt Register....................................................................................................... 23
Module Location In System Register (Read Only) - (BAR0 + 0x0000 0004)............................................24
Table 3.8 Location Register........................................................................................................ 24
Port Registers (Standard Mode Ports 0-3, Read Only) ..........................................................................24
Enhanced Mode Select Register (Standard Mode Ports 7, Read/Write) ...............................................24
Port Registers (Enhanced Mode Bank 0, Ports 0-3, Read Only) ............................................................24
Bank Select Register 0 (Enhanced Mode Bank 0, Ports 7, Read/Write) ................................................24
Table 3.10 Enhanced Mode Register (Port 7).............................................................................. 25
Table 3.11 Enhanced Mode Bank Select ..................................................................................... 25
Event Sense Status & Clear Registers For IN00-IN31 (Enhanced Mode Bank 1, Ports 0-3, Read/Write) 25
Table 3.12 Port 0 Event Sense/Status Register (Ports 1-3 and Similar)....................................... 26
Event Interrupt Status Register for Ports 0-3 (Enhanced Mode Bank 1, Port 6, Read Only) ..................26
Table 3.13 Event Interrupt Status Register for Ports 0-3............................................................. 26
Event Polarity Control Register For Ports 0-3 (Enhanced Mode Bank 1, Ports 6, Write Only) ...............26
Table 3.14 Standard Mode Events Register (Port 7) ................................................................... 27
Bank Select Register (Enhanced Mode Bank 1, Port 7, Write Only) ......................................................27
Table 3.15 Bank Select Register (Write) ...................................................................................... 27
Bank Select Status Register 1 (Enhanced Mode Bank 1, Port 7, Read Only)..........................................27
Table 3.16 Bank Select Register (Read) ....................................................................................... 28
Debounce Control Register (Enhanced Mode Bank 2, Port 0, Read/Write) ..........................................28
Table 3.17 Debounce Control Register ...................................................................................... 28
Debounce Duration Register 0 (Enhanced Mode Bank 2, Port 1, Read/Write) .....................................28
Table 3.18 Debounce Duration Register 0:.................................................................................. 29
Debounce Reset Select Register (Enhanced Mode Bank 2, Port 3, Write Only) ....................................29
Bank Select (Write) & Status (Read) Register 2 (Enhanced Mode Bank 2, Ports 7, Read and Write) .....29
Table 3.19 Bank Select (Write) & Status (Read) Register ............................................................ 30
Software Reset Register (Read/Write, Base + 44H) ..............................................................................30
XADC Status/Control Register (Read/Write) - (BAR0 + 48H).................................................................30
XADC Address Register (Write Only) - (BAR0 + 4CH).............................................................................31
Table 3.20: System Monitor Register Map .................................................................................. 31
Table 3.21 FPGA Voltage and Temperature Range ..................................................................... 31
Firmware Revision Register (Read Only) - (BAR0 + 0x0000 0200) .........................................................31
The Effect of Reset ...............................................................................................................................31
Basic Input Operation ..........................................................................................................................32
Enhanced Operating Mode ..................................................................................................................32
Event Sensing.......................................................................................................................................33

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Change-Of-State Detection ..................................................................................................................33
Debounce Control................................................................................................................................33
Interrupt Generation ...........................................................................................................................34
Programming Example.........................................................................................................................34
4.0 THEORY OF OPERATION.......................................................................................... 37
4.1 AcroPack 440 Operation .............................................................................................37
4.2 PCIe Interface Logic ....................................................................................................37
5.0 SERVICE AND REPAIR............................................................................................... 38
5.1 Service and Repair Assistance .....................................................................................38
5.2 Preliminary Service Procedure ....................................................................................38
5.3 Where to Get Help......................................................................................................38
6.0 SPECIFICATIONS......................................................................................................... 40
6.1 Physical......................................................................................................................40
6.2 Power Requirements ..................................................................................................40
6.3 Environmental Considerations....................................................................................40
6.3.1 Operating Temperature.............................................................................................................40
6.3.2. Relative Humidity .....................................................................................................................41
6.3.3Isolation ....................................................................................................................................41
6.3.4Vibration and Shock Standards..................................................................................................41
6.3.5EMC Directives ..........................................................................................................................41
6.4 Reliability Prediction ....................................................................................................42
Table 6.4.1 AP440E-LF..........................................................................................................................42
6.5 INPUTS.......................................................................................................................42
6.6 PCIe Bus Specifications ...............................................................................................43
Table 6.6 PCIe Bus Data Rates..............................................................................................................44
APPENDIX A .......................................................................................................................... 45
AP-CC-01 Heatsink Kit Installation......................................................................................45

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APPENDIX B .......................................................................................................................... 48
Figure 1 AP440 Block Diagram .............................................................................................................48
Figure 2 AP440 and AP445 Loopback Interconnect ..............................................................................49
CERTIFICATE OF VOLATILITY ........................................................................................ 50
REVISION HISTORY ............................................................................................................ 51
1.0 GENERAL INFORMATION
1.1 Intended Audience
This users’ manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with I/O devices and
their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag,
1.2.1 Trademark, Trade Name and Copyright Information
© 2016 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final

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disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.
1.3 AcroPack Information –All Models
The AcroPack IO module are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an added 100
pin field I/O connector.
The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP440 module is a bus isolated 32-channel input module. Optical
isolation is bipolar and may be used to sense positive or negative voltages.
Each individual input includes built-in event sense circuitry with
programmable polarity, debounce, and interrupt support. Inputs also
include hysteresis for increased noise immunity. The AP440 utilizes state of
the art Surface-Mounted Technology (SMT) to achieve its wide functionality
and is an ideal choice for a wide range of industrial I/O applications that
require a high-density, highly reliable, high-performance interface at a low
cost.
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Model Number
Description
Threshold
AP440-1E-LF1
4V to 18V DC or AC peak
4V Max
AP440-2E-LF1
16V to 40V DC or AC peak
16V Max
AP440-3E-LF1
38V to 60V DC or AC peak
38V Max
Note 1: Operating temperature range for models:-40oCto 85oC.
Applications requiring operating temperatures of 70oCto 85oC
will require purchase of AcroPack Heatsink Accessory AP-CC-01.
AP-CC-01
AcroPack Heatsink Conduction
Cool Kit
See Appendix A for installation instructions.
1.3.2 Key Features
High Channel Count - Provides programmable monitor and control
of 32 optically isolated input points.
Wide Range Bipolar Input Voltage - Three model ranges provide

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interface capability for bipolar voltages from 4 to 60V DC or AC
peak (see Specifications section).
Optically Isolated - Individual bipolar opto-couplers provide
isolation. There are four groups (ports) of 8 channels, each which
include separate port commons to ensure port-to-port isolation.
Individual ports are isolated from each other and from the logic.
Programmable Polarity Event Interrupts - Interrupts are software
programmable for positive (low-to-high) or negative (high-to-low)
input level transitions on all 32 channels. Using two channels per
input, change-of-state transitions may also be configured.
Input Hysteresis - Isolated inputs include hysteresis for increased
noise immunity.
Programmable Debounce - The event sense input circuitry includes
programmable debounce times for all 32 channels. Debounce time
is the duration of time that must pass before the input transition is
recognized as valid at the FPGA input. This helps prevent false
events and increases noise immunity.
Reverse Polarity Protection - Bipolar inputs are not polarized and
are inherently reverse polarity protected.
No Configuration Jumpers or Switches - All configuration is
performed through software commands with no internal jumpers to
configure or switches to set.
Loopback Compatible with AP445 Output Module - The field side
of this model are directly compatible with those of the Acromag
Model AP445 32-Channel Digital Output Module for direct closed-
loop monitoring of the output states. The AP440 also shares the
same pinout used on the Acromag non-isolated AP408 32-Channel
I/O Module, for channels 0-31.
Module Health Monitoring- On board supply voltages and FPGA
junction temperature can be monitored for out of tolerance
conditions via XADC registers.
1.3.3 Key Features PCIe Interface
PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
Compatibility –PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.

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1.4Signal Interface Products
This AcroPack Module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a 50 pin front panel connector.
The cables and termination panels are also available. For optimum
performance with the AP440 digital I/O module, use of the shortest possible
length of shielded I/O cable is recommended.
1.5Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks
Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.

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1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
PCI Express MINI Card Electromechanical Specification, REV 1.2
http://www.pcisig.com

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive components and should only be handled at
a static-safe workstation.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Board Configuration
Power should be removed from the board when installing AP modules,
cables, termination panels, and field wiring. Model AP440 digital input
boards have no hardware jumpers or switches to configure.
2.4Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Pin assignments are unique to each AP model. Table 2.1 lists signal pin
assignments for the module field I/O connector. Every other pin of the 100
pin connector is left unconnected in order to meet the minimum creepage
distance required for 60 Volt isolation.

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Table 2.1 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
Field I/O 1
35
26
2
1
Field I/O 2
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
Field I/O 3
36
27
4
5
Field I/O 4
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
NC
37
28
6
9
Field I/O 5
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
Field I/O 6
38
29
8
13
Field I/O 7
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
Field I/O 8
39
30
10
17
ACOM
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
Field I/O 9
40
31
12
21
Field I/O 10
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
Field I/O 11
41
32
14
25
Field I/O 12
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
NC
42
33
16
29
Field I/O 13
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
Field I/O 14
43
34
18
33
Field I/O 15
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
Field I/O 16
44
35
20
37
BCOM

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40
Reserved/isolation
39
Reserved/isolation
11
11
21
42
Field I/O 17
45
36
22
41
Field I/O 18
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
Field I/O 19
46
37
24
45
Field I/O 20
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
NC
47
38
26
49
Field I/O 21
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
Field I/O 22
48
39
28
53
Field I/O 23
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
Field I/O 24
49
40
30
57
CCOM
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Field I/O 25
50
41
32
61
Field I/O 26
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
Field I/O 27
51
42
34
65
Field I/O 28
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
NC
52
43
36
69
Field I/O 29
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
Field I/O 30
53
44
38
73
Field I/O 31
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Field I/O 32
54
45
40
77
DCOM
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
NC
55
46
42
81
NC

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84
Reserved/isolation
83
Reserved/isolation
22
22
43
86
NC
56
47
44
85
NC
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
NC
57
48
46
89
NC
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
NC
58
49
48
93
NC
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
NC
59
50
50
97
NC
100
Reserved/isolation
99
Reserved/isolation
Note 1: VPX4500-CC-LF is an
example of a carrier that uses the
ribbon cable connector see image
of carrier.

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Note 2: APCe7020E-LF is an
example of a carrier that uses the
50 pin Champ connector see
image of carrier.
Input channels of this module are divided into four ports of eight channels
each. Channels of a port share a common signal connection with each other
(ACOM, BCOM, CCOM, and DCOM). Isolation is provided between ports and
between each port and the AP logic. With respect to interrupt generation
and events, event polarities may be defined as positive (low-to-high), or
negative (high-to-low) for individual nibbles (groups of 4 input lines, or half
ports). Change-of-State detection would require 2 input channels--one
detecting positive events, one detecting negative events.
Field I/O pinouts are arranged to be compatible with similar AcroPack
models. This model is directly loopback compatible with the Acromag
Model AP445 Digital Output Module. Likewise, pin assignments are
identical to those of Acromag Model AP408.
Note that the inputs of this device are bipolar, and may be connected in any
polarity with respect to the port common. Further, do not confuse port
commons with signal common. For the AP440, port common only infers
that this lead is connected common to the 8 inputs of the port (a separate
port common for each port). Likewise, the port commons of the AP440
input module and AP445 output module are normally not connected
together for loopback interconnection of the AP440 and AP445 (see Figure 2
in Appendix A)
2.5Noise and Earth Grounding Considerations
Input lines of the AP440 are optically isolated between the logic and field
input connections. Likewise, separate port commons facilitate port-to-port
isolation. Consequently, the field I/O connections are isolated from the
carrier board and backplane, thus minimizing the negative effects of ground
bounce, impedance drops, and switching transients. However, care should
be taken in designing installations to avoid inadvertent isolation bridges,
noise pickup, isolation voltage clearance violations, equipment failure, or

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ground loops.
2.6Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2.2 and noted
below).
Threaded metric M2.5 screws and spacers are supplied with the AP module
carriers and conduction cooling kit to provide additional stability for harsh
environments.
Power supplies +5, +12, and -12 Volt have been assigned to pins that are
reserved in the mini-PCIe specification. The Present signal is grounded on
the AP module. In addition, COEX1, COEX2 –wireless transmitter control
are reassigned to JTAG signals TMS and TCK. Lastly, UIM_C4, UIM_C8 –
reserved User Identity Module signals are reassigned to JTAG signals TDI and
TDO.
Table 2.2: Logic Interface
Connections
Pin #
Name
Pin #
Name
51
+5V2
52
+3.3V3
49
+12V2
50
GND
47
-12V2
48
+1.5V
45
Present2
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V3
42
N.C. (LED_WWAN#)1
39
+3.3V3
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND

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31
PETn0
32
SMB_DATA4
29
GND
30
SMB_CLK4
27
GND
28
+1.5V
25
PERp0
26
GND
23
PERn0
24
+3.3V3
21
GND
22
PERST#
19
TDI (UIM_C4)1
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1
18
GND
15
GND
16
UIM_VPP
13
RECLK+
14
UIM_RESET
11
REFCLK-
12
UIM_CLK
9
GND
10
UIM_DATA
7
CLKREQ#
8
UIM_PWR
5
TCK (COEX2)1
6
+1.5V
3
TMS (COEX1)1
4
GND
1
N.C. (WAKE#)1
2
+3.3V3
Note 1: The following mini-PCIe signals are not used by the AP440: USB_D+, USB_D-, WAKE#, LED_WPAN#, LED_WLAN#,
LED_WWAN#, W_DISABLE#, COEX1, COEX2, UIM_C4, UIM_C8.
Note 2: +5, +12, and -12 Volt power supplies have been assigned to pins that are reserved in the mini-PCIe specification. The
Present signal is tied to circuit common on the AP module.
Note 3: All +3.3Vaux power pins are changed to system +3.3V power.
Note 4: The SM bus signals SMB_CLK and SMB_DATA will be used to clock a carrier location serial stream from the carrier. These
signals are under the control of the AcroPack module.

SERIES AP440 ACROPACK
USER’S MANUAL
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3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the AP440 module.
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed
via the PCIe bus memory space and configuration spaces, only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AcroPack module is a Plug-and-Play
PCIe card. As a Plug-and-Play card the board’s base address and system
interrupt request are not selected via jumpers but are assigned by system
software upon power-up via the configuration registers. A PCIe bus
configuration access is used to access the AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request for the board.
CONFIGURATION
REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate Plug-and-
Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to
determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.

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Table 3.1 Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x7011 AP440-1E-LF
0x7012 AP440-2E-LF
0x7013 AP440-3E-LF
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space (BAR0)
5:10
Not Used
11
Subsystem ID
0x7011 AP440-1E-LF
0x7012 AP440-2E-LF
0x7013 AP440-3E-LF
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
The memory space address map for the AP440 is shown in Table 3.2. Note
that the base address for the board (BAR0) in memory space must be added
to the addresses shown to properly access these AP440 registers. Register
accesses as 32, 16, and 8-bit data in memory space are permitted.
This board is addressable in the PCIe memory space to control the
configuration and status monitoring of 32 digital input or event channels.
This board operates in two modes: Standard Mode and Enhanced Mode.
Standard Mode provides digital input voltage monitoring of 32 isolated
signal lines. In Standard Mode, each input line is configured as a simple
input without interrupts. Data is read from (or written to) one of four
groups (ports) as designated by the address and read and write signals.
Enhanced Mode includes the same functionality of Standard Mode, but adds
access to 32 additional event sense inputs connected to each input point of
ports 0-3. Individual inputs also include selectable hardware debounce in
Enhanced Mode. For event sensing, the Enhanced Mode allows a specific
input level transition (High-to-Low, Low-to-High, or Change-of-State) to be

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detected and optionally generate an interrupt.
Memory is organized and addressed in separate banks of eight registers or
ports (eight ports to a bank). The Standard Mode of operation addresses the
first group of 8 registers or ports (ports 0-3 for reading inputs, Ports 4, 5, & 6
which are not used on this model). If the Enhanced Mode is selected, then 3
additional banks of 8 registers are accessed to cover the additional
functionality in this mode (events, interrupts, and debounce). The first bank
of the Enhanced Mode (bank 0) is similar in operation to the Standard Mode.
The second bank (bank 1) provides event sense and interrupt control. The
third bank (bank 2) is used to configure the debounce circuitry to be applied
to input channels in the Enhanced Mode. Two additional mode-independent
registers are provided to enable the interrupt request line and generate a
software reset.
The memory space address map for the AP440 is shown in Table 3.2.
Note that some functions share the same register address. For these items,
the address lines are used along with the read and write signals to determine
the function required.
Standard (Default) Mode
Memory Map
Table 3.2 shows the memory map for the Standard Mode of operation. This
is the Default mode reached after power-up or system reset. Standard
Mode provides simple monitoring of 32 digital input lines without
interrupts. Data is read from or written to one of eight groups (ports) as
designated by the address and read and write signals.
To switch to Enhanced Mode, four unique bytes must be written to port 7,
in consecutive order, without doing any reads or writes to any other port
and with interrupts disabled. The data pattern to be written is 07H, 0DH,
06H, and 12H, and this must be written after reset or power-up.
Enhanced Mode Memory
Map
Table 3.3 shows the memory maps used for the Enhanced Mode of
operation. Enhanced Mode includes the same functionality of Standard
Mode, but allows each input port’s event sense input and debounce logic to
be enabled.
In Enhanced Mode, a memory map is given for each of 3 memory banks.
The first memory bank (bank 0) has the same functionality as the Standard
Mode. Additionally, its port 7 register is used to select which bank to access
(similar to Standard Mode where port 7 was used to select the Enhanced
Mode). Bank 1 provides read/write access to the 32 event sense inputs.
Bank 2 provides access to the registers used to control the debounce
circuitry of these event sense inputs.