Acromag AP220 AcroPack User manual

Series AP220 AcroPack
12-Bit Analog Output Module
AP231 AcroPack
16-Bit High Density Analog Output Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Email: [e-mail]
Copyright 2016, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501059G

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Table of Contents
1. GENERAL INFORMATION ..............................................................................................4
1.1 Intended Audience .......................................................................................................4
1.2 Preface.........................................................................................................................4
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 4
1.2.2 Class A Product Warning............................................................................................................. 4
1.2.3 Environmental Protection Statement ......................................................................................... 4
1.3 AcroPack Information –All Models...............................................................................4
1.3.1 Ordering Information ................................................................................................................. 5
1.3.2 Key Features............................................................................................................................... 5
1.3.3 Key Features PCIe Interface........................................................................................................ 6
1.4 Signal Interface Products ..............................................................................................6
1.5 Software Support .........................................................................................................6
Windows............................................................................................................................................ 7
VxWorks............................................................................................................................................ 7
Linux.................................................................................................................................................. 7
1.6 References ...................................................................................................................7
2.0 PREPARATION FOR USE..............................................................................................8
2.1 Unpacking and Inspecting.............................................................................................8
2.2 Installation Considerations ...........................................................................................9
2.3 Non-Isolation Considerations........................................................................................9
2.4 Default Hardware Configuration...................................................................................9
2.5 Programmable Register Configuration ..........................................................................9
2.6 Functional Block diagram............................................................................................10
2.7 Field I/O Connector ....................................................................................................11
Table 2.1 Field I/O Connector Pin Assignments .......................................................................... 11
68 PIN CHAMP CARRIER CONNECTOR ......................................................................... 11

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50 PIN CHAMP CARRIER CONNECTOR2........................................................................ 11
RIBBON CARRIER CONNECTOR1.................................................................................... 11
2.8 Logic Interface Connector ...........................................................................................13
Table 2.2 Logic Interface connector Pin Assignments ............................................................... 14
3.0 PROGRAMMING INFORMATION............................................................................ 15
CONFIGURATION REGISTERS................................................................................................................15
Table 3.1 Configuration Registers.............................................................................................. 16
Table 3.2: BAR0 Registers .......................................................................................................... 16
Module Location In System Register (Read Only) - (BAR0 + 0x0000 0004)............................................17
Table 3.3 Location Register........................................................................................................ 18
DAC Channel Registers (Read/Write) - (BAR0 + 0x0000 0008 to 0x0000 0044) .....................................18
Table 3.4 DAC Channel Register ................................................................................................ 18
Table 3.5 DAC Channel Control Register.................................................................................... 19
Output Data Format.............................................................................................................................20
Table 3.6 DAC Channel Data Format ......................................................................................... 20
Transparent Mode ...............................................................................................................................21
Simultaneous Mode (Read/Write) - (BAR0 + 0x0000 0048)..................................................................21
Simultaneous Output Trigger (Write Only) - (BAR0 + 0x0000 004C) .....................................................21
DAC Write Status Register (Read Only) - (BAR0 + 0x0000 0054) ...........................................................22
Control Register (Write Only) - (BAR0 + 0x0000 0058)..........................................................................22
XADC Status/Control Register (Read/Write) - (BAR0 + 0x0000 0088)...................................................23
XADC Address Register (Write Only) - (BAR0 + 0x0000 008C)...............................................................23
Table 3.7: System Monitor Register Map .................................................................................... 24
Firmware Revision Register (Read Only) - (BAR0 + 0x0000 0200) .........................................................24
Flash Data Register (Read/Write) - (BAR0 + 0x0000 0204) ...................................................................24
Table 3.8 Flash Data Register..................................................................................................... 24
Flash Chip Select (Write Only) - (BAR0 + 0x0000 0208).........................................................................24
Flash Coefficient Memory Map ............................................................................................................25
Table 3.9 Flash Coefficient Memory Map.................................................................................. 25
Table 3.10 Flash Coefficient Memory Map ASCII String Location.............................................. 26
4.0 USE OF CALIBRATION DATA................................................................................... 26
4.1 Uncalibrated Performance..........................................................................................27
AP231 Model ............................................................................................................................... 27
AP220 Model ............................................................................................................................... 27
4.2 Calibrated Performance..............................................................................................28
AP231 Model ............................................................................................................................... 28
AP220 Model ............................................................................................................................... 28
Table 3.11 AP231 Model............................................................................................................ 29

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Table 3.12 AP220 Model............................................................................................................ 29
5.0 SERVICE AND REPAIR............................................................................................... 31
5.1 Service and Repair Assistance.....................................................................................31
5.2 Preliminary Service Procedure ....................................................................................31
5.3 Where to Get Help......................................................................................................31
6.0 SPECIFICATIONS......................................................................................................... 32
6.1 Physical......................................................................................................................32
6.2 Power Requirements..................................................................................................33
6.3 Environmental Considerations....................................................................................33
6.3.1 Operating Temperature.............................................................................................................33
6.3.2 Other Environmental Requirements..........................................................................................34
6.3.2.1 Relative Humidity .......................................................................................................... 34
6.3.2.2 Isolation ......................................................................................................................... 34
6.3.3 Vibration and Shock Standards..................................................................................................34
6.3.4 EMC Directives ..........................................................................................................................34
6.4 Reliability Prediction ..................................................................................................35
AP220-16E............................................................................................................................................35
AP231-16E............................................................................................................................................35
6.5 PCIe Bus Specifications ...............................................................................................35
Table 6.5 PCIe Bus Data Rates ..................................................................................................... 36
APPENDIX.............................................................................................................................. 37
AP-CC-01 Heatsink Kit Installation......................................................................................37
CERTIFICATE OF VOLATILITY ........................................................................................ 40
REVISION HISTORY ............................................................................................................ 41

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1. GENERAL INFORMATION
1.1 Intended Audience
This users’ manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with AcroPack
devices and their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag,
1.2.1 Trademark, Trade Name and Copyright Information
© 2016 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.
1.3 AcroPack Information –All Models
The AcroPack IO module are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an add 100 pin
field I/O connector.

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The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP231 is a 16-bit, high-density, single-width AcroPack module, with the
capability to drive up to 16 analog voltage output channels. The AP231
utilizes state of the art Surface-Mounted Technology (SMT) to achieve its
high channel density and is an ideal choice for a wide range of industrial
control and monitor applications that require high-density, high-reliability,
and high-performance at a low cost.
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Model Number
Description
Temp Range
AP220-16E-LF1
16-Channel 12-Bit Analog Output
-40°Cto 85°C
AP231-16E-LF1
16-Channel 16-Bit Analog Output
-40°Cto 85°C
Note 1: Applications requiring operating temperatures of 70°C to 85°C will
require purchase of AcroPack Heatsink Accessory AP-CC-01 and minimum
airflow of 400LFM. For temperatures below 70°C the module will require a
minimal airflow of 200LFM
AP-CC-01 AcroPack Conduction Cool Kit (See Appendix for
installation instructions)
1.3.2 Key Features
•High Channel Count –Individual control of up to 16 analog voltage output
channels is provided.
•AP220, 12-Bit Accuracy - Each channel contains its own 16-bit, Digital to
Analog Converter (DAC) with 7.5uS output settling time.
•AP231, 16-Bit Accuracy - Each channel contains its own 16-bit, Digital to
Analog Converter (DAC) with 7.5uS output settling time.
•Software selectable outputs - Provides 6 Unipolar/bipolar voltage range
outputs:
▪unipolar, 0V to +10 Volts, 0vV to +5 Volts
▪bipolar, +/-10 Volts, +/-5 Volts, +/-3 Volts, +/- 2.5V to 7.5
Volts
•Reliable Software Calibration - Calibration coefficients stored on-board
provide the means for accurate software calibration of the module.

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•Individual Output Control - Output channels can be individually selected
and updated with a single channel data write command when using the
"transparent" output mode.
•Simultaneous Output Control - All output channels can be simultaneously
updated with a single software trigger command when using the
"simultaneous" output mode (DAC's are double-buffered which allows
new data to be written to each channel before the simultaneous trigger
updates the outputs).
•Easy Mode Selection - Selection of transparent and simultaneous output
modes is easily done via software commands.
•Reset is Failsafe - Outputs reset to 0 volts following a power up or reset.
•Alarm –Software readable, monitor Brownout, short circuit and Die
temperature >150C.
1.3.3 Key Features PCIe Interface
•PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
•Compatibility –PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.
1.4 Signal Interface Products
This AcroPack Module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a front panel connector.
The cables and termination panels are also available. For optimum
performance with the AP231 analog output module, use of the shortest
possible length of shielded I/O cable is recommended.
1.5Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks

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Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.
1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
•PCI Express MINI Card Electromechanical Specification, REV 1.2
https://www.acromag.com

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, a minimum of 200 LFM of air circulation must be
provided to prevent a temperature rise above the maximum operating
temperature and to prolong the life of the electronics. If operating in an
ambient temperature of > 70⁰C a heatsink is required as well as 400 LFM of
Air circulation. If the installation is in an industrial environment and the
board is exposed to environmental air, careful consideration should be given
to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Non-Isolation Considerations
The board is non-isolated, since there is electrical continuity between the
PCIe bus and AcroPack module grounds. As such, the field I/O connections
are not isolated from the system. Care should be taken in designing
installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.
2.4 Default Hardware Configuration
A board is shipped from the factory configured as follows:
•Internal 12 Volt power supplies are used (sourced from PCI Local
Bus connectors).
•Analog output bipolar range is -10 to +10 Volts.
•Software programmable register bits are undefined at reset, but the
board defaults to 0 Volts on all analog outputs and the Simultaneous
Channel Update Mode (see Section 3).
2.5Programmable Register Configuration
Programmable registers are software configurable. That is, there are no
hardware jumpers associated with them. Registers must be accessed to
select the desired mode of operation and to update analog outputs (refer to
Section 3 for details).

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2.6 Functional Block diagram

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2.7Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Threaded metric M2.5 screws and spacers are supplied with the module to
provide additional stability for harsh environments.
Pin assignments are unique to each AP model. Table 2.1 lists signal pin
assignments for the module field I/O connector. Every other pin of the 100
pin connector is left unconnected in order to meet the minimum distance
required for 60 Volt isolation.
Table 2.1 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
CH0+
35
26
2
1
Signal Return
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
CH1+
36
27
4
5
Signal Return
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
CH2+
37
28
6
9
Signal Return
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
CH3+
38
29
8
13
Signal Return
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
CH4+
39
30
10
17
Signal Return
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
CH5+
40
31
12
21
Signal Return
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
CH6+

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41
32
14
25
Signal Return
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
CH7+
42
33
16
29
Signal Return
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
CH8+
43
34
18
33
Signal Return
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
CH9+
44
35
20
37
Signal Return
40
Reserved/isolation
39
Reserved/isolation
11
11
21
42
CH10+
45
36
22
41
Signal Return
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
CH11+
46
37
24
45
Signal Return
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
CH12+
47
38
26
49
Signal Return
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
CH13+
48
39
28
53
Signal Return
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
CH14+
49
40
30
57
Signal Return
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
CH15+
50
41
32
61
Signal Return
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
51
42
34
65
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70

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52
43
36
69
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
53
44
38
73
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
54
45
40
77
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
55
46
42
81
84
Reserved/isolation
83
Reserved/isolation
22
22
43
86
56
47
44
85
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
57
48
46
89
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
EXT_VSS_DAC
58
49
48
93
Signal Return
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
EXT_VDD_DAC
59
50
50
97
Signal Return
100
Reserved/isolation
99
Reserved/isolation
2.8Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on the carrier board.
The pin assignments of this connector are standard for all AP modules according to the PCI
Express MINI Card Electromechanical Specification, REV 1.2 (with exceptions shown in Table
2.2 and noted below).
Power supplies +5, +12, and -12 Volt have been assigned to pins that are reserved in the
mini-PCIe specification. The Present signal is grounded on the AP module. In addition,
COEX1, COEX2 –wireless transmitter control are reassigned to JTAG signals TMS and TCK
Lastly, UIM_C4, UIM_C8 –reserved User Identity Module signals are reassigned to JTAG
signals TDI and TDO.

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Table 2.2 Logic Interface connector Pin Assignments
Pin #
Name
Pin #
Name
51
+5V1,2
52
+3.3V3
49
+12V1,2
50
GND
47
-12V1,2
48
N.C. (+1.5V)1
45
Present4
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V3
42
N.C. (LED_WWAN#)1
39
+3.3V3
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA
29
GND
30
SMB_CLK
27
GND
28
N.C. (+1.5V)1
25
PERp0
26
GND
23
PERn0
24
+3.3V3
21
GND
22
PERST#
19
TDI (UIM_C4)1
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1
18
GND
15
GND
16
N.C. (UIM_VPP)1
13
RECLK+
14
N.C. (UIM_RESET)1
11
REFCLK-
12
N.C (UIM_CLK)1
9
GND
10
N.C. (UIM_DATA)1
7
CLKREQ#
8
N.C. (UIM_PWR)1
5
TCK (COEX2)1
6
N.C. (+1.5V)1
3
TMS (COEX1)1
4
GND
1
N.C. (WAKE#)1
2
+3.3V3
Note 1: Signals are not applicable for the AP220 and AP231 implementation. Pins are either
“no connects” on the module or are repurposed for JTAG.
Note 2: +5V, +12V, and -12V power supplies have been assigned to pins that are reserved in
the mini-PCIe specification.
Note 3: All +3.3Vaux power pins are changed to +3.3V power.
Note 4: The Present signal is tied to circuit common on the AP module.

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3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the AP220 or AP231 module.
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed
via the PCIe bus memory space and configuration spaces, only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AP220 or AP231 module is a Plug-and-
Play PCIe card. As a Plug-and-Play card the board’s base address and system
interrupt request are not selected via jumpers but are assigned by system
software upon power-up via the configuration registers. A PCIe bus
configuration access is used to access an AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request assigned to the board.
CONFIGURATION REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate Plug-and-
Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to
determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.

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Table 3.1 Configuration Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x701A AP220
0x701B AP231
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space (BAR0)
5:10
Not Used
11
Subsystem ID
0x701A AP220
0x701B AP231
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
The memory space address map for the AP220 or AP231 is shown in Table
3.2. Note that the base address for the board (BAR0) in memory space must
be added to the addresses shown to properly access these AP220 and AP231
registers. Register accesses as 32, 16, and 8-bit data in memory space are
permitted. All the registers of the AP220 or AP231 are accessed via data
lines D0 to D31.
Table 3.2: BAR0 Registers
Note that any registers/bits not
mentioned will remain at the
default value logic low.
BAR0 Base Address
Bit(s)
Description
0x0000 0000
31:0
Not Used
0x0000 0004
7:0
Location in System Register
0x0000 0008
31:0
DAC Channel 0
0x0000 000C
31:0
DAC Channel 1
0x0000 0010
31:0
DAC Channel 2
0x0000 0014
31:0
DAC Channel 3

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0x0000 0018
31:0
DAC Channel 4
0x0000 001C
31:0
DAC Channel 5
0x0000 0020
31:0
DAC Channel 6
0x0000 0024
31:0
DAC Channel 7
0x0000 0028
31:0
DAC Channel 8
0x0000 002C
31:0
DAC Channel 9
0x0000 0030
31:0
DAC Channel 10
0x0000 0034
31:0
DAC Channel 11
0x0000 0038
31:0
DAC Channel 12
0x0000 003C
31:0
DAC Channel 13
0x0000 0040
31:0
DAC Channel 14
0x0000 0044
31:0
DAC Channel 15
0x0000 0048
31:0
Simultaneous Mode
0x0000 004C
31:0
Simultaneous Output Trigger
0x0000 0050
31:0
Not Used
0x0000 0054
31:0
DAC Write Status
0x0000 0058
31:0
DAC Reset Control
0x0000 005C→0x00000084
31:0
Not Used
0x0000 0088
XADC Status/Control Register
0x0000 008C
XADC Address Register
0x0000 0090→0x000001FC
Not Used
0x0000 0200
31:0
Firmware Revision
0x0000 0204
7:0
Flash Data
0x0000 0208
Bit-0
Flash Chip Select
0x0000 020C→0x000007FF
31:0
Not Used
Module Location In System Register (Read Only) - (BAR0 + 0x0000 0004)
This read only register is used identify the module’s plugin location in a
system.

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Table 3.3 Location Register
Note that any registers/bits not
mentioned will remain at the
default value logic low.
This feature was implemented
on the Revision B boards.
Bit(s)
FUNCTION
2 to 0
Module Site Location Bits. These bits identify the location on
the carrier of the AP module.
000
Carrier Site A
001
Carrier Site B
010
Carrier Site C
011
Carrier Site D
7 to 3
Module Slot Location Bits. These bits identify the slot location
of the AP module in a system. The Carrier may use backplane
signals as in a VPX system or a carrier DIP switch to uniquely
identify the system location of the carrier.
XXXXX
System Slot identification bits are described by the
AcroPack carrier card.
31 to 8
Not Used
DAC Channel Registers (Read/Write) - (BAR0 + 0x0000 0008 to 0x0000 0044)
Sixteen (16) DAC Channels registers are used to write and read the DAC 24-bit
control/data values. Writing to the address of the specific register enables
transfer of data and control of the DAC. Read of the specified register returns
the DAC data or control value as requested. All reads requires write of two
read commands to complete serial shift out of the DAC data or control value.
Then read the DAC channel register will contain the read data in the lower 16
bits for AP231 and bits-15 to 4 of the AP220. See Table 3.5 for the allowed
DAC write and read commands.
The contents of the DAC Channel registers are transferred to their
corresponding converter input buffer serially. This serial data transfer take
1.6µs. Thus, a new write of the same DAC register can be performed no
sooner then 1.6µs after the previous write. A DAC Write Status register, at
base address plus 54H, is available as a write operation busy status indicator.
The channels Status bit will be set low upon initiation of a write operation
and will remain low until the requested write operation has completed. New
write accesses to the same DAC Channel register, should not be initiated
unless its write busy status bit is set high. Read of the DAC registers must
also wait 1.6µs after issue of two read commands. Thus you avoid read of the
register as it is being serially shift out.
Table 3.4 DAC Channel Register
Bit(s)
FUNCTION
15 to 0
Data 16-bits or Control register data with issue of 0100
commend or DAC data when issued of 0001 or 0011.
19 to 16
Address 4-bits
0000
No Operation
0001
Write to input register (no DAC output update input
register only written.) Used for simultaneous mode

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0010
Update DAC register from input register (Updates
DAC output voltage). Software equivalent of LDAC
0011
Write and update DAC register (Updates the input
register and DAC register irrespective of LDAC) Use
for transparent mode
0100
Write to control register
0101
No operation
0110
No operation
0111
Software data reset (Reset to zero scale, midscale, or
full scale as specified by PV1 and PV0 bits of control.)
1000
Reserved
1001
Disable daisy-chain functionality (Default enabled)
Leave enabled for SDO read-back operation.
1010
Readback input register (Provides contents of input
register after issue of two commands and 1.6µs.)
1011
Readback DAC register (Provides contents of DAC
register after issue of two commands and 1.6µs.)
1100
Readback control register (Provides contents of
control register after issue of two commands and
1.6µs. See Table 3.6 for description of DAC Control
register.)
1101
No operation
1110
No operation
1111
Software full reset (Device set to power up state,
output at AGND and output buffer is powered down.)
20
0 (This bit must be fixed at 0)
31 to 21
Not Used
Table 3.5 DAC Channel Control Register
Bit(s)
FUNCTION
2 to 0
3-bits Output Range (Software full reset is also issued when
the output range is reconfigured.)
000
-10V to +10V
001
0V to +10V
010
-5V to +5V
011
0V to +5V
100
-2.5V to +7.5V
101
-3V to +3V
110
0V to 16V (external power supply, contact Acromag)
111
0V to 20V (external power supply, contact Acromag)
4 to 3
2-bits Power-up Voltage
00
Zero scale
01
Midscale
10
Full scale
11
Full scale