ADC SUPER SIX S-100 User manual

SUPER SIX
5 .. 100 ,Single>Board
Computer TechnlcCllManual
"

SUPER SIX™
S-100 Single Board Computer
Technical Manual
June 1, 1983
ADVANCED DIGITAL CORPORATION

SECTIO(\l
TABLE OF CONTENTS
TITLE
PAGE
SECTION I - 1NTRODUCTH .. 'l(\l
1.1 Purpose
1.2 Equipment Overvie\N
1.3 Document Organization
1.4 List of Acronyms
1.5 Document Maintenance
1.6 Theory of Operation
SECTIO N 11 - OPERA TION
2.1
Floppy Disk Controller
2.2 128K Dynamic RAM
2.3 System Monitor EPROM
2.4 Serial Ports
2.5 Parallel Ports
2.6 Real Time Interrupt Clock
2.7 S-lOO Bus Interface
2.8 Baud Rate Jumper
2.9 EPROM and Monitor Operations
2.9.1 EPROM Enable and Disable
2.9.2 Monitor Sign-on
2.9.3 Monitor Commands
2.9.4 Cold Start Program
2.10 RAM Organization
2.11 Z80A DMA Features
2.12 PSNET/I0peration
2.13 PS NET /PAR Operation
2. Jif Synchronous Operations
2.15 Power Consumption
SECTION HI - IN PUT /OUTPUT POR IS
3.1 Input/Output Port Assignments
3.2 Input/Output Descriptions
3.2.! Port 00
3.2.2 Port 01
3.2.3 Port 02
3.2.4 Port 03
3.2.5 Port 04
3.2.6 Port OJ
3.2.7 Port 06
3.2.8 Port 07
3.2.9 Port 08
3.2.10 Port 09
3.2.11 Port OA
3.2.12 Port OB
3.2.13 Port OC
3.2.14 Port 00
3.2.15 Port OE
3.2.16 Port OF
3.2.17 Ports 10-13
1
1
1
2
2
3
3
4
4
4
5
5
.5
.5
.5
7
7.
7
8
8
10
11
11
lA
12
12
12
13
13
14
14
14
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
All information contained in this document is the property of Advanced Digital
Corporati.on.

TABLE OF CONTENTS (continued)
SECTION
nILE
PAGE
3.2.18 Port 14
3.2.18.1 Port 14 Read Operation
3.2.19 Port 15
3.2.19.1 Port 15 Read Operation
3.2.19.2 Port 15 Write Operation
3.2.20 Ports 16 and 17
3.2.20.1 Port 17 \\-rite Operation
3.2.20.2 Port 17 Write Operation
3.2.21 Ports 18-18
16
j6
17
17
17
17
18
1'7
21
22
22
23
23
23
23
24
24
24
24
24
25
25
25
26
26
26
27
27
27
28
28
28
28
28
28
29
29
29
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.1 1
4.3.14
4.3.16
4.3.17
4.3
SECTION IV - JUMPER CONNECTIONS
4.1 Jumper Definitions·
4.2 Jumper Descriptions
4.2.1 Jumper A
4.2.2 Jumper B
4.2.3 Jumper C
4.2.4 Jumper D
4.2.5 Jumper E
4.2.6 Jumper G
4.2.7 Jumpers Hand T
4.2.8 Jumper J6
4.2.9 Jumper R25
4.2.10 Jumper J7
4.2.11 Jumpers P, N, M, K, J, R, S, and F
Factory and OEM InstaHed Jumpers
8-lnch Floppy Disk Drive
~hugart SA800/801 Disk Drive
Shugart 850 Disk Drive
MFE Model 700 Disk Drive
Tandon Slim Line Disk Drive
NEC Model FDl160 Disk Drive
QUME Data Track Disk Drive
Tandon 5.25 Inch Disk Drive
Mitsubishi Model 2894 Disk Drive
Mitsubishi Model 2896 Disk Drive
Shugart SA 860 Disk Drive
Siemens FDD-100-8 Disk Drive
Qume Trak 592 5.25 Inch Disk LJrive
All Other Disk Drives
SECTION V - EXTERNAL CONNEC10R PINS
5.1 Connector S-100
5.2 Connector J2
5.3 Connector J3
5.4 Connector J4
5.5 Connector J5
30
30
31
32
33
33

SECTION
TABLE OF CONTENTS (continued)
TITLE
APPENDIX A - Z80A/Z80B SIO AND DART
APPEN DIX B - Z80A/Z80B PIO
APPENDIX C - Z80A/Z80B CTC
APPEN DlX D - Z80A/Z80B CPU
APPENDIX E - Z80 DMA
APPENDIX F - FLOPPY DISK CONTROLLER
APPENDIX G - FLOPPY DISK ERROR CODES
APPENDIX H - APPLICATION NOTES
APPENDIX I - SUPER SIX WARRANTY
APPENDIX J - PAR TS LAYOUT AND LIST
APPENDIX K - PLL REALIGNMENT
APPENDIX L - PSNET/l SCHEMATICS
APPENDIX M - PSN ET/PAR SCHEMATICS
APPENDIX N - SUPER SIX SCHEMATICS
LIST
OF FIGURES
FIGURE NO. TITLE PAGE
2-1 SUPER SIX
Interface To the S-100 Bus 6
2-2
SUPER SIX RAM Configuration 11
LISl OF TABLES
TABLE NO. TITLE
PAGE
1-1
List Of Acronyms
2
2-1 SUPER SIX Baud Rate Jumper Settings 7
2-2
Monitor Commanos For the SUPER SIX 9
3-1
I/O Port Assignments For the SUPER SIX 13
3-2
SUPER SIX Port 18 Baud Rate Settings
21
4-1 SUPER SIX
Jumpers and Abbreviated Functions
22
5-1 SUPER SIX J 1
Connector Pin Functions
30
5-2
SUPER SIX J2 Connector Pin Functions
31
5-3 SUPER SIX
J3 Connector Pin Functions
32
5-4 SUPER SIX J4 Connector Pin Functions
33
5-5
SUPER SIX J5 Connector Pin Functions
33

I. I
SECTION I
INTRODUCTION
PURPOSE
This Manual provides the technical information necessary to In,:>tall, operate dno maintair
the SUPER SIX singleboard computer by Advanced Digital Corporation.
1.2 EQUIPMENT OVER VIEW
SUPER SIX, produced by Advanced Digital Corporation, is the first single boara computer
for the S-IOO bus running at 6MHz. Without the S-100 bus the SUPER SIX can also run as
a standalone computer executing a single user CP/M 2.2 or 3.0, or amultlUser MP/M~
OASIS, or TurboDOS operating system. SUPER SIX runs substantially faster than any
other S-100 single board computer avialable in the market.
The SUPER SIX contains the following set of capabilities:
I. Z80B CPU operating at 6MHZ
2. 128K
of dynamic bank select RAM arranged in 16k banks
3. Floppy Disk Controller which supports the 8-inch and 5.25-inch disk
drives simuitaniously
4. 2/4 K of shadow EPROM (Monitor)
5. 2 serial I/O (RS-232) ports offering software or hardware selectable
baud rate, Z80B DART
6. 2
parallel ports (Z80B PIO)
7.
Real time clock (Z80B CTC)
8. DMA controller (Z80 DMA)
9. Extended addressing: A16-A23
10.
Single 5 volt supply on board
Ii. One-year warranty
12. Free copy of CP/M 2.2 BIOS supplie_d.
*NOTE: Items 5 and 6reqUire external adaptation for
RS-232 and Centronics. The adapter boards contain a
DB-25
connector on a 2-inch by 2-inch board attached to
the back panel of the S-IOO system (MODEM and RS 422
Paddle cards are also available).
-1-

1.3 .
This document is organized inh' ) St',:t i,'"~ ~lIld 14 J.ppendices.
Section I serves as an introduction to the entire document, stating the purpose of the
document and providing an introduction to the SlJPER SIX single board computer. This
section also provides a list of acronyms used in the document and provides a statement on
the responsibilities of document maintenance.
Section II provides a description of the operations of aU components associated with the
SUPER SIX single board computer.
Section III lists aD SUPER SIX input/output ports and defines the assignments and
functions of each port.
Section IV lists and defines all SUPER SIX jumper connections •. This section includes the
jumper assignments for factory (OEM) installed jumpers.
Section V describes the external connector pins for SUPER SIX connectors J I through J5.
The appendices provide supplemental material to the body of the text and' are referenced
in the text at the associated points.
1.4 LIST
OF ACRONYMS
.\
Table 1-1 provides a listing and description of the acronyms used within this text.
ACRONYM DESCRIPTIOt\l
CPU
Central Processor Unit
CTC Controller trimer Circui t
DART Dual Asynchronous
Receiver/Transmitter
DMA Direct Memory Access
EPROM
ElectricaHy Erasable Programmable Read-Only Memory
FOe
Floppy Disk ControHer
IEEE
Institute of Electrical and Electronic Engineers
MP/M
Multiuser Program For Microcomputers
OEM
Original Equipment Manufacturer
PIO
ParaDel Input/Output
PROM
Programmable Read-Only Memory
Table 1-1. List of Acronyms
-2-

Tilble I-I. List of Acronyms (Continued)
ACRONYM
DE~U-<[PTIOi\
RAM Random Access Mernory
SIO
Serial Input/Output
TTL
Transistor-transistor Logic
TurboDOS
A
Multiuser
Networking
Operating
System used
as software with
the
SUPER SIX
1.5 DOCUMENT MAINTENANCE
This document is the property of Advanced Digital Corporation, who is responsible for its
content. Any modifications made to this manual must be made with the exptess written
approval of Advanced Digital Corporation.
1.6 THEORY
OF OPERATION - START-UP PROCEDURE
The SUPER SIX Single board computer is shipped configured for 19.
installation procedure is as follows: baud
rate. The
I. Plug the PSNET II to connector 35. Use caution; pin Iis marked.
2. Connect the CRT. Pins 2, 3, 5, 7, and 20 must be used; no parity
must be specified,
3. Apply power to the system. The monitor message shown in
subsection 2.9.2 appears. Check the CRT baud rate; if 9600 baud is
required, unplug jumper area 37, pin 7-8.
,4. Install the floppy disk cable, load the CP 1M diskette, and bootstrap
the system.
Note: CP/M is shipped configured for 64K bytes of
memory. The parallel port is configured as the default
printer. 1024 bytes per sector read/writes are also'
supported (or DMA). The plus 8V and the plus/minus 16V
on the S-IOO bus must be verified prior to installing the
SU PER SIX board.
-3-

SECTION II
OPERATION
This section describes the operation of all SUPER SIX components.
2.1
FLOPPY DISK CONTROLLER
The floppy disk controller can access up to four 8:'inch or four 5.25-inch disk drives or any
combination of the two. The controller can read and write IBl\\ 3740 single density format
and double density 1024 sector-SIze formats. Data transfer is performed via Direct
Memory Access (DMA). Due to the simultanious operation capability of the SUPER SIX
the format compatibility problems with 5.25-inch disks have Deen eliminated. The floppy
disk controller used is the W D27~3. The WD2793 has on-chip PLL data separators and
on-chip write pre-compensation logic. Adjustments for PLL are factory set dno write
pre-compensation has been provided with the SUPER SIX. 50 Pin and 34 pin connectors
are available for 8-inch and 5.25-inch disk drives respectively.
NOTE: Customer adjustment of trim pots
may result in cancellation of warranty.
2.2
THE l28K DYNAMIC RAM
The 128K RAM array can be switched ON and OFF in 16K increments, (O-loK, 16K-32K,
32K-48K, 48K-64K for both banks) under software control. This feature allows the CPU
to access bank switchable external memory on the 5-100 bus. The memury tlas an access
time of 150ns. A Refresh operation is performed during 280 MI cycles and during W AlI
and RESET states. The memory can be accessed by floppy dISk via DI\iIA, serial and
paralielljO, or another DMA device un the S-IOO bus.
*NOTE: Any external DMA deVIce that is
using continous mode DMA cycles must
transfer data at an average rate of 15ms per
byte or faster when holding the DMA request
line for more than 1.5ms. The RAM row
address is the low order address; therefore
the entire RAM array is refreshed by DMA
device every i 28 contiguous memory cycles.
Under CPM 2.2 or CPM 3.0 the additional 64K can be used as adiSk buffer. The SUPER
SIX is ideal when operating in the bank mode under CP jM 3.0, as 128K l{AM is required.
-4-

2.3 SYSTEM MONITOR EPkOlv\
The system monitor t.P~OM is switched UN during reset. It Cdll tJ(: dl<,<.lt)J(:O dr,G enabled
under software control. When enabled, the system JllOl,llor r<:,>lrj(:') dt locations
F800-FFFF (hex) (refer to subsection 2.'::1.1.2) when uSIng L716 LI'I<U,\\ or i:1t locations
FOOO-FFFF (hex) when using the 2732 EPR.l)M. lhc systelrr fflonitor tPl:--Cltv! contains the
cold-start loader for CP/M, MP/M and TurboDCIS. In .:.IdUltiol' It Ci:1n be used to perform
LOAD, I/O READ and 1/0 ~l{nE operations. ~hen the LPHU,vi IS disableo no system
address space is used.
2.4 SERIAL
puR TS
A6MHz Z80tl DART is used for the two serial I/U ports; aZ80B SIO or Z80A DAR T can
be used in it's place Of a4MHz Z80A DAR1is used the CPU and all other devices must
also be 4MHz). This allows asynchronous serial data communication plus a variety of
interrupt modes. Modem control signals are available at each serial connector. There are
software selectable baud rates as weB as hardware selectable baud rates (mini-jumpers
J7).
*NOTE: The serial ports are TTL and must
be connected to PS NE T/ 1 (serial adapter
interface) for RS-232 communications. The
J4 connector is for the CRT; the J5
connector is for the serial printer or CR 1.
2.5
PARALLEL POR TS
A6MHz Z80B PIO is used as the parallel port. The "A" channel of this chip is used to
connect the paraHel port connector (J2) to PIO. This port has an 8-bit bi-directional data
line and two hand-shake lines. 1 he "B" port can be split between the parallel port
connector and the S-100 bus vectored interrupts lines by jumper options. This allows the
port to be used as an additional parallel port, an interrupt controller, or both of the
above. In the output mode the parallel ports can drive one TTL load.
2.6
RtAL TIME INTERRUPT LLOCK
A6MHz Z80/:) CTC is used for providing a real time system clock for lVIP /M or TurboD05
operating systems. Three channels of the CTC are available to the user for jumpering to
synchronous baud rates or long clock times.
2.7
S-100 BUS IN1ERFACE
The 5-100 bus interface provides the signals necessary for an 8-bit bus master as
described by the lEEE-696 bus specification. Vectored interrupt lines VIO-VI7 are
supported via jumper options (refer to section I V) and A 16-A23 are also supported via an
I/O port. The Phantom line is also implemented for the dynamic H.AM array.
The SUPER SIX interface with the 5-100 bus is depicted in Figure 2-1.
Turbol)O~ is the registered trademark of Software 2000, Inc.
CP/M and MP/M are the registered trademarks of Digital Research, Inc.
-5-

I
Cj'.
,.
CONNECTOR
J3
CONNECTOR
CONNECTOR
CONNECTOR
J2
J4 J5
CONNECTOR
JUMPERS
Jl
B
A
P:ARAlLEL
SERIAL PORTS
PORTS
FLOPPY DISK
f--
DMA
CONTROLLER
EPROM
CLOCK
CPU
2K,4K
RA~ ARRAY
RAM ARRAY
64K
c- ..f\
,
1
DATA
S~100
RECEIVERS/
ADDRESS
DRIVERS
DRIVERS
VI
LINES
5-100 BUS
I
Flgurc ,~.:. SUPER -"IX Interface to the 5-100 Bus

2.8
BAUD RATE JUMPER
Upon SUPER SIX initialization, the baud rate for the two serial channels can be
hardware-selected independently by means of the baud rate jumper (J7). This 7-pole
jumper is located between U70 and U68 and is divided into two sets of jumpers containing
four and three pins for SIO channels A and B, respectively. Pins 7, 6, 5, and 4 set the baud
rate for SIO channel A and are designated as A, B, C, and D, respectively; pins 3, 2, and I
set the baud rate for SIO channel B and are designated as A, B, and C, respectively.
Because this jumper comprises of only seven pin sets, SIO channel B has a hardware
limitation of 1200 baud; by means of port 18 the software may be set to allow up to 19.2K
baud for channel B. The baud rate settings, as determined by this jumper, are shown in
Table 2-1, below. Once the SUPER SIX is initialized, I/O port 18 is used to modify the
baud rate. Port 18 is described in subsection 3.2.2 L
BIT BIT BIT BIT
BAUD
DCB A
RATE
0000
50
000I75
00I0110
00I I 134.5
0I 0 0150
0I0I
300
0I I 0
600
0I I I 1200
I0 0 01800
I0 0 I
2000
I0I0
2400
I0I I
3600
II00
4800
I I 0I
7200
II I 0
9600
III I
19,200
Table 2-1. SUPER SIX Baud Rate Jumper Settings
2.9
EPROM AND MONITOR OPERATION
The on-board EPROM occupies addresses FOOO-FFFF (hex). This EPROM is switched ON
automatically during RESET or POWER-ON. It contains the serial input/output (SIO) and
floppy disk controller (FDC) initialization code along with a simple debugger and floppy
disk cold-start loader. After the operating system is loaded the EPROM can be turned
OFF to allow access to the RAM at address FOOOH-FFFFH. The EPROM can be enabled
or disabled at any time to permit the calling of hardware dependant I/O routines.
2.9.1
EPROM Enable/Disable
A listing of-the program required to enable and disable the EPROM is provided below
-7-

BAUD RATE JUMPERS
ADVANCED DIGITAL CORPORATION SUPER SIX SUPPLEMENT
Update for Page 7
With the Super Six component side facing you and the S-100 connector down there
are 7 jumpters between U68 and U70 aligned vertically. There are assigned as
follows:
console -SIO CH. A=
-SIO CH. B=
<' III
bit A
II II
bit B
JUMPER INSTALLED 1
IIlI
bit C
IIlI bit D
JUMPER OFF = 0
~""
bit A
IIlI
bit
B
II II
bit
C
in 15
ani 7f (for 50 to 1200 baud. for 1800 to
19.2k type ori 80)
out 18
jmp 0
(CR)
0104
0106
0109
-gO
Bit D for SIO CH. B is not available as a jumper and must be set in software.
Bit 7 of this input, port (port 15) is instead used to sense double sided drives.
Some software reads this bit and sends it to the SIO CH. B baud rate anyway. If
you have double sided drives, this will make the bit a 0 thru creating baud rates
from 50 to 1200. If you have single sided drives, this will make the bit a 1
and create baud rates from 1800 to 19.2K. If you experience a problem with this
you can make a file under cpm to correctly assign the baud rate to SIO CH. B
(used for serial printer and/or modem) as follows:
A>ddt
-a100
0100
0102
A)save 1 setbaud.com
A)setbaud
COMMON BAUD RATE SETTINGS
Console
19.2k
Console
19.2k Console 9600
SIO CR. B=300 SIO
CR. B=1200
(ON )
(ON)
(off)
(ON )
(ON .)
(ON )
(ON )
(ON )
(ON )
(ON )
(ON )
(ON)
(ON )
(ON)
(off)
(ON )
(ON)
(ON)
Console 12
(ON )
(ON )
(ON )
(off)
7A

2.9.1.1 Enabling the EPROM:
F033 JE4F
F035D316
MVI A,OIOOIIIIB
OUT 16H
;RESET POWER ON JUMP AND
ENABLE MEMORY, EPROM ON
;WRITE TO CONTROL PORT
2.9.1.2
Disabling the EPROM: .
FOJ33E4F
F035 0316
MVI A,OIIOIIIIB
OUT 16H
!
;KESET POWER ON JUMP AND
ENABLE MEMORY, EPROM OFF
;WRITE TO CONTROL PORT
Jumper R25 configures the board to accept a 2716 or 2732 EPROM (as described in
section IV).
NOTE: The EPROM is always addressed at
location F800 (hex) and can not be moved.
Since the 2716 EPROM is 2K long it appears
twice, at location F800-FCOO (hex) and at
location FBFF-FFFF (hex).
2.9.2 Monitor Sign-on
The monitor signs-on with the following messages:
ADVANCED DIGITAL CORP.
Monitor Version 3.6
April -1983
Press "HI! for help
2.9.3
Monitor Commands
The monitor commands are shown in table 1.-2.
-8-

COMMAND
B
D ssss qqqq
F ssss qqqq bb
G AAAA
I pp
L aaaa
M ssss qqqq dddd
o pp dd
ESC
FUNCTION
Loads the disk-boot loader
Dumps memory in hex starting at user-specified address
ssss and ending at user-specified address qqqq
Fills memory from user-specified address ssss to
user-specified address qqqq with bb
Goes to address AAAA
Input to user-specified port pp
Loads memory starting at user-specified address aaaa
Moves the contents of user-specified starting address
ssss through user-specified ending address qqqq tp the
user-specifiea starting address of dddd
Output user-specified data dd to port pp
Terminates any command
Table 2-2. Monitor Commands For the SUPER SIX
The cold-start loader will select and home drive O. 1 rack 0 sector 1will be read into
memory at location o. Single density is assumed for track O. if an error occures an error
code will be printed. The error code must be translated using the table in appendex G.
-Sl-