VersaLogic Fox VL-EPM-19 User manual

Programmer’s
Reference
Manual
REV. April 2019
Fox
(VL-EPM-19)
DMP Vortex86DX2 SoC-based
SBC with dual Ethernet, Video,
USB, SATA, Counter/Timers,
Mini PCIe, microSD, GPIO,
SPX, and PC/104-Plus Interface

EPM-19 Programmer’s Reference Manual ii
WWW.VERSALOGIC.COM
12100 SW Tualatin Road
Tualatin, OR 97062-7341
[phone]
Fax [phone]
Copyright © 2015-2019 VersaLogic Corp. All rights reserved.
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
PC/104 and the PC/104 logo are trademarks of the PC/104 Consortium.

EPM-19 Programmer’s Reference Manual iii
Product Release Notes
Release 1
First release of this document.
Release 1.1
Removed 8254 interrupt information.
Support
The EPM-19 support page, at http://www.versalogic.com/private/foxsupport.asp contains
additional information and resources for this product including:
Reference Manual (PDF format)
Operating system information and software drivers
VersaAPI Version 1.2.0 and later
Data sheets and manufacturers’ links for chips used in this product
BIOS information and upgrades
Utility routines and benchmark software
This is a private page for EPM-19 users that can be accessed only be entering this address
directly. It cannot be reached from the VersaLogic homepage.
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.
VersaTech KnowledgeBase

EPM-19 Programmer’s Reference Manual iv
Contents
Introduction ...................................................................................................................1
Related Documents.............................................................................................................1
System Resources and Maps.......................................................................................2
Memory Map ......................................................................................................................2
IRQ Map.............................................................................................................................2
I/O Map...............................................................................................................................3
FPGA Registers.............................................................................................................4
Accessing the FPGA...........................................................................................................4
FPGA I/O Space .................................................................................................................4
FPGA Register Map ...........................................................................................................5
FPGA Register Descriptions...............................................................................................6
Product Information Registers...............................................................................6
Status/Control Register.......................................................................................... 7
SPI Control Registers ............................................................................................8
SPI Data Registers...............................................................................................10
SPI Debug Control Register ................................................................................11
Miscellaneous FPGA Registers...........................................................................12
GPIO Registers....................................................................................................13
COM Port Register..............................................................................................19
FPGA Interrupt Interface..................................................................................................20
Programming Information for Hardware Interfaces..................................................21
PC/104 Expansion Bus.....................................................................................................21
PCI Express Ports (PCIe)..................................................................................................22
Processor WAKE# Capabilities........................................................................................22
GPIO Configuration
..........................................................................................................23
Industrial I/O Functions and SPI Interface.......................................................................25
Serial Ports........................................................................................................................26
COM3/COM4 Hardware Configuration..............................................................26
COM3/COM4 Software Configuration...............................................................26
Serial Port Assignment........................................................................................27
COM Ports (FIFO UARTs) .................................................................................28
COM Port Baud Rate Support.............................................................................28
Programmable LED..........................................................................................................30
Appendix A – References............................................................................................31
Tables
Table 1: Memory Map ........................................................................................................ 2

Contents
EPM-19 Programmer’s Reference Manual v
Table 2: IRQ Map ............................................................................................................... 2
Table 3: I/O Map................................................................................................................. 3
Table 4: FPGA I/O Map...................................................................................................... 4
Table 5: FPGA Register Map.............................................................................................. 5
Table 6: PCR – Product Code and LED Register............................................................... 6
Table 7: PSR – Product Status Register.............................................................................. 6
Table 8: SCR –Status/Control Register .............................................................................. 7
Table 12: SPI Control Register........................................................................................... 8
Table 13: SPI Status Register.............................................................................................. 9
Table 14: SPI – SPI Debug Control Register.................................................................... 11
Table 15: MISCR1 – Misc. Control Register #1 .............................................................. 12
Table 16: MISCSR2 – Misc. Control Register #2............................................................ 12
Table 17: AUXDIR – Auxiliary GPIO Direction Control Register.................................. 13
Table 18: AUXPOL – Auxiliary GPIO Polarity Control Register.................................... 14
Table 19: AUXOUT – Auxiliary GPIO I/O Output Value Register................................. 15
Table 20: AUXIN – Auxiliary GPIO Input Value Register.............................................. 16
Table 21: AUXIMASK – Auxiliary GPIO I/O Interrupt Mask and Control Register...... 17
Table 22: AUXISTAT– Auxiliary GPIO I/O Interrupt Mask and Status Register........... 18
Table 23: AUXIMODE1– Auxiliary GPIO I/O Mode Register ....................................... 19
Table 24: COMMODE – COM Port Mode Control Register........................................... 19
Table 25: PC/104 ISA I/O, IRQ, and Memory Resources................................................ 21
Table 26: PCIe Port Configuration ................................................................................... 22
Table 27: Vortex86DX2 GPIO Configuration.................................................................. 23
Table 28: GPIO Port 2 Direction Register – 0x9A........................................................... 27
Table 29: GPIO Port 2 Data Register – 0x7A................................................................... 27
Table 30: Recommended Serial Port Settings for Vortex86DX2 BIOS........................... 27
Table 31: COM Port PCI Address Map............................................................................ 29
Table 32: Baud Rates, Divisors, and Base Clock and Ratio Selection for UARTs.......... 30

EPM-19 Programmer’s Reference Manual 1
Introduction
This document provides information for users requiring register-level information for developing
applications with the EPM-19.
Related Documents
The following documents available are on the EPM-19 Product Support Web Page:
EPM-19 Hardware Reference Manual – provides information on the board’s hardware
features including connectors and all interfaces.
EPM-19-EBX-18 BIOS Reference Manual – provides information on accessing and
configuring settings in the BIOS Setup utility. All BIOS menus, submenus, and configuration
options are described.
VersaAPI Installation and Reference Guide – describes the shared library of API calls for
reading and controlling on-board devices on certain VersaLogic products.
1

EPM-19 Programmer’s Reference Manual 2
System Resources and Maps
Memory Map
Table 1: Memory Map
Address Range Description
00000000 – 0009FFFF
System RAM
000A0000 – 000AFFFF
EGA/VGA video memory
000B0000 – 000B7FFF
MDA RAM, Hercules graphics display RAM
000B8000 – 000BFFFF
CGA display RAM
000C0000 – 000C7FFF
EGA/VGA BIOS ROM
000C8000 – 000CFFFF
Boot ROM enable
000CC000 – 000CFFFF
Console redirection enable
000D0000 – 000D7FFF
Expansion ROM space
000D8000 – 000DBFFF
SPI Flash emulation floppy A enable
000DC000 – 000DFFFF
Expansion ROM space
000E0000 – 000EFFFF
USB Legacy SCSI ROM space
000F0000 – 000FFFFF
Motherboard BIOS
FEFBB400 – FEFBB4FF
On-board Ethernet adapter
FEFDB800 – FEFDBFFF
Standard enhanced PCI-to-USB host controller
FEFDBC00 – FEFDBCFF
Standard OpenHCD USB host controller
IRQ Map
Table 2: IRQ Map
IRQ Description
IRQ0
System timer
IRQ1
Keyboard controller
IRQ2
Cascade for IRQ8 – IRQ15
IRQ3
COM3 / Vortex86DX2 UART2
IRQ4
COM1 / Vortex86DX2 UART1
IRQ5
USB
IRQ6
USB
IRQ7
USB/Ethernet 10/100Mbit LAN
IRQ8
Real-time clock
IRQ9
Multimedia device
IRQ10
COM2 / Vortex86DX2 UART9
IRQ11
COM4 / Vortex86DX2 UART4
IRQ12
Mouse
IRQ13
Math coprocessor
IRQ14
Hard disk controller #1
IRQ15
Hard disk controller #2
2

System Resources and Maps
EPM-19 Programmer’s Reference Manual 3
I/O Map
Table 3: I/O Map
I/O Address Range Device/Owner
0000h – 000Fh
DMA 8237-1
0020h – 0021h
8259-1 programmable interrupt controller
0022h – 0023h
Indirect access registers (6117D configuration port)
002Eh – 002Fh
Forward to LPC bus
0040h – 0043h
8254 timer/counter
0048h – 004Bh
8254 counter (Reserved)
004Eh – 004Fh
Forward to LPC bus
0060h
Keyboard/Mouse data port
0061h
Port B + NMI control port
0062h – 0063h
8051 download 4K address counter
0064h
Keyboard/mouse command/status port
0065h
Watchdog0 reload counter
0066h
8051 download 8-bit data port
0067h
Watchdog1 reload counter
0068h – 006Dh
Watchdog1 control counter
0070h – 0071h
CMOS RAM port
0072h – 0075h
MTBF control register
0078h – 007Ch
GPIO port 0/1/2/3/4 default setup
0080h – 008Fh
DMA page register
0092h
System control register
0098h – 009Ch
GPIO direction control
00A0h – 00A1h
8259-2 programmable interrupt controller
00C0h – 00DFh
DMA 8237-2
00E0h – 00EFh
DOS 4G page access
0170h – 0177h
IDE1 (IRQ15)
01F0h – 01F7h
IDE0 (IRQ14)
02E8h – 02EFh
COM4 (IRQ11)
02F8h – 02FFh
COM2 (IRQ10)
0376h
IDE1 ATAPI device control write only register
03E8h – 03EFh
COM3 (IRQ3)
03F6h
IDE0 ATAPI device control write only register
03F8h – 03FFh
COM1 (IRQ4)
0480h – 048Fh
DMA high page register
0490h – 0499h
Instruction counter register
04D0h – 04D1h
8259 Edge/level control register
0CF8h – 0CFFh
PCI configuration port
DE00h – DEFFh
On-board LAN
FC00h – FC05h
SPI Flash BIOS control register
FC08h – FC0Dh
External SPI bus control register

EPM-19 Programmer’s Reference Manual 4
FPGA Registers
Accessing the FPGA
To access the FPGA, obtain the PCI Base Address Register value (BAR) and add it to the Offset
Address provided in Table 5 below. The PCI BAR can be obtained by reading the 32-bit
hexadecimal value (indicated by the 0x prefix) loaded in the PCI Configuration register at
address 0x10 for PCI Bus 02, Dev 04, Func 00.
The FPGA 32-bit PCI Configuration BAR would normally be read as 0x0000C801 (the LSB=1
simply enables I/O space and is not used with the base address calculation) if there are no other
PCI expansion cards plugged into the system (including PCIe Minicards) which equates to the
FPGA I/O Base Address at 0xC800. Add the Offset Address (found in column 1 of Table 5) to
obtain the I/O address for each 8-bit register.
Example:
FPGA I/O Base Address
0xC800
SPICONTROL offset address
+ 0x08
I/O address for accessing the SPICONTROL register
= 0xC808
FPGA I/O Space
The FPGA is mapped into I/O space on the PCI bus. Without any PCI expansion cards (PC/104-
Plus) in use, the FPGA is the only endpoint device on the PCI bus. The address range will be
mapped into the I/O Space, but because this is a PCI-based device, the base address is subject to
change with the use of PCIe or PCI expansion card use; therefore, it should be read each power
cycle for use in calculating the FPGA register addresses.
FPGA access: PCI I/O space
FPGA access size: All 8-bit (single byte) I/O accesses
FPGA Address Range: PCI I/O BAR for Bus 02/Device 04/Function 00 added to offset
range of 0x00 to 0x3FF (1 Kbyte window, but only addresses 0x00 to 0xFF contain utilized
registers).
The three 8254 timers only require four bytes of addressing and are located at the end of the
256-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. Table 4 lists the FPGA’s I/O map.
Table 4: FPGA I/O Map
Offset Address Range Device Size
0x00 – 0xFB
FPGA registers
252 bytes
0xFC – 0xFF
8254 timer address registers
4 bytes
3

FPGA Registers
EPM-19 Programmer’s Reference Manual 5
FPGA Register Map
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
WO Write-only (0 if read)
RSVD Reserved (registers implemented but not used)
Table 5: FPGA Register Map
Offset
Address Identifier D7 D6 D5 D4 D3 D2 D1 D0
0x00 PCR PLED EPM-19 PRODUCT_CODE = 0010010
0x01 PSR REV_LEVEL RSVD 0 0
0x02 SCR 0 0 0 DEBUG_LED RSVD 0 0 0
0x03 TICR RSVD RSVD RSVD RSVD 0 IMSK_TC5 IMSK_TC4 IMSK_TC3
0x04 TISR INTRTEST TMRTEST TMRIN4 TMRIN3 0 ISTAT_TC5 ISTAT_TC4 ISTAT_TC3
0x05 TCR TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL TMROCTST TMRFULL
0x06 Reserved 0 0 0 0 0 0 0 0
0x07 Reserved 0 0 0 0 0 0 0 0
0x08 SPICONTROL CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
0x09 SPISTATUS RSVD RSVD SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY
0x0A SPIDATA0 MSB LSB
0x0B SPIDATA1 MSB LSB
0x0C SPIDATA2 MSB LSB
0x0D SPIDATA3 MSB LSB
0x0E SPI 0 MUXSEL2 MUXSEL1 MUXSEL0 0 0 SPILB 0
0x0F MISCSR1 0 0 0 0 0 0 0 0
0x11 MISCSR2 NO_BATT W_DISABLE 0 PBRST 0 0 0 USB_OBDIS
0x21 AUXDIR DIR_GPIO8 DIR_GPIO7 DIR_GPIO6 DIR_GPIO5 DIR_GPIO4 DIR_GPIO3 DIR_GPIO2 DIR_GPIO1
0x22 AUXPOL POL_GPIO8 POL_GPIO7 POL_GPIO6 POL_GPIO5 POL_GPIO4 POL_GPIO3 POL_GPIO2 POL_GPIO1
0x23 AUXOUT OUT_GPIO8 OUT_GPIO7 OUT_GPIO6 OUT_GPIO5 OUT_GPIO4 OUT_GPIO3 OUT_GPIO2 OUT_GPIO1
0x24 AUXIN IN_GPIO8 IN_GPIO7 IN_GPIO6 IN_GPIO5 IN_GPIO4 IN_GPIO3 IN_GPIO2 IN_GPIO1
0x25 AUXIMASK
IMASK_
GPIO8
IMASK_
PIO7
IMASK_
GPIO6
IMASK_
GPIO5
IMASK_
GPIO4
IMASK_
GPIO3
IMASK_
GPIO2
IMASK_
GPIO1
0x26 AUXISTAT
ISTAT_
GPIO8
ISTAT_
PIO7
ISTAT_
GPIO6
ISTAT_
GPIO5
ISTAT_
GPIO4
ISTAT_
GPIO3
ISTAT_
GPIO2
ISTAT_
GPIO1
0x27 AUXMODE1
MODE_
GPIO8
MODE_
PIO7
MODE_
GPIO6
MODE_
GPIO5
MODE_
GPIO4
MODE_
GPIO3
MODE_
GPIO2
MODE_
GPIO1
0x40 COMMODE 0 0 0 0 COM4_TXEN COM3_TXEN 0 0
0xFC
8254 Timer
Address 0
MSB ————— —————— ————— ————— LSB
0xFD
8254 Timer
Address 1
MSB ————— —————— ————— ————— LSB
0xFE
8254 Timer
Address 2
MSB ————— —————— ————— ————— LSB
0xFF
8254 Timer
Address 3
MSB ————— —————— ————— ————— LSB

FPGA Registers
EPM-19 Programmer’s Reference Manual 6
FPGA Register Descriptions
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
WO Write-only (0 if read)
RSVD Reserved (registers implemented but not used)
PRODUCT INFORMATION REGISTERS
The FPGA register at offset 0x00 (PCR VersaReg) provides read access to the product code. At
offset 0x01 (PSR VersaReg), the revision level can be read.
Table 6: PCR – Product Code and LED Register
Bit
Identifier
Access
Default
Description
7 PLED R/W 0 Drives the programmable LED on the paddleboard. 0 – LED is off (default)
1 – LED is on (can be used by software)
6-0
PRODUCT_CODE
RO
0010010
Product Code for the EPM-19 (0x12)
Table 7: PSR – Product Status Register
Bit Identifier Access Default Description
7:3 REV_LEVEL[4:0] RO N/A
Revision level of the PLD (incremented every FPGA release)
0 – Indicates production release revision level when BETA
status bit (bit 0) is set to ‘0’
1 – Indicates development release revision level when BETA
status bit (bit 0) is set to ‘1’
2
Reserved
RO
1
Reserved. Writes are ignored; reads always return 1.
1
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
0
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.

FPGA Registers
EPM-19 Programmer’s Reference Manual 7
STATUS/CONTROL REGISTER
Table 8: SCR –Status/Control Register
Bit Identifier Access Default Description
7 Reserved RO N/A Reserved. Writes are ignored; reads always return 0.
6
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
5
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
4 DEBUG_LED R/W 1 Debug LED (controls the blue LED): 0 – LED is off and follows its primary function (MSATA_DAS)
1 – LED is on (indicates FPGA is programmed by default)
3
Reserved
RSVD
N/A
Reserved. Writes are ignored; reads always return 0.
2
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
1 Reserved RO N/A Reserved. Writes are ignored; reads always return 0.
0
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.

FPGA Registers
EPM-19 Programmer’s Reference Manual 8
SPI CONTROL REGISTERS
This section describes the SPI registers for the EPM-19. In this section, the term “BAR” refers
to the PCI Base Address Register value. Refer to the section titled Accessing the FPGA on page
4 for information on determining the values of the BAR and the Offset address.
SPICONTROL (Read/Write) BAR + Offset 08h
D7 D6 D5 D4 D3 D2 D1 D0
CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
Table 9: SPI Control Register
Bit Mnemonic Description
D7 CPOL
SPI Clock Polarity – Sets the SCLK idle state.
0 –SCLK idles low
1 –SCLK idles high
D6 CPHA SPI Clock Phase – Sets the SCLK edge on which valid data will be read. 0 – Data read on rising edge
1 – Data read on falling edge
D5-D4 SPILEN(1:0)
SPI Frame Length – Sets the SPI frame length. This selection works in manual and auto
slave select modes.
SPILEN1 SPILEN0 Frame Length
0 0 8-bit
0 1 16-bit
1 0 24-bit
1 1 32-bit
D3 MAN_SS
SPI Manual Slave Select Mode – This bit determines whether the slave select lines are
controlled through the user software or are automatically controlled by a write operation to
SPIDATA3. If MAN_SS = 0, then the slave select operates automatically; if MAN_SS = 1,
then the slave select line is controlled manually through SPICONTROL bits SS2, SS1,
and SS0.
0 – Automatic, default
1 – Manual
D2-D0 SS(2:0)
SPI Slave Select –These bits select which slave select will be asserted. The SSx# pin
on the EPM-19 will be directly controlled by these bits when MAN_SS = 1.
SS2
SS1
SS0
EPM-19 Slave Select
0 0 0 None N/A
0 0 1 SS#0 SPX device 1
0 1 0 SS#1 SPX device 2
0 1 1 None N/A
1 0 0 None N/A
1 0 1 None N/A
1 1 0 None N/A
1 1 1 None N/A

FPGA Registers
EPM-19 Programmer’s Reference Manual 9
SPISTATUS (Read/Write) BAR + Offset 09h
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY
Table 10: SPI Status Register
Bit Mnemonic Description
D7-D6
Reserved
Reserved
D5-D4 SPICLK(1:0)
SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0 Frequency
0 0 1.042 MHz
0 1 2.083 MHz
1 0 4.167 MHz
1 1 8.333 MHz
D3 HW_IRQ_EN
Hardware IRQ Enable – Enables or disables the use of the FPGA interrupt by an SPI
device.
0 – SPI interrupt disabled, default
1 – SPI interrupt enabled – passed to FPGA interrupt output
D2 LSBIT_1ST
SPI Shift Direction – Controls the SPI shift direction of the SPIDATA registers. The
direction can be shifted toward the least significant bit or the most significant bit.
0 – SPIDATA data is left-shifted (MSB first), default
1 – SPIDATA data is right-shifted (LSB first)
D1 HW_INT
SPI Device Interrupt State – This bit is a status flag that indicates when the hardware
SPX signal SINT# is asserted.
0 – Hardware interrupt on SINT# is de-asserted
1 – Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device’s interrupt is cleared.
D0 BUSY
SPI Busy Flag – This bit is a status flag that indicates when an SPI transaction is
underway.
0 – SPI bus idle
1 – SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.

FPGA Registers
EPM-19 Programmer’s Reference Manual 10
SPI DATA REGISTERS
SPIDATA0 (Read/Write) BAR + Offset 0Ah
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA1 (Read/Write) BAR + Offset 0Bh
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA2 (Read/Write) BAR + Offset 0Ch
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA3 (Read/Write) BAR + Offset 0Dh
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this
register initiates the SPI clock and, if the MAN_SS bit = 0, also asserts a slave select to begin an
SPI bus transaction. Increasing frame sizes from 8-bit use the lowest address for the least
significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSB
of SPIDATA3 is sent first, and received data will be shifted into the LSB of the selected frame
size set in the SPILEN field. When LSBIT_1ST = 1, the LSB of the selected frame size is sent
first, and the received data will be shifted into the MSB of SPIDATA3.

FPGA Registers
EPM-19 Programmer’s Reference Manual 11
SPI DEBUG CONTROL REGISTER
Table 11: SPI – SPI Debug Control Register
Bit Identifier Access Default Description
7 Reserved RO 0 Reserved – Writes are ignored. Reads always return 0
6-4 MUXSEL(2:0) R/W 000
mSATA/PCIe Mux Selection for Minicard Slot (and 2nd SATA
connector):
•000 – Select mSATA using only pin 43 (MSATA_DETECT).
This is an Intel-mode that is reliable for PCIe Minicards but not
for mSATA modules that inadvertently ground this signal. This
signal is purposely pulled low by the FPGA to avoid
accidentally switching the SATA channel when no mSATA or
PCIe Minicard is present. See the Minicard description for
more info.
•001 – Use only Pin 51 (PRES_DISABLE2#). This is the
default method and is defined in the Draft mSATA spec but
some Minicards use it as a second Wireless disable.
•010 – Use either Pin 43 or Pin 51. This will work just like 001
because Pin 43 is disabled by an FPGA pull-down.
•011 – Force PCIe mode on the Minicard
•100 – Force mSATA mode on the Minicard.
•101 – Undefined (same as 000)
•110 – Undefined (same as 000)
•111 – Undefined (same as 000)
Note: When the Minicard uses PCIe, the SATA channel
automatically switches to the SATA connector.
3
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
2
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
1 SPILB R/W 0
Debug/Test Only: Used to loop SPI output data back to the input
(debug/test mode).
0 – Normal operation
1 – Loop SPI output data back to the SPI input data (data output
still active)
0
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.

FPGA Registers
EPM-19 Programmer’s Reference Manual 12
MISCELLANEOUS FPGAREGISTERS
Table 12: MISCR1 – Misc. Control Register #1
Bit Identifier Access Default Description
7 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
6
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
5
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
4 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
3
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
2
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
1 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
0
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
Table 13: MISCSR2 – Misc. Control Register #2
Bit
Identifier
Access
Default
Description (Note)
7 NO_BATT RO N/A Indicates whether the V2 jumper is set to use a battery: 0 – Using the RTC Battery
1 – Not using the RTC Battery
6 W_DISABLE R/W 0
Controls the W_DISABLE (wireless disable) signal going to the
PCIe Minicard:
0 – W_DISABLE signal is not asserted (enabled)
1 – W_DISABLE signal is asserted (disabled)
There are other control sources that can be configured to control
this signal and if enabled the control becomes the “OR” of all
sources.
5
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
4
PBRST
WO
0
Writing a 1 to this bit initiates a reset.
3 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
2
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
1
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
0 USB_OBDIS R/W 0
Disable control for the on-board USB port VBUS power switches
(there are two with a common overcurrent):
0 – VBUS power switches are enabled
1 – VBUS power switched are disabled.
The I2164 power switches latch-off in overcurrent and can only be
re-enabled by a power-cycle or by setting this bit to a ‘1 and then a
‘0’ with at least 1 ms in between.
Note: This is a register in the always-on power well of the FPGA. It will hold its state during reboots and can only be
reset by a power cycle. It is primarily used for control signals for the always-powered Ethernet controllers and the USB
hubs.

FPGA Registers
EPM-19 Programmer’s Reference Manual 13
GPIO REGISTERS
AUXDIR
This register controls the direction of the eight GPIO signals.
Table 14: AUXDIR – Auxiliary GPIO Direction Control Register
Bit Identifier Access Default Description
7 DIR_GPIO8 R/W 0 Sets the direction of GPIO_8 0 – Input
1 – Output
6 DIR_GPIO7 R/W 0 Sets the direction of GPIO_7 0 – Input
1 – Output
5 DIR_GPIO6 R/W 0 Sets the direction of GPIO_6 0 – Input
1 – Output
4 DIR_GPIO5 R/W 0 Sets the direction of GPIO_5 0 – Input
1 – Output
3 DIR_GPIO4 R/W 0 Sets the direction of GPIO_4 0 – Input
1 – Output
2 DIR_GPIO3 R/W 0 Sets the direction of GPIO_3 0 – Input
1 – Output
1 DIR_GPIO2 R/W 0 Sets the direction of GPIO_2 0 – Input
1 – Output
0 DIR_GPIO1 R/W 0 Sets the direction of GPIO_1 0 – Input
1 – Output

FPGA Registers
EPM-19 Programmer’s Reference Manual 14
AUXPOL
This register controls the polarity of the eight GPIO signals.
Table 15: AUXPOL – Auxiliary GPIO Polarity Control Register
Bit Identifier Access Default Description
7 POL_GPIO8 R/W 0 Sets the polarity of GPIO_8 (Note) 0 – No polarity inversion
1 – Invert polarity
6 POL_GPIO7 R/W 0 Sets the polarity of GPIO_7 (Note) 0 – No polarity inversion
1 – Invert polarity
5 POL_GPIO6 R/W 0 Sets the polarity of GPIO_6 (Note) 0 – No polarity inversion
1 – Invert polarity
4 POL_GPIO5 R/W 0 Sets the polarity of GPIO_5 (Note) 0 – No polarity inversion
1 – Invert polarity
3 POL_GPIO4 R/W 0 Sets the polarity of GPIO_4 (Note) 0 – No polarity inversion
1 – Invert polarity
2 POL_GPIO3 R/W 0 Sets the polarity of GPIO_3 (Note) 0 – No polarity inversion
1 – Invert polarity
1 POL_GPIO2 R/W 0 Sets the polarity of GPIO_2 (Note) 0 – No polarity inversion
1 – Invert polarity
0 POL_GPIO1 R/W 0 Sets the polarity of GPIO_1 (Note) 0 – No polarity inversion
1 – Invert polarity
Note: This impacts the polarity as well as the interrupt status edge used.

FPGA Registers
EPM-19 Programmer’s Reference Manual 15
AUXOUT
This register sets the GPIO output value. This value will only set the actual output if the GPIO
direction is set as an output. Reading this register does not return the actual input value of the
GPIO; use the AUXIN register for that function. This register can be used to detect input/output
conflicts.
Table 16: AUXOUT – Auxiliary GPIO I/O Output Value Register
Bit Identifier Access Default Description
7 OUT_GPIO8 R/W 0 Sets the GPIO_8 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
6 OUT_GPIO7 R/W 0 Sets the GPIO_7 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
5 OUT_GPIO6 R/W 0 Sets the GPIO_6 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
4 OUT_GPIO5 R/W 0 Sets the GPIO_5 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
3 OUT_GPIO4 R/W 0 Sets the GPIO_4 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
2 OUT_GPIO3 R/W 0 Sets the GPIO_3 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
1 OUT_GPIO2 R/W 0 Sets the GPIO_2 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
0 OUT_GPIO1 R/W 0 Sets the GPIO_1 output 0 – De-asserts the output (0 if polarity not inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)