Aim AMCX1553 User manual

V01.11 Rev. A
July 2016
AMCX1553
Hardware
Manual
Single/Dual/Quad Stream MIL-STD-1553
PMC Interface Module

AMCX1553-1T/2T Hardware Manual
i
AMCX1553
Single/Dual/Quad Stream
MIL-STD-1553
PMC Interface Module
V01.11 Rev. A
July 2016
AIM No.
60-11A4x-16-0111-A
Hardware
Manual

AMCX1553 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
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D-79111 Freiburg / Germany
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AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
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[e-mail]
AIM GmbH –Munich Sales Office
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D-80689 München / Germany
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AIM USA LLC
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Fax [phone]
[e-mail]
© AIM GmbH 2016
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by
implication in connection therewith. Specifications are subject to change without notice.

AMCX1553 Hardware Manual
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DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 Rev-A
17.05.2011
D. Bau
First Released Version
V01.01 Rev-A
26.10.2011
D. Bau
Figure 3-1 replaced
V01.02 Rev-A
19.12.2011
D. Bau
Additional information in the chapter
Installation
V01.03 Rev-A
22.10.2012
D. Bau
Variable Trigger pulse length
Standard Operating Temperature
V01.10 Rev-A
06.05.2013
D. Bau
Conduction Cooled Versions included
Power Consumption 5V/12V
Rear IO varistor hint
Termination for unused bus
Format of the IRIG B decoder/encoder
V01.11 Rev-A
12.07.2016
D. Bau
New layout
Corrections on the discrete section
IRIG- In/Out voltage corrections
Certificate of Volatility

AMCX1553 Hardware Manual
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AMCX1553 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1INTRODUCTION .....................................................................................................1
1.1 General ...............................................................................................................1
1.2 How This Manual is Organized............................................................................2
1.3 Applicable Documents.........................................................................................2
1.3.1 Industry Documents ........................................................................................2
1.3.2 Product Specific AIM Documents....................................................................2
2INSTALLATION.......................................................................................................3
2.1 Preparation and Precaution for Installation..........................................................3
2.2 Installation Instructions........................................................................................3
2.3 Connecting to other Devices................................................................................5
2.3.1 MIL-STD-1553-A/B Dual Channel Interface Connector ...................................6
2.3.2 MILbus Coupling Modes..................................................................................7
2.3.3 Trigger and IRIG connector.............................................................................7
2.3.4 Thermal Conduction Cooling...........................................................................7
2.3.5 AMCX1553-n Rear-IO Interface ......................................................................8
3STRUCTURE OF THE AMCX1553-N......................................................................9
3.1 PCI bus and BIU-I/O FPGA ...............................................................................11
3.2 Global RAM Interface and Arbitration ................................................................11
3.3 Boot Function....................................................................................................11
3.4 Global RAM.......................................................................................................11
3.5 BIU Section .......................................................................................................11
3.6 BIU-Processor (BIP)..........................................................................................11
3.7 DMA Engine......................................................................................................12
3.8 Physical Bus Interface MIL-STD-1553 Board.....................................................12
3.9 MIL-STD-1553 Encoder.....................................................................................12
3.10 MIL-STD-1553 Decoder.....................................................................................12
3.11 External Trigger Inputs and Outputs..................................................................13
3.12 User programmable Discrete I/O (GPIO)...........................................................15
3.13 IRIG- and Time Code Section............................................................................17
3.13.1 Time Code Encoder/Decoder........................................................................17
3.13.2 Time Tag Methods ........................................................................................17
3.14 Voltage Supplies................................................................................................18
3.14.1 Standard Voltage Supply...............................................................................18
4TECHNICAL DATA ...............................................................................................19
5NOTES ..................................................................................................................23
5.1 Acronyms ..........................................................................................................23
6CERTIFICATE OF VOLATILITY............................................................................25

AMCX1553 Hardware Manual
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LIST OF TABLES
Table Title Page
Table 2.1: Pin Assignment Channel 1 and 2...........................................................................6
Table 2.2: Pin Assignment Channel 3 and 4 (Only AMCX1553-4)..........................................6
Table 2.3: Pin Assignment PMC Rear I/O ..............................................................................8
Table 3.1: IRIG-B Binary Coded Time Tag...........................................................................17
LIST OF FIGURES
Figure Title Page
Figure 2.1: Installing an Air Cooled AMCX1553-n Mezzanine Module....................................4
Figure 2.2: Installing a Conduction Cooled AMCX1553-n-CC Mezzanine Module..................5
Figure 2.3: Front Panel...........................................................................................................6
Figure 2.4: Pinout DSUB for Trigger and IRIG connector .......................................................7
Figure 3.1: Block Diagram of AMCX1553-n..........................................................................10
Figure 3.2: Trigger IN of AMCX1553-n.................................................................................13
Figure 3.3: Trigger Out of AMCX1553-n...............................................................................14
Figure 3.4: GPI/O AMCX1553-n circuitry..............................................................................15
Figure 3.5: GPIO Protection with external resistor................................................................16

1. Introduction
AMCX1553 Hardware Manual
1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the AMCX1553-n and AMCX1553-n-
CC Mezzanine Cards. The document covers the hardware installation, the board connections
the technical data and a general description of the hardware architecture. For programming
information please refer to the documents listed in the ‘Applicable Documents’ section.
The AMCX1553 modules are members of AIM's family of advanced PCI mezzanine cards for
analyzing, simulating, monitoring and testing of avionic databus systems. The PMC module is
designed to be plugged on a host carrier board to adapt to busses like standard PCI or cPCI, or
on an embedded host computer with PMC ports.
The AMCX1553 modules are used to simulate, monitor and inject protocol errors of MIL-STD-
1553A/B based databus systems. The mezzanine card is available as air cooled AMCX1553-n
or conduction cooled AMCX1553-n-CC variant. The functionality of both variants is nearly equal,
except that the Conduction Cooled Mezzanine Card does not implement any Frontpanel
Interface provisions rather than the Rear IO interface functionality. That means all interface
signals of the AMCX1553-n-CC module are routed to the Rear-IO connectors P14. The
Conduction Cooled Thermal Interface is in conformance with the CCPMC specification. To
simplify the explanation, the further description uses only the AMCX1553-n expression, even if
both variants (AMCX1553-n/ AMCX1553-n-CC) are referenced.
The index n in AMCX1553-n stands for the bus channel quantity (AMCX1553-1/2/4) and offers
an interface for up to four dual-redundant MIL-STD-1553 bus channels. Furthermore the
interface implements trigger IN/OUT functions for Bus Controller (BC), Remote Terminal (RT)
and Bus Monitor (BM), as well as 8 user definable Discrete I/O signals. An additional free
wheeling IRIG-B time code generator allows the user to synchronize to either the self generated
time code or the time code of an external board with a resolution of 1ppm.
Adjusted by assembly configuration, Transformer coupling and Direct coupling for one, two or
four dual redundant MIL-STD-1553A/B databus connections are available at the external
interface connector or at the back panel connector. A standard breakout cable is available,
which includes the primary and secondary transformer coupled MIL-STD-1553 signals for
single, dual and quad stream boards.
The hardware architecture provides ample resources (i.e. processing capability and memory) to
guarantee, that all specified interface functions are available concurrently and to full
performance specifications.
The advanced architecture uses up to two processors for the MIL-STD-1553A/B streams. A
powerful Memory Arbiter and PCI-Express Controller in combination with a external PCIe to PCI
bridge is implemented in a Field Programmable Gate Array (FPGA). This FPGA supports both,
the interface to the application and driver software tasks running on the host computer and
assists the communication for data transfer. This feature expands the capability of the
AMCX1553 module to that of a high level instrument.
To fulfill the real-time requirements of a typical avionic type databus system, a high performance
32bit RISC processor (BIP) is implemented for each Bus Interface Unit (BIU).
A free wheeling IRIG-B Time code Encoder/Decoder is implemented on the AMCX1553 to
satisfy the requirements of 'multi-channel time tag synchronization' on the system level. The

1. Introduction
AMCX1553 Hardware Manual
2
IRIG-B compatible amplitude modulated sine wave output allows the synchronization of any
external module implementing IRIG-B time stamping.
1.2 How This Manual is Organized
Section 1 - INTRODUCTION - contains an overview of this manual.
Section 2 - INSTALLATION - describes the steps required to install the AMCX1553 device,
and connect the device to other external interfaces including the MIL-STD-1553
Bus, IRIG-B and triggers.
Section 3 - STRUCTURE OF THE AMCX1553-N - describes the physical hardware
interfaces on the AMCX1553 using a block diagram and a description of each
main component
Section 4 - TECHNICAL DATA - describes the technical specification of the
AMCX1553.
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent that
they are referenced herein. In the event of conflict between the documents referenced and the
contents of this document, the contents of this document shall have precedence.
1.3.1 Industry Documents
[1] MIL-STD-1553B, Department of Defence Interface Standard for Digital Time
Division Command/Response Multiplex Data Bus, Notice 1-4, January 1996
[2] Draft Standard for CMC, P1386 / Draft 2.4, January 12, 2001
[3] Draft Standard for PMC, P1386 / Draft 2.4, January 12, 2001
[4] PCI LOCAL BUS Specification, Revision 2.1, June 1, 1995
1.3.2 Product Specific AIM Documents
[5] AIM - Reference Manual AMCX1553 Application Interface Library. Detailed description
of the programming interface between the Host Carrier board and the on-board driver
software.