Aim AMCX429 User manual

Hardware
Manual
V01.13 Rev. A
February 2019
AMCX429
4/8/16/32 Channel ARINC429
PMC Interface Module

AMCX429 Hardware Manual
i
AMCX429
ARINC429 Test and Simulation Module
With 4/8/16/32 channels
for
PMC Interface Modules
V01.13 Rev. A
February 2019
AIM No.
60-12A3x-16-0113-A
60-12A5x-16-0113-A
Hardware
Manual

AMCX429 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
Sasbacher Str. 2
D-79111 Freiburg / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
Fax [phone]
[email protected]
AIM GmbH –Munich Sales Office
Terofalstr. 23a
D-80689 München / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM USA LLC
Seven Neshaminy Interplex
Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[email protected]
© AIM GmbH 2019
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted
by implication in connection therewith. Specifications are subject to change without
notice.

AMCX429 Hardware Manual
iii
DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 Rev. A
20.02.2012
M. Mutter
First Released Version
V01.01 Rev. A
04.01.2013
M. Mutter
- Discrete IO description for
AMCX429-4/8/16 corrected
- Power consumption added
- Weight information added
- Cosmetically changes chapter 4/5
V01.10 Rev. A
06.05.2013
M. Mutter
CC conduction cooled version
included
All characteristics are equal to the
standard version unless otherwise
stated
V01.10 Rev. B
13.05.2014
M. Lamp
Wrong AIM USA Tel. No.
V01.11 Rev. A
19.08.2015
B. Schweitzer
Modify Transmitter Technical Data
V01.12 Rev. A
13.01.2017
M. Lamp/
S. Thota
New Layout, Discrete IO description,
add memory volatility page,
Rework technical data with GOST
Variant.
V01.13 Rev. A
01.02.2019
M.Schuessele
Update Power Consumption section

AMCX429 Hardware Manual
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AMCX429 Hardware Manual
v
TABLE OF CONTENTS
Section Title Page
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is organized..................................................................................................2
1.3 Applicable Documents ..............................................................................................................2
1.3.1 Industry Documents.................................................................................................................3
1.3.2 Product Specific Documents....................................................................................................3
2Installation ..............................................................................................................5
2.1 Preparation and Precaution for Installation ............................................................................5
2.2 Installation Instructions.............................................................................................................5
2.3 Connecting to Other Devices....................................................................................................8
2.3.1 AMCX429-4/8/16 Front panel Connector Pinout.....................................................................9
2.3.2 AMCX429-32 Front panel Connector Pinout.........................................................................10
3Structure of the AMCX429...................................................................................11
3.1 PCI bus and BIU-I/O FPGA......................................................................................................12
3.1.1 Global RAM Interface and Arbitration....................................................................................12
3.1.2 Boot up...................................................................................................................................12
3.2 Global RAM...............................................................................................................................12
3.3 BIU-Processor (BIP).................................................................................................................12
3.4 ARINC-429 Encoder .................................................................................................................13
3.5 ARINC-429 Decoder .................................................................................................................13
3.6 External Trigger Inputs and Outputs .....................................................................................13
3.7 User Programmable Discrete I/Os..........................................................................................14
3.8 IRIG- and Time Code Section..................................................................................................16
3.8.1 Time Code Encoder/Decoder ................................................................................................16
3.8.2 Time Tag Methods.................................................................................................................16
4Technical Data......................................................................................................17
5Appendix...............................................................................................................21
5.1 Front Connector (Ordering Information) ...............................................................................21
5.2 Rear IO Pin Assignment PMC Connectors............................................................................22
5.3 Certificate of Volatility.............................................................................................................24
6Notes .....................................................................................................................25
6.1 Acronyms..................................................................................................................................25

AMCX429 Hardware Manual
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LIST OF TABLES
Table Title Page
Table 2-1: Pin assignment AMCX429-4/8/16.............................................................. 9
Table 2-2: Pin assignment AMCX429-32 ..................................................................10
Table 3-1: IRIG-B: Binary Coded Time Tag...............................................................16
Table 5-1: Rear I/O Connector AMCX429-32............................................................22
Table 5-2: Rear I/O Connector AMCX429-4/8/16......................................................23
LIST OF FIGURES
Figure Title Page
Figure 2-1: Installing an AMCX429 Mezzanine Module.............................................. 6
Figure 2-2: Installing a Conduction Cooled AMCX429-n-CC Mezzanine Module....... 7
Figure 2-3: Front Connector Pin Orientation............................................................... 8
Figure 3-1: Block Diagram of AMCX429....................................................................11
Figure 3-2: GPI/O AMCX429-x circuitry.....................................................................14
Figure 3-3: GPIO Protection with external resistor ....................................................15

1. Introduction
AMCX429 Hardware Manual
1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the AMCX429-4/8/16/32 PCI
Mezzanine Card, consisting of the AMCX429-4/8/16/32 electronic module. The document
covers the hardware installation, the board connections, and a general description of the
hardware architecture and the technical data of the AMCX429. For programming
information please refer to the according documents listed in the 'Applicable Documents'
section.
The AMCX429 module is a member of AIM's family of advanced PMC-Bus modules for
analysing, simulating, monitoring and testing of avionics data bus systems.
The PMC module is designed to be plugged on either, a host carrier board to adapt to
standard PCI, VME or CPCI busses, or on an embedded host computer with PMC ports.
The AMCX429 provides four, eight, sixteen or thirty-two fully configurable ARINC429
channels whereby the four and eight channel board is an assembly variant of the
AMCX429 sixteen channel board. Each channel can be individually configured by
software as a transmit or receive channel with shared front panel connector outputs and
inputs.
Due to desiderate amount of IO pins, the IRIG Input and Output on AMCX429-32 variant
is only available on Front-IO. The Trigger feature is limited to only one Trigger Output line
on Front panel Connector on AMCX429-32. Trigger Inputs and Discrete IO are not
supported on 32 Channel ARINC mezzanine modules.
The conduction cooled AMCX429-32 version has no Trigger IOs at all due to the limited
pin count of the Rear IO connector.
On transmit channels the AMCX429 acts as an autonomously operating bus traffic
simulator, supporting multiple modes of transmission sequencing. Full error injection
capabilities are available, whereby the error injection is programmable individually for
each channel and label. For a special transmission operating mode the parity bit can be
used alternately as an additional data bit. The rise and fall time of the bus signals are
individually programmable by software for each transmit channel.
For the receive channels the AMCX429 provides an advanced monitor and analyser
function, with unique on-board error detection, triggering and filtering capabilities.
Both functions are available concurrentlyand independent from each other. Thehardware
architecture provides resources to guarantee the performance of one function is not
affected by the current load of other function. The rise and fall time of the bus signals are
individually programmable for each receive channel. To adapt todifferent transmit speeds
the transmission rate can be varied in discrete steps between approximately 90 and
120Kbit on the high speed bus and between 11.5 and 16.0Kbit on the low speed lines.
The discrete steps are global for all channels.

1. Introduction
AMCX429 Hardware Manual
2
The hardware architecture provides ample resources (i.e. processing capability and
memory) to guarantee, that all specified interface functions are available concurrently and
to full performance specifications.
The advanced architecture uses a special processor for the ARINC-429 stream. A
powerful PCI Controller and Memory Arbiter are implemented in a Field Programmable
Gate Array (FPGA). This FPGA supports both, the interface to the application and driver
software tasks running on the host computer and assists the communication for data
transfer. This feature expands the capability of the AMCX429 module to that of a high
level instrument. To fulfil the real-time requirements of a typical avionic type data bus
system, a high performance 32bit RISC processor (BIP) is implemented.
A free wheeling IRIG-B Time code Encoder/Decoder is implemented on the AMCX429 to
satisfy the requirements of 'multi-channel time tag synchronization' on the system level.
The IRIG-B compatible amplitude modulated sine wave output allows the synchronization
of any external module implementing IRIG-B time stamping.
1.2 How This Manual is organized
This AMCX429 Hardware Manual is comprised of the following sections.
Section 1
INTRODUCTION - contains an overview of this manual.
Section 2
INSTALLATION - describes the steps required to install the AMCX429
device and connect the device to other external 429 interfaces, IRIG-B, and
triggers.
Section 3
STRUCTURE OF THE AMCX429 - describes the physical hardware
interfaces on the AMCX429 using a block diagram and a description of each
main component
Section 4
TECHNICAL DATA - describes the technical specification of the AMCX429.
Section 5
APPENDIX - additional Information
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents